[apple/xnu.git] / osfmk / i386 / cpuid.h

/*
 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */

/*
 * x86 CPU identification
 *
 */

#ifndef _MACHINE_CPUID_H_
#define _MACHINE_CPUID_H_

#include <sys/appleapiopts.h>

#ifdef __APPLE_API_PRIVATE

#define	CPUID_VID_INTEL		"GenuineIntel"
#define	CPUID_VID_AMD		"AuthenticAMD"

#define CPUID_VMM_ID_VMWARE		"VMwareVMware"
#define CPUID_VMM_ID_PARALLELS	"Parallels\0\0\0"

#define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"

#define _Bit(n)			(1ULL << n)
#define _HBit(n)		(1ULL << ((n)+32))

/*
 * The CPUID_FEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 1: 
 */
#define CPUID_FEATURE_FPU       _Bit(0)   /* Floating point unit on-chip */
#define CPUID_FEATURE_VME       _Bit(1)   /* Virtual Mode Extension */
#define CPUID_FEATURE_DE        _Bit(2)   /* Debugging Extension */
#define CPUID_FEATURE_PSE       _Bit(3)   /* Page Size Extension */
#define CPUID_FEATURE_TSC       _Bit(4)   /* Time Stamp Counter */
#define CPUID_FEATURE_MSR       _Bit(5)   /* Model Specific Registers */
#define CPUID_FEATURE_PAE       _Bit(6)   /* Physical Address Extension */
#define CPUID_FEATURE_MCE       _Bit(7)   /* Machine Check Exception */
#define CPUID_FEATURE_CX8       _Bit(8)   /* CMPXCHG8B */
#define CPUID_FEATURE_APIC      _Bit(9)   /* On-chip APIC */
#define CPUID_FEATURE_SEP       _Bit(11)  /* Fast System Call */
#define CPUID_FEATURE_MTRR      _Bit(12)  /* Memory Type Range Register */
#define CPUID_FEATURE_PGE       _Bit(13)  /* Page Global Enable */
#define CPUID_FEATURE_MCA       _Bit(14)  /* Machine Check Architecture */
#define CPUID_FEATURE_CMOV      _Bit(15)  /* Conditional Move Instruction */
#define CPUID_FEATURE_PAT       _Bit(16)  /* Page Attribute Table */
#define CPUID_FEATURE_PSE36     _Bit(17)  /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN       _Bit(18)  /* Processor Serial Number */
#define CPUID_FEATURE_CLFSH     _Bit(19)  /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS        _Bit(21)  /* Debug Store */
#define CPUID_FEATURE_ACPI      _Bit(22)  /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX       _Bit(23)  /* MMX supported */
#define CPUID_FEATURE_FXSR      _Bit(24)  /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE       _Bit(25)  /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2      _Bit(26)  /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS        _Bit(27)  /* Self-Snoop */
#define CPUID_FEATURE_HTT       _Bit(28)  /* Hyper-Threading Technology */
#define CPUID_FEATURE_TM        _Bit(29)  /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE       _Bit(31)  /* Pend Break Enable */
 
#define CPUID_FEATURE_SSE3      _HBit(0)  /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1)  /* PCLMULQDQ instruction */
#define CPUID_FEATURE_DTES64    _HBit(2)  /* 64-bit DS layout */
#define CPUID_FEATURE_MONITOR   _HBit(3)  /* Monitor/mwait */
#define CPUID_FEATURE_DSCPL     _HBit(4)  /* Debug Store CPL */
#define CPUID_FEATURE_VMX       _HBit(5)  /* VMX */
#define CPUID_FEATURE_SMX       _HBit(6)  /* SMX */
#define CPUID_FEATURE_EST       _HBit(7)  /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2       _HBit(8)  /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3     _HBit(9)  /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID       _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMA       _HBit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16      _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR      _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM      _HBit(15) /* Perf/Debug Capability MSR */

#define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA       _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1    _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2    _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIC    _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE     _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT    _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES       _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE     _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE   _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0	_HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16C	_HBit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRAND	_HBit(30) /* RDRAND instruction */
#define CPUID_FEATURE_VMM       _HBit(31) /* VMM (Hypervisor) present */

/*
 * Leaf 7, subleaf 0 additional features.
 * Bits returned in %ebx:%ecx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
 */
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)	/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_TSCOFF   _Bit(1)	/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1     _Bit(3)	/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLE      _Bit(4)	/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2     _Bit(5)	/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_SMEP     _Bit(7)	/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_BMI2     _Bit(8)	/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_ERMS     _Bit(9)	/* Enhanced Rep Movsb/Stosb */
#define CPUID_LEAF7_FEATURE_INVPCID  _Bit(10)	/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTM      _Bit(11)	/* RTM */
#define CPUID_LEAF7_FEATURE_RDSEED   _Bit(18)	/* RDSEED Instruction */
#define CPUID_LEAF7_FEATURE_ADX      _Bit(19)	/* ADX Instructions */
#define CPUID_LEAF7_FEATURE_SMAP     _Bit(20)	/* Supervisor Mode Access Protect */
#define CPUID_LEAF7_FEATURE_SGX      _Bit(2)	/* Software Guard eXtensions */
#define CPUID_LEAF7_FEATURE_PQM      _Bit(12)	/* Platform Qos Monitoring */
#define CPUID_LEAF7_FEATURE_FPU_CSDS _Bit(13)	/* FPU CS/DS deprecation */
#define CPUID_LEAF7_FEATURE_MPX      _Bit(14)	/* Memory Protection eXtensions */
#define CPUID_LEAF7_FEATURE_PQE      _Bit(15)	/* Platform Qos Enforcement */
#define CPUID_LEAF7_FEATURE_CLFSOPT  _Bit(23)	/* CLFSOPT */
#define CPUID_LEAF7_FEATURE_IPT      _Bit(25)	/* Intel Processor Trace */
#define CPUID_LEAF7_FEATURE_SHA      _Bit(29)	/* SHA instructions */

#define CPUID_LEAF7_FEATURE_PREFETCHWT1 _HBit(0)/* Prefetch Write/T1 hint */

/*
 * The CPUID_EXTFEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: 
 */
#define CPUID_EXTFEATURE_SYSCALL   _Bit(11)	/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD	   _Bit(20)	/* eXecute Disable */

#define CPUID_EXTFEATURE_1GBPAGE   _Bit(26)	/* 1GB pages */
#define CPUID_EXTFEATURE_RDTSCP	   _Bit(27)	/* RDTSCP */
#define CPUID_EXTFEATURE_EM64T	   _Bit(29)	/* Extended Mem 64 Technology */

#define CPUID_EXTFEATURE_LAHF	   _HBit(0)	/* LAFH/SAHF instructions */
#define CPUID_EXTFEATURE_LZCNT     _HBit(5)	/* LZCNT instruction */
#define CPUID_EXTFEATURE_PREFETCHW _HBit(8)	/* PREFETCHW instruction */

/*
 * The CPUID_EXTFEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: 
 */
#define CPUID_EXTFEATURE_TSCI      _Bit(8)	/* TSC Invariant */

/*
 * CPUID_X86_64_H_FEATURE_SUBSET and CPUID_X86_64_H_LEAF7_FEATURE_SUBSET
 * indicate the bitmask of features that must be present before the system
 * is eligible to run the "x86_64h" "Haswell feature subset" slice.
 */
#define CPUID_X86_64_H_FEATURE_SUBSET ( CPUID_FEATURE_FMA    | \
                                        CPUID_FEATURE_SSE4_2 | \
                                        CPUID_FEATURE_MOVBE  | \
                                        CPUID_FEATURE_POPCNT | \
                                        CPUID_FEATURE_AVX1_0   \
                                      )

#define CPUID_X86_64_H_EXTFEATURE_SUBSET ( CPUID_EXTFEATURE_LZCNT \
                                         )

#define CPUID_X86_64_H_LEAF7_FEATURE_SUBSET ( CPUID_LEAF7_FEATURE_BMI1 | \
                                              CPUID_LEAF7_FEATURE_AVX2 | \
                                              CPUID_LEAF7_FEATURE_BMI2   \
                                            )

#define	CPUID_CACHE_SIZE	16	/* Number of descriptor values */

#define CPUID_MWAIT_EXTENSION	_Bit(0)	/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK	_Bit(1)	/* interrupts are break events	   */

#define CPUID_MODEL_YONAH		0x0E
#define CPUID_MODEL_MEROM		0x0F
#define CPUID_MODEL_PENRYN		0x17
#define CPUID_MODEL_NEHALEM		0x1A
#define CPUID_MODEL_FIELDS		0x1E	/* Lynnfield, Clarksfield */
#define CPUID_MODEL_DALES		0x1F	/* Havendale, Auburndale */
#define CPUID_MODEL_NEHALEM_EX		0x2E
#define CPUID_MODEL_DALES_32NM		0x25	/* Clarkdale, Arrandale */
#define CPUID_MODEL_WESTMERE		0x2C	/* Gulftown, Westmere-EP/-WS */
#define CPUID_MODEL_WESTMERE_EX		0x2F
#define CPUID_MODEL_SANDYBRIDGE		0x2A
#define CPUID_MODEL_JAKETOWN		0x2D
#define CPUID_MODEL_IVYBRIDGE		0x3A
#define CPUID_MODEL_IVYBRIDGE_EP	0x3E
#define CPUID_MODEL_CRYSTALWELL		0x46
#define CPUID_MODEL_HASWELL		0x3C
#define CPUID_MODEL_HASWELL_EP		0x3F
#define CPUID_MODEL_HASWELL_ULT		0x45
#define CPUID_MODEL_BROADWELL		0x3D
#define CPUID_MODEL_BROADWELL_ULX	0x3D
#define CPUID_MODEL_BROADWELL_ULT	0x3D
#define CPUID_MODEL_BRYSTALWELL		0x47
#define CPUID_MODEL_SKYLAKE		0x4E
#define CPUID_MODEL_SKYLAKE_ULT		0x4E
#define CPUID_MODEL_SKYLAKE_ULX		0x4E
#define CPUID_MODEL_SKYLAKE_DT		0x5E

#define CPUID_VMM_FAMILY_UNKNOWN	0x0
#define CPUID_VMM_FAMILY_VMWARE		0x1
#define CPUID_VMM_FAMILY_PARALLELS	0x2

#ifndef ASSEMBLER
#include <stdint.h>
#include <mach/mach_types.h>
#include <kern/kern_types.h>
#include <mach/machine.h>


typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
static inline void
cpuid(uint32_t *data)
{
	__asm__ volatile ("cpuid"
		: "=a" (data[eax]),
		  "=b" (data[ebx]),
		  "=c" (data[ecx]),
		  "=d" (data[edx])
		: "a"  (data[eax]),
		  "b"  (data[ebx]),
		  "c"  (data[ecx]),
		  "d"  (data[edx]));
}

static inline void
do_cpuid(uint32_t selector, uint32_t *data)
{
	__asm__ volatile ("cpuid"
		: "=a" (data[0]),
		  "=b" (data[1]),
		  "=c" (data[2]),
		  "=d" (data[3])
		: "a"(selector),
		  "b" (0),
		  "c" (0),
		  "d" (0));
}

/*
 * Cache ID descriptor structure, used to parse CPUID leaf 2.
 * Note: not used in kernel.
 */
typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ; 
typedef struct {
	unsigned char	value;          /* Descriptor value */
	cache_type_t 	type;           /* Cache type */
	unsigned int 	size;           /* Cache size */
	unsigned int 	linesize;       /* Cache line size */
#ifdef KERNEL
	const char	*description;   /* Cache description */
#endif /* KERNEL */
} cpuid_cache_desc_t;  

#ifdef KERNEL
#define CACHE_DESC(value,type,size,linesize,text) \
	{ value, type, size, linesize, text }
#else
#define CACHE_DESC(value,type,size,linesize,text) \
	{ value, type, size, linesize }
#endif /* KERNEL */

/* Monitor/mwait Leaf: */
typedef struct {
	uint32_t	linesize_min;
	uint32_t	linesize_max;
	uint32_t	extensions;
	uint32_t	sub_Cstates;
} cpuid_mwait_leaf_t;

/* Thermal and Power Management Leaf: */
typedef struct {
	boolean_t	sensor;
	boolean_t	dynamic_acceleration;
	boolean_t	invariant_APIC_timer;
	boolean_t	core_power_limits;
	boolean_t	fine_grain_clock_mod;
	boolean_t	package_thermal_intr;
	uint32_t	thresholds;
	boolean_t	ACNT_MCNT;
	boolean_t	hardware_feedback;
	boolean_t	energy_policy;
} cpuid_thermal_leaf_t;


/* XSAVE Feature Leaf: */
typedef struct {
	uint32_t	extended_state[4];	/* eax .. edx */
} cpuid_xsave_leaf_t;


/* Architectural Performance Monitoring Leaf: */
typedef struct {
	uint8_t		version;
	uint8_t		number;
	uint8_t		width;
	uint8_t		events_number;
	uint32_t	events;
	uint8_t		fixed_number;
	uint8_t		fixed_width;
} cpuid_arch_perf_leaf_t;

/* The TSC to Core Crystal (RefCLK) Clock Information leaf */
typedef struct {
	uint32_t	numerator;
	uint32_t	denominator;
} cpuid_tsc_leaf_t;

/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
typedef struct {
	char		cpuid_vendor[16];
	char		cpuid_brand_string[48];
	const char	*cpuid_model_string;

	cpu_type_t	cpuid_type;	/* this is *not* a cpu_type_t in our <mach/machine.h> */
	uint8_t		cpuid_family;
	uint8_t		cpuid_model;
	uint8_t		cpuid_extmodel;
	uint8_t		cpuid_extfamily;
	uint8_t		cpuid_stepping;
	uint64_t	cpuid_features;
	uint64_t	cpuid_extfeatures;
	uint32_t	cpuid_signature;
	uint8_t   	cpuid_brand; 
	uint8_t		cpuid_processor_flag;
	
	uint32_t	cache_size[LCACHE_MAX];
	uint32_t	cache_linesize;

	uint8_t		cache_info[64];    /* list of cache descriptors */

	uint32_t	cpuid_cores_per_package;
	uint32_t	cpuid_logical_per_package;
	uint32_t	cache_sharing[LCACHE_MAX];
	uint32_t	cache_partitions[LCACHE_MAX];

	cpu_type_t	cpuid_cpu_type;			/* <mach/machine.h> */
	cpu_subtype_t	cpuid_cpu_subtype;		/* <mach/machine.h> */	

	/* Per-vendor info */
	cpuid_mwait_leaf_t	cpuid_mwait_leaf;	
#define cpuid_mwait_linesize_max	cpuid_mwait_leaf.linesize_max
#define cpuid_mwait_linesize_min	cpuid_mwait_leaf.linesize_min
#define cpuid_mwait_extensions		cpuid_mwait_leaf.extensions
#define cpuid_mwait_sub_Cstates		cpuid_mwait_leaf.sub_Cstates
	cpuid_thermal_leaf_t	cpuid_thermal_leaf;
	cpuid_arch_perf_leaf_t	cpuid_arch_perf_leaf;
	uint32_t	unused[4];			/* cpuid_xsave_leaf */

	/* Cache details: */
	uint32_t	cpuid_cache_linesize;
	uint32_t	cpuid_cache_L2_associativity;
	uint32_t	cpuid_cache_size;

	/* Virtual and physical address aize: */
	uint32_t	cpuid_address_bits_physical;
	uint32_t	cpuid_address_bits_virtual;

	uint32_t	cpuid_microcode_version;

	/* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
	uint32_t	cpuid_tlb[2][2][2];
			#define	TLB_INST	0
			#define	TLB_DATA	1
			#define	TLB_SMALL	0
			#define	TLB_LARGE	1
	uint32_t	cpuid_stlb;

	uint32_t	core_count;
	uint32_t	thread_count;

	/* Max leaf ids available from CPUID */
	uint32_t	cpuid_max_basic;
	uint32_t	cpuid_max_ext;

	/* Family-specific info links */
	uint32_t		cpuid_cpufamily;
	cpuid_mwait_leaf_t	*cpuid_mwait_leafp;	
	cpuid_thermal_leaf_t	*cpuid_thermal_leafp;
	cpuid_arch_perf_leaf_t	*cpuid_arch_perf_leafp;
	cpuid_xsave_leaf_t	*cpuid_xsave_leafp;
	uint64_t		cpuid_leaf7_features;
	cpuid_tsc_leaf_t	cpuid_tsc_leaf;
	cpuid_xsave_leaf_t	cpuid_xsave_leaf[2];
} i386_cpu_info_t;

#ifdef MACH_KERNEL_PRIVATE
typedef struct {
	char		cpuid_vmm_vendor[16];
	uint32_t	cpuid_vmm_family;
	uint32_t	cpuid_vmm_bus_frequency;
	uint32_t	cpuid_vmm_tsc_frequency;
} i386_vmm_info_t;
#endif

#ifdef __cplusplus
extern "C" {
#endif

/*
 * External declarations
 */
extern cpu_type_t	cpuid_cputype(void);
extern cpu_subtype_t	cpuid_cpusubtype(void);
extern void		cpuid_cpu_display(const char *);
extern void		cpuid_feature_display(const char *);
extern void		cpuid_extfeature_display(const char *);
extern char *		cpuid_get_feature_names(uint64_t, char *, unsigned);
extern char *		cpuid_get_extfeature_names(uint64_t, char *, unsigned);
extern char *		cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);

extern uint64_t		cpuid_features(void);
extern uint64_t		cpuid_extfeatures(void);
extern uint64_t		cpuid_leaf7_features(void);
extern uint32_t		cpuid_family(void);
extern uint32_t		cpuid_cpufamily(void);
	
extern i386_cpu_info_t	*cpuid_info(void);
extern void		cpuid_set_info(void);

#ifdef MACH_KERNEL_PRIVATE
extern boolean_t	cpuid_vmm_present(void);
extern i386_vmm_info_t	*cpuid_vmm_info(void);
extern uint32_t		cpuid_vmm_family(void);
#endif

#ifdef __cplusplus
}
#endif

#endif /* ASSEMBLER */

#endif /* __APPLE_API_PRIVATE */
#endif /* _MACHINE_CPUID_H_ */
Commit	Line	Data
1c79356b	1	/*
2d21ac55	2	* Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
1c79356b	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
1c79356b	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b A	27	*/
	28	/*
	29	* @OSF_COPYRIGHT@
	30	*/
	31
	32	/*
	33	* x86 CPU identification
	34	*
1c79356b A	35	*/
	36
	37	#ifndef _MACHINE_CPUID_H_
	38	#define _MACHINE_CPUID_H_
	39
55e303ae A	40	#include <sys/appleapiopts.h>
	41
	42	#ifdef __APPLE_API_PRIVATE
	43
1c79356b	44	#define CPUID_VID_INTEL "GenuineIntel"
1c79356b	45	#define CPUID_VID_AMD "AuthenticAMD"
91447636	46
fe8ab488 A	47	#define CPUID_VMM_ID_VMWARE "VMwareVMware"
fe8ab488 A	48	#define CPUID_VMM_ID_PARALLELS "Parallels\0\0\0"
316670eb	49
91447636	50	#define CPUID_STRING_UNKNOWN "Unknown CPU Typ"
1c79356b	51
0c530ab8 A	52	#define _Bit(n) (1ULL << n)
	53	#define _HBit(n) (1ULL << ((n)+32))
	54
	55	/*
	56	* The CPUID_FEATURE_XXX values define 64-bit values
	57	* returned in %ecx:%edx to a CPUID request with %eax of 1:
	58	*/
060df5ea A	59	#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
	60	#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
	61	#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
	62	#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
	63	#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
	64	#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
	65	#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
	66	#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
	67	#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
	68	#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
	69	#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
	70	#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
	71	#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
	72	#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
	73	#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
	74	#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
	75	#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
	76	#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
	77	#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
	78	#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
	79	#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
	80	#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
	81	#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
	82	#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
	83	#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
	84	#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
	85	#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
	86	#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
	87	#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
	88
	89	#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
	90	#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
	91	#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
	92	#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
	93	#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
	94	#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
	95	#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
	96	#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
	97	#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
	98	#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
	99	#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
7ddcb079	100	#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
bd504ef0	101	#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
060df5ea A	102	#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
	103	#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
	104	#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
	105
7ddcb079	106	#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
060df5ea A	107	#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
	108	#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
	109	#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
bd504ef0	110	#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
060df5ea A	111	#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
060df5ea A	112	#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
7ddcb079	113	#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
060df5ea A	114	#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
	115	#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
	116	#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
060df5ea	117	#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
316670eb A	118	#define CPUID_FEATURE_F16C _HBit(29) /* Float16 convert instructions */
316670eb A	119	#define CPUID_FEATURE_RDRAND _HBit(30) /* RDRAND instruction */
fe8ab488	120	#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
7ddcb079 A	121
	122	/*
	123	* Leaf 7, subleaf 0 additional features.
a1c7dba1	124	* Bits returned in %ebx:%ecx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
7ddcb079 A	125	*/
7ddcb079 A	126	#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */
bd504ef0 A	127	#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1) /* TSC thread offset */
	128	#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3) /* Bit Manipulation Instrs, set 1 */
	129	#define CPUID_LEAF7_FEATURE_HLE _Bit(4) /* Hardware Lock Elision*/
	130	#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5) /* AVX2 Instructions */
fe8ab488	131	#define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */
bd504ef0	132	#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8) /* Bit Manipulation Instrs, set 2 */
fe8ab488	133	#define CPUID_LEAF7_FEATURE_ERMS _Bit(9) /* Enhanced Rep Movsb/Stosb */
bd504ef0	134	#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10) /* INVPCID intruction, TDB */
a1c7dba1 A	135	#define CPUID_LEAF7_FEATURE_RTM _Bit(11) /* RTM */
	136	#define CPUID_LEAF7_FEATURE_RDSEED _Bit(18) /* RDSEED Instruction */
	137	#define CPUID_LEAF7_FEATURE_ADX _Bit(19) /* ADX Instructions */
a1c7dba1	138	#define CPUID_LEAF7_FEATURE_SMAP _Bit(20) /* Supervisor Mode Access Protect */
2dced7af A	139	#define CPUID_LEAF7_FEATURE_SGX _Bit(2) /* Software Guard eXtensions */
	140	#define CPUID_LEAF7_FEATURE_PQM _Bit(12) /* Platform Qos Monitoring */
	141	#define CPUID_LEAF7_FEATURE_FPU_CSDS _Bit(13) /* FPU CS/DS deprecation */
	142	#define CPUID_LEAF7_FEATURE_MPX _Bit(14) /* Memory Protection eXtensions */
	143	#define CPUID_LEAF7_FEATURE_PQE _Bit(15) /* Platform Qos Enforcement */
	144	#define CPUID_LEAF7_FEATURE_CLFSOPT _Bit(23) /* CLFSOPT */
	145	#define CPUID_LEAF7_FEATURE_IPT _Bit(25) /* Intel Processor Trace */
	146	#define CPUID_LEAF7_FEATURE_SHA _Bit(29) /* SHA instructions */
	147
	148	#define CPUID_LEAF7_FEATURE_PREFETCHWT1 _HBit(0)/* Prefetch Write/T1 hint */
0c530ab8 A	149
	150	/*
	151	* The CPUID_EXTFEATURE_XXX values define 64-bit values
	152	* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
	153	*/
	154	#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
	155	#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
b7266188	156
060df5ea	157	#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1GB pages */
c910b4d9	158	#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
0c530ab8 A	159	#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
0c530ab8 A	160
060df5ea	161	#define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAFH/SAHF instructions */
fe8ab488 A	162	#define CPUID_EXTFEATURE_LZCNT _HBit(5) /* LZCNT instruction */
fe8ab488 A	163	#define CPUID_EXTFEATURE_PREFETCHW _HBit(8) /* PREFETCHW instruction */
0c530ab8	164
c910b4d9 A	165	/*
	166	* The CPUID_EXTFEATURE_XXX values define 64-bit values
	167	* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
	168	*/
	169	#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
	170
fe8ab488 A	171	/*
	172	* CPUID_X86_64_H_FEATURE_SUBSET and CPUID_X86_64_H_LEAF7_FEATURE_SUBSET
	173	* indicate the bitmask of features that must be present before the system
	174	* is eligible to run the "x86_64h" "Haswell feature subset" slice.
	175	*/
	176	#define CPUID_X86_64_H_FEATURE_SUBSET ( CPUID_FEATURE_FMA \| \
	177	CPUID_FEATURE_SSE4_2 \| \
	178	CPUID_FEATURE_MOVBE \| \
	179	CPUID_FEATURE_POPCNT \| \
	180	CPUID_FEATURE_AVX1_0 \
	181	)
	182
	183	#define CPUID_X86_64_H_EXTFEATURE_SUBSET ( CPUID_EXTFEATURE_LZCNT \
	184	)
	185
	186	#define CPUID_X86_64_H_LEAF7_FEATURE_SUBSET ( CPUID_LEAF7_FEATURE_BMI1 \| \
	187	CPUID_LEAF7_FEATURE_AVX2 \| \
	188	CPUID_LEAF7_FEATURE_BMI2 \
	189	)
	190
b0d623f7	191	#define CPUID_CACHE_SIZE 16 /* Number of descriptor values */
1c79356b	192
2d21ac55 A	193	#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
	194	#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
	195
39236c6e A	196	#define CPUID_MODEL_YONAH 0x0E
	197	#define CPUID_MODEL_MEROM 0x0F
	198	#define CPUID_MODEL_PENRYN 0x17
	199	#define CPUID_MODEL_NEHALEM 0x1A
	200	#define CPUID_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield */
	201	#define CPUID_MODEL_DALES 0x1F /* Havendale, Auburndale */
	202	#define CPUID_MODEL_NEHALEM_EX 0x2E
	203	#define CPUID_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */
	204	#define CPUID_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP/-WS */
	205	#define CPUID_MODEL_WESTMERE_EX 0x2F
	206	#define CPUID_MODEL_SANDYBRIDGE 0x2A
	207	#define CPUID_MODEL_JAKETOWN 0x2D
	208	#define CPUID_MODEL_IVYBRIDGE 0x3A
15129b1c	209	#define CPUID_MODEL_IVYBRIDGE_EP 0x3E
39236c6e	210	#define CPUID_MODEL_CRYSTALWELL 0x46
39236c6e	211	#define CPUID_MODEL_HASWELL 0x3C
a1c7dba1	212	#define CPUID_MODEL_HASWELL_EP 0x3F
39236c6e	213	#define CPUID_MODEL_HASWELL_ULT 0x45
a1c7dba1 A	214	#define CPUID_MODEL_BROADWELL 0x3D
	215	#define CPUID_MODEL_BROADWELL_ULX 0x3D
	216	#define CPUID_MODEL_BROADWELL_ULT 0x3D
	217	#define CPUID_MODEL_BRYSTALWELL 0x47
2dced7af A	218	#define CPUID_MODEL_SKYLAKE 0x4E
	219	#define CPUID_MODEL_SKYLAKE_ULT 0x4E
	220	#define CPUID_MODEL_SKYLAKE_ULX 0x4E
	221	#define CPUID_MODEL_SKYLAKE_DT 0x5E
7ddcb079	222
316670eb A	223	#define CPUID_VMM_FAMILY_UNKNOWN 0x0
316670eb A	224	#define CPUID_VMM_FAMILY_VMWARE 0x1
fe8ab488	225	#define CPUID_VMM_FAMILY_PARALLELS 0x2
316670eb	226
1c79356b	227	#ifndef ASSEMBLER
55e303ae A	228	#include <stdint.h>
	229	#include <mach/mach_types.h>
	230	#include <kern/kern_types.h>
1c79356b A	231	#include <mach/machine.h>
1c79356b A	232
1c79356b	233
0c530ab8 A	234	typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
	235	static inline void
	236	cpuid(uint32_t *data)
	237	{
fe8ab488	238	__asm__ volatile ("cpuid"
0c530ab8 A	239	: "=a" (data[eax]),
	240	"=b" (data[ebx]),
	241	"=c" (data[ecx]),
	242	"=d" (data[edx])
	243	: "a" (data[eax]),
	244	"b" (data[ebx]),
	245	"c" (data[ecx]),
	246	"d" (data[edx]));
	247	}
060df5ea	248
55e303ae A	249	static inline void
	250	do_cpuid(uint32_t selector, uint32_t *data)
	251	{
fe8ab488	252	__asm__ volatile ("cpuid"
55e303ae A	253	: "=a" (data[0]),
	254	"=b" (data[1]),
	255	"=c" (data[2]),
	256	"=d" (data[3])
060df5ea A	257	: "a"(selector),
	258	"b" (0),
	259	"c" (0),
	260	"d" (0));
55e303ae	261	}
1c79356b A	262
1c79356b A	263	/*
2d21ac55 A	264	* Cache ID descriptor structure, used to parse CPUID leaf 2.
2d21ac55 A	265	* Note: not used in kernel.
1c79356b	266	*/
91447636	267	typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
55e303ae A	268	typedef struct {
	269	unsigned char value; /* Descriptor value */
	270	cache_type_t type; /* Cache type */
	271	unsigned int size; /* Cache size */
	272	unsigned int linesize; /* Cache line size */
	273	#ifdef KERNEL
91447636	274	const char description; / Cache description */
55e303ae A	275	#endif /* KERNEL */
	276	} cpuid_cache_desc_t;
	277
	278	#ifdef KERNEL
	279	#define CACHE_DESC(value,type,size,linesize,text) \
	280	{ value, type, size, linesize, text }
	281	#else
	282	#define CACHE_DESC(value,type,size,linesize,text) \
	283	{ value, type, size, linesize }
	284	#endif /* KERNEL */
	285
7e4a7d39 A	286	/* Monitor/mwait Leaf: */
	287	typedef struct {
	288	uint32_t linesize_min;
	289	uint32_t linesize_max;
	290	uint32_t extensions;
	291	uint32_t sub_Cstates;
	292	} cpuid_mwait_leaf_t;
	293
	294	/* Thermal and Power Management Leaf: */
	295	typedef struct {
	296	boolean_t sensor;
	297	boolean_t dynamic_acceleration;
b7266188	298	boolean_t invariant_APIC_timer;
060df5ea A	299	boolean_t core_power_limits;
	300	boolean_t fine_grain_clock_mod;
	301	boolean_t package_thermal_intr;
7e4a7d39 A	302	uint32_t thresholds;
7e4a7d39 A	303	boolean_t ACNT_MCNT;
060df5ea A	304	boolean_t hardware_feedback;
060df5ea A	305	boolean_t energy_policy;
7e4a7d39 A	306	} cpuid_thermal_leaf_t;
7e4a7d39 A	307
060df5ea A	308
	309	/* XSAVE Feature Leaf: */
	310	typedef struct {
	311	uint32_t extended_state[4]; /* eax .. edx */
	312	} cpuid_xsave_leaf_t;
	313
	314
7e4a7d39 A	315	/* Architectural Performance Monitoring Leaf: */
	316	typedef struct {
	317	uint8_t version;
	318	uint8_t number;
	319	uint8_t width;
	320	uint8_t events_number;
	321	uint32_t events;
	322	uint8_t fixed_number;
	323	uint8_t fixed_width;
	324	} cpuid_arch_perf_leaf_t;
	325
2dced7af A	326	/* The TSC to Core Crystal (RefCLK) Clock Information leaf */
	327	typedef struct {
	328	uint32_t numerator;
	329	uint32_t denominator;
	330	} cpuid_tsc_leaf_t;
	331
0c530ab8	332	/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
55e303ae A	333	typedef struct {
	334	char cpuid_vendor[16];
	335	char cpuid_brand_string[48];
91447636	336	const char *cpuid_model_string;
55e303ae	337
7e4a7d39	338	cpu_type_t cpuid_type; /* this is not a cpu_type_t in our <mach/machine.h> */
55e303ae A	339	uint8_t cpuid_family;
	340	uint8_t cpuid_model;
	341	uint8_t cpuid_extmodel;
	342	uint8_t cpuid_extfamily;
	343	uint8_t cpuid_stepping;
0c530ab8 A	344	uint64_t cpuid_features;
0c530ab8 A	345	uint64_t cpuid_extfeatures;
55e303ae A	346	uint32_t cpuid_signature;
55e303ae A	347	uint8_t cpuid_brand;
6d2010ae	348	uint8_t cpuid_processor_flag;
55e303ae A	349
	350	uint32_t cache_size[LCACHE_MAX];
	351	uint32_t cache_linesize;
	352
55e303ae A	353	uint8_t cache_info[64]; /* list of cache descriptors */
55e303ae A	354
0c530ab8 A	355	uint32_t cpuid_cores_per_package;
	356	uint32_t cpuid_logical_per_package;
	357	uint32_t cache_sharing[LCACHE_MAX];
2d21ac55	358	uint32_t cache_partitions[LCACHE_MAX];
0c530ab8	359
2d21ac55	360	cpu_type_t cpuid_cpu_type; /* <mach/machine.h> */
0c530ab8	361	cpu_subtype_t cpuid_cpu_subtype; /* <mach/machine.h> */
2d21ac55	362
7e4a7d39 A	363	/* Per-vendor info */
	364	cpuid_mwait_leaf_t cpuid_mwait_leaf;
	365	#define cpuid_mwait_linesize_max cpuid_mwait_leaf.linesize_max
	366	#define cpuid_mwait_linesize_min cpuid_mwait_leaf.linesize_min
	367	#define cpuid_mwait_extensions cpuid_mwait_leaf.extensions
	368	#define cpuid_mwait_sub_Cstates cpuid_mwait_leaf.sub_Cstates
	369	cpuid_thermal_leaf_t cpuid_thermal_leaf;
	370	cpuid_arch_perf_leaf_t cpuid_arch_perf_leaf;
3e170ce0	371	uint32_t unused[4]; /* cpuid_xsave_leaf */
7e4a7d39	372
2d21ac55 A	373	/* Cache details: */
	374	uint32_t cpuid_cache_linesize;
	375	uint32_t cpuid_cache_L2_associativity;
	376	uint32_t cpuid_cache_size;
	377
	378	/* Virtual and physical address aize: */
	379	uint32_t cpuid_address_bits_physical;
	380	uint32_t cpuid_address_bits_virtual;
593a1d5f A	381
	382	uint32_t cpuid_microcode_version;
	383
b0d623f7 A	384	/* Numbers of tlbs per processor [i\|d, small\|large, level0\|level1] */
	385	uint32_t cpuid_tlb[2][2][2];
	386	#define TLB_INST 0
	387	#define TLB_DATA 1
	388	#define TLB_SMALL 0
	389	#define TLB_LARGE 1
	390	uint32_t cpuid_stlb;
593a1d5f A	391
	392	uint32_t core_count;
	393	uint32_t thread_count;
	394
b0d623f7 A	395	/* Max leaf ids available from CPUID */
	396	uint32_t cpuid_max_basic;
	397	uint32_t cpuid_max_ext;
7e4a7d39 A	398
	399	/* Family-specific info links */
	400	uint32_t cpuid_cpufamily;
	401	cpuid_mwait_leaf_t *cpuid_mwait_leafp;
	402	cpuid_thermal_leaf_t *cpuid_thermal_leafp;
	403	cpuid_arch_perf_leaf_t *cpuid_arch_perf_leafp;
060df5ea	404	cpuid_xsave_leaf_t *cpuid_xsave_leafp;
a1c7dba1	405	uint64_t cpuid_leaf7_features;
2dced7af	406	cpuid_tsc_leaf_t cpuid_tsc_leaf;
3e170ce0	407	cpuid_xsave_leaf_t cpuid_xsave_leaf[2];
55e303ae	408	} i386_cpu_info_t;
1c79356b	409
316670eb A	410	#ifdef MACH_KERNEL_PRIVATE
	411	typedef struct {
	412	char cpuid_vmm_vendor[16];
	413	uint32_t cpuid_vmm_family;
	414	uint32_t cpuid_vmm_bus_frequency;
	415	uint32_t cpuid_vmm_tsc_frequency;
	416	} i386_vmm_info_t;
	417	#endif
	418
91447636 A	419	#ifdef __cplusplus
	420	extern "C" {
	421	#endif
1c79356b A	422
	423	/*
	424	* External declarations
	425	*/
0c530ab8 A	426	extern cpu_type_t cpuid_cputype(void);
	427	extern cpu_subtype_t cpuid_cpusubtype(void);
	428	extern void cpuid_cpu_display(const char *);
	429	extern void cpuid_feature_display(const char *);
	430	extern void cpuid_extfeature_display(const char *);
	431	extern char * cpuid_get_feature_names(uint64_t, char *, unsigned);
	432	extern char * cpuid_get_extfeature_names(uint64_t, char *, unsigned);
7ddcb079	433	extern char * cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);
0c530ab8 A	434
	435	extern uint64_t cpuid_features(void);
	436	extern uint64_t cpuid_extfeatures(void);
7ddcb079	437	extern uint64_t cpuid_leaf7_features(void);
55e303ae	438	extern uint32_t cpuid_family(void);
7e4a7d39	439	extern uint32_t cpuid_cpufamily(void);
91447636	440
91447636	441	extern i386_cpu_info_t *cpuid_info(void);
0c530ab8	442	extern void cpuid_set_info(void);
1c79356b	443
316670eb A	444	#ifdef MACH_KERNEL_PRIVATE
	445	extern boolean_t cpuid_vmm_present(void);
	446	extern i386_vmm_info_t *cpuid_vmm_info(void);
	447	extern uint32_t cpuid_vmm_family(void);
	448	#endif
	449
91447636 A	450	#ifdef __cplusplus
	451	}
	452	#endif
55e303ae	453
1c79356b	454	#endif /* ASSEMBLER */
55e303ae A	455
55e303ae A	456	#endif /* __APPLE_API_PRIVATE */
1c79356b	457	#endif /* _MACHINE_CPUID_H_ */