[apple/xnu.git] / osfmk / i386 / cpuid.h

/*
 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */

/*
 * x86 CPU identification
 *
 */

#ifndef _MACHINE_CPUID_H_
#define _MACHINE_CPUID_H_

#include <sys/appleapiopts.h>

#ifdef __APPLE_API_PRIVATE

#define	CPUID_VID_INTEL		"GenuineIntel"
#define	CPUID_VID_AMD		"AuthenticAMD"

#define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"

#define _Bit(n)			(1ULL << n)
#define _HBit(n)		(1ULL << ((n)+32))

/*
 * The CPUID_FEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 1: 
 */
#define CPUID_FEATURE_FPU       _Bit(0)   /* Floating point unit on-chip */
#define CPUID_FEATURE_VME       _Bit(1)   /* Virtual Mode Extension */
#define CPUID_FEATURE_DE        _Bit(2)   /* Debugging Extension */
#define CPUID_FEATURE_PSE       _Bit(3)   /* Page Size Extension */
#define CPUID_FEATURE_TSC       _Bit(4)   /* Time Stamp Counter */
#define CPUID_FEATURE_MSR       _Bit(5)   /* Model Specific Registers */
#define CPUID_FEATURE_PAE       _Bit(6)   /* Physical Address Extension */
#define CPUID_FEATURE_MCE       _Bit(7)   /* Machine Check Exception */
#define CPUID_FEATURE_CX8       _Bit(8)   /* CMPXCHG8B */
#define CPUID_FEATURE_APIC      _Bit(9)   /* On-chip APIC */
#define CPUID_FEATURE_SEP       _Bit(11)  /* Fast System Call */
#define CPUID_FEATURE_MTRR      _Bit(12)  /* Memory Type Range Register */
#define CPUID_FEATURE_PGE       _Bit(13)  /* Page Global Enable */
#define CPUID_FEATURE_MCA       _Bit(14)  /* Machine Check Architecture */
#define CPUID_FEATURE_CMOV      _Bit(15)  /* Conditional Move Instruction */
#define CPUID_FEATURE_PAT       _Bit(16)  /* Page Attribute Table */
#define CPUID_FEATURE_PSE36     _Bit(17)  /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN       _Bit(18)  /* Processor Serial Number */
#define CPUID_FEATURE_CLFSH     _Bit(19)  /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS        _Bit(21)  /* Debug Store */
#define CPUID_FEATURE_ACPI      _Bit(22)  /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX       _Bit(23)  /* MMX supported */
#define CPUID_FEATURE_FXSR      _Bit(24)  /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE       _Bit(25)  /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2      _Bit(26)  /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS        _Bit(27)  /* Self-Snoop */
#define CPUID_FEATURE_HTT       _Bit(28)  /* Hyper-Threading Technology */
#define CPUID_FEATURE_TM        _Bit(29)  /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE       _Bit(31)  /* Pend Break Enable */
 
#define CPUID_FEATURE_SSE3      _HBit(0)  /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1)  /* PCLMULQDQ instruction */
#define CPUID_FEATURE_DTES64    _HBit(2)  /* 64-bit DS layout */
#define CPUID_FEATURE_MONITOR   _HBit(3)  /* Monitor/mwait */
#define CPUID_FEATURE_DSCPL     _HBit(4)  /* Debug Store CPL */
#define CPUID_FEATURE_VMX       _HBit(5)  /* VMX */
#define CPUID_FEATURE_SMX       _HBit(6)  /* SMX */
#define CPUID_FEATURE_EST       _HBit(7)  /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2       _HBit(8)  /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3     _HBit(9)  /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID       _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_CX16      _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR      _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM      _HBit(15) /* Perf/Debug Capability MSR */

#define CPUID_FEATURE_DCA       _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1    _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2    _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_xAPIC     _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE     _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT    _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_AES       _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE     _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE   _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_VMM       _HBit(31) /* VMM (Hypervisor) present */
#define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AVX1_0	_HBit(28) /* AVX 1.0 instructions */

/*
 * The CPUID_EXTFEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: 
 */
#define CPUID_EXTFEATURE_SYSCALL   _Bit(11)	/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD	   _Bit(20)	/* eXecute Disable */

#define CPUID_EXTFEATURE_1GBPAGE   _Bit(26)	/* 1GB pages */
#define CPUID_EXTFEATURE_RDTSCP	   _Bit(27)	/* RDTSCP */
#define CPUID_EXTFEATURE_EM64T	   _Bit(29)	/* Extended Mem 64 Technology */

#define CPUID_EXTFEATURE_LAHF	   _HBit(0)	/* LAFH/SAHF instructions */

/*
 * The CPUID_EXTFEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: 
 */
#define CPUID_EXTFEATURE_TSCI      _Bit(8)	/* TSC Invariant */

#define	CPUID_CACHE_SIZE	16	/* Number of descriptor values */

#define CPUID_MWAIT_EXTENSION	_Bit(0)	/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK	_Bit(1)	/* interrupts are break events	   */

#define CPUID_MODEL_YONAH	0x0E
#define CPUID_MODEL_MEROM	0x0F
#define CPUID_MODEL_PENRYN	0x17
#define CPUID_MODEL_NEHALEM	0x1A
#define CPUID_MODEL_FIELDS	0x1E	/* Lynnfield, Clarksfield, Jasper */
#define CPUID_MODEL_DALES	0x1F	/* Havendale, Auburndale */
#define CPUID_MODEL_NEHALEM_EX	0x2E
#define CPUID_MODEL_DALES_32NM	0x25	/* Clarkdale, Arrandale */
#define CPUID_MODEL_WESTMERE	0x2C	/* Gulftown, Westmere-EP, Westmere-WS */
#define CPUID_MODEL_WESTMERE_EX	0x2F
/* Additional internal models go here */
#define CPUID_MODEL_SANDYBRIDGE	0x2A
#define CPUID_MODEL_JAKETOWN	0x2D

#ifndef ASSEMBLER
#include <stdint.h>
#include <mach/mach_types.h>
#include <kern/kern_types.h>
#include <mach/machine.h>


typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
static inline void
cpuid(uint32_t *data)
{
	asm("cpuid"
		: "=a" (data[eax]),
		  "=b" (data[ebx]),
		  "=c" (data[ecx]),
		  "=d" (data[edx])
		: "a"  (data[eax]),
		  "b"  (data[ebx]),
		  "c"  (data[ecx]),
		  "d"  (data[edx]));
}

static inline void
do_cpuid(uint32_t selector, uint32_t *data)
{
	asm("cpuid"
		: "=a" (data[0]),
		  "=b" (data[1]),
		  "=c" (data[2]),
		  "=d" (data[3])
		: "a"(selector),
		  "b" (0),
		  "c" (0),
		  "d" (0));
}

/*
 * Cache ID descriptor structure, used to parse CPUID leaf 2.
 * Note: not used in kernel.
 */
typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ; 
typedef struct {
	unsigned char	value;          /* Descriptor value */
	cache_type_t 	type;           /* Cache type */
	unsigned int 	size;           /* Cache size */
	unsigned int 	linesize;       /* Cache line size */
#ifdef KERNEL
	const char	*description;   /* Cache description */
#endif /* KERNEL */
} cpuid_cache_desc_t;  

#ifdef KERNEL
#define CACHE_DESC(value,type,size,linesize,text) \
	{ value, type, size, linesize, text }
#else
#define CACHE_DESC(value,type,size,linesize,text) \
	{ value, type, size, linesize }
#endif /* KERNEL */

/* Monitor/mwait Leaf: */
typedef struct {
	uint32_t	linesize_min;
	uint32_t	linesize_max;
	uint32_t	extensions;
	uint32_t	sub_Cstates;
} cpuid_mwait_leaf_t;

/* Thermal and Power Management Leaf: */
typedef struct {
	boolean_t	sensor;
	boolean_t	dynamic_acceleration;
	boolean_t	invariant_APIC_timer;
	boolean_t	core_power_limits;
	boolean_t	fine_grain_clock_mod;
	boolean_t	package_thermal_intr;
	uint32_t	thresholds;
	boolean_t	ACNT_MCNT;
	boolean_t	hardware_feedback;
	boolean_t	energy_policy;
} cpuid_thermal_leaf_t;


/* XSAVE Feature Leaf: */
typedef struct {
	uint32_t	extended_state[4];	/* eax .. edx */
} cpuid_xsave_leaf_t;


/* Architectural Performance Monitoring Leaf: */
typedef struct {
	uint8_t		version;
	uint8_t		number;
	uint8_t		width;
	uint8_t		events_number;
	uint32_t	events;
	uint8_t		fixed_number;
	uint8_t		fixed_width;
} cpuid_arch_perf_leaf_t;

/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
typedef struct {
	char		cpuid_vendor[16];
	char		cpuid_brand_string[48];
	const char	*cpuid_model_string;

	cpu_type_t	cpuid_type;	/* this is *not* a cpu_type_t in our <mach/machine.h> */
	uint8_t		cpuid_family;
	uint8_t		cpuid_model;
	uint8_t		cpuid_extmodel;
	uint8_t		cpuid_extfamily;
	uint8_t		cpuid_stepping;
	uint64_t	cpuid_features;
	uint64_t	cpuid_extfeatures;
	uint32_t	cpuid_signature;
	uint8_t   	cpuid_brand; 
	
	uint32_t	cache_size[LCACHE_MAX];
	uint32_t	cache_linesize;

	uint8_t		cache_info[64];    /* list of cache descriptors */

	uint32_t	cpuid_cores_per_package;
	uint32_t	cpuid_logical_per_package;
	uint32_t	cache_sharing[LCACHE_MAX];
	uint32_t	cache_partitions[LCACHE_MAX];

	cpu_type_t	cpuid_cpu_type;			/* <mach/machine.h> */
	cpu_subtype_t	cpuid_cpu_subtype;		/* <mach/machine.h> */	

	/* Per-vendor info */
	cpuid_mwait_leaf_t	cpuid_mwait_leaf;	
#define cpuid_mwait_linesize_max	cpuid_mwait_leaf.linesize_max
#define cpuid_mwait_linesize_min	cpuid_mwait_leaf.linesize_min
#define cpuid_mwait_extensions		cpuid_mwait_leaf.extensions
#define cpuid_mwait_sub_Cstates		cpuid_mwait_leaf.sub_Cstates
	cpuid_thermal_leaf_t	cpuid_thermal_leaf;
	cpuid_arch_perf_leaf_t	cpuid_arch_perf_leaf;
	cpuid_xsave_leaf_t	cpuid_xsave_leaf;

	/* Cache details: */
	uint32_t	cpuid_cache_linesize;
	uint32_t	cpuid_cache_L2_associativity;
	uint32_t	cpuid_cache_size;

	/* Virtual and physical address aize: */
	uint32_t	cpuid_address_bits_physical;
	uint32_t	cpuid_address_bits_virtual;

	uint32_t	cpuid_microcode_version;

	/* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
	uint32_t	cpuid_tlb[2][2][2];
			#define	TLB_INST	0
			#define	TLB_DATA	1
			#define	TLB_SMALL	0
			#define	TLB_LARGE	1
	uint32_t	cpuid_stlb;

	uint32_t	core_count;
	uint32_t	thread_count;

	/* Max leaf ids available from CPUID */
	uint32_t	cpuid_max_basic;
	uint32_t	cpuid_max_ext;

	/* Family-specific info links */
	uint32_t		cpuid_cpufamily;
	cpuid_mwait_leaf_t	*cpuid_mwait_leafp;	
	cpuid_thermal_leaf_t	*cpuid_thermal_leafp;
	cpuid_arch_perf_leaf_t	*cpuid_arch_perf_leafp;
	cpuid_xsave_leaf_t	*cpuid_xsave_leafp;
} i386_cpu_info_t;

#ifdef __cplusplus
extern "C" {
#endif

/*
 * External declarations
 */
extern cpu_type_t	cpuid_cputype(void);
extern cpu_subtype_t	cpuid_cpusubtype(void);
extern void		cpuid_cpu_display(const char *);
extern void		cpuid_feature_display(const char *);
extern void		cpuid_extfeature_display(const char *);
extern char *		cpuid_get_feature_names(uint64_t, char *, unsigned);
extern char *		cpuid_get_extfeature_names(uint64_t, char *, unsigned);

extern uint64_t		cpuid_features(void);
extern uint64_t		cpuid_extfeatures(void);
extern uint32_t		cpuid_family(void);
extern uint32_t		cpuid_cpufamily(void);
	
extern void		cpuid_get_info(i386_cpu_info_t *info_p);
extern i386_cpu_info_t	*cpuid_info(void);

extern void		cpuid_set_info(void);

#ifdef __cplusplus
}
#endif

#endif /* ASSEMBLER */

#endif /* __APPLE_API_PRIVATE */
#endif /* _MACHINE_CPUID_H_ */
Commit	Line	Data
1c79356b	1	/*
2d21ac55	2	* Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
1c79356b	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
1c79356b	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b A	27	*/
	28	/*
	29	* @OSF_COPYRIGHT@
	30	*/
	31
	32	/*
	33	* x86 CPU identification
	34	*
1c79356b A	35	*/
	36
	37	#ifndef _MACHINE_CPUID_H_
	38	#define _MACHINE_CPUID_H_
	39
55e303ae A	40	#include <sys/appleapiopts.h>
	41
	42	#ifdef __APPLE_API_PRIVATE
	43
1c79356b	44	#define CPUID_VID_INTEL "GenuineIntel"
1c79356b	45	#define CPUID_VID_AMD "AuthenticAMD"
91447636 A	46
91447636 A	47	#define CPUID_STRING_UNKNOWN "Unknown CPU Typ"
1c79356b	48
0c530ab8 A	49	#define _Bit(n) (1ULL << n)
	50	#define _HBit(n) (1ULL << ((n)+32))
	51
	52	/*
	53	* The CPUID_FEATURE_XXX values define 64-bit values
	54	* returned in %ecx:%edx to a CPUID request with %eax of 1:
	55	*/
060df5ea A	56	#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
	57	#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
	58	#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
	59	#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
	60	#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
	61	#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
	62	#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
	63	#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
	64	#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
	65	#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
	66	#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
	67	#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
	68	#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
	69	#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
	70	#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
	71	#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
	72	#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
	73	#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
	74	#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
	75	#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
	76	#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
	77	#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
	78	#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
	79	#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
	80	#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
	81	#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
	82	#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
	83	#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
	84	#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
	85
	86	#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
	87	#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
	88	#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
	89	#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
	90	#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
	91	#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
	92	#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
	93	#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
	94	#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
	95	#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
	96	#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
	97	#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
	98	#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
	99	#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
	100
	101	#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
	102	#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
	103	#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
	104	#define CPUID_FEATURE_xAPIC _HBit(21) /* Extended APIC Mode */
	105	#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
	106	#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
	107	#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
	108	#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
	109	#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
	110	#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
	111	#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
	112	#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
	113	#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
	114	#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
0c530ab8 A	115
	116	/*
	117	* The CPUID_EXTFEATURE_XXX values define 64-bit values
	118	* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
	119	*/
	120	#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
	121	#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
b7266188	122
060df5ea	123	#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1GB pages */
c910b4d9	124	#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
0c530ab8 A	125	#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
0c530ab8 A	126
060df5ea	127	#define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAFH/SAHF instructions */
0c530ab8	128
c910b4d9 A	129	/*
	130	* The CPUID_EXTFEATURE_XXX values define 64-bit values
	131	* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
	132	*/
	133	#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
	134
b0d623f7	135	#define CPUID_CACHE_SIZE 16 /* Number of descriptor values */
1c79356b	136
2d21ac55 A	137	#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
	138	#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
	139
060df5ea A	140	#define CPUID_MODEL_YONAH 0x0E
	141	#define CPUID_MODEL_MEROM 0x0F
	142	#define CPUID_MODEL_PENRYN 0x17
	143	#define CPUID_MODEL_NEHALEM 0x1A
	144	#define CPUID_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield, Jasper */
	145	#define CPUID_MODEL_DALES 0x1F /* Havendale, Auburndale */
	146	#define CPUID_MODEL_NEHALEM_EX 0x2E
	147	#define CPUID_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */
	148	#define CPUID_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP, Westmere-WS */
	149	#define CPUID_MODEL_WESTMERE_EX 0x2F
	150	/* Additional internal models go here */
	151	#define CPUID_MODEL_SANDYBRIDGE 0x2A
	152	#define CPUID_MODEL_JAKETOWN 0x2D
593a1d5f	153
1c79356b	154	#ifndef ASSEMBLER
55e303ae A	155	#include <stdint.h>
	156	#include <mach/mach_types.h>
	157	#include <kern/kern_types.h>
1c79356b A	158	#include <mach/machine.h>
1c79356b A	159
1c79356b	160
0c530ab8 A	161	typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
	162	static inline void
	163	cpuid(uint32_t *data)
	164	{
	165	asm("cpuid"
	166	: "=a" (data[eax]),
	167	"=b" (data[ebx]),
	168	"=c" (data[ecx]),
	169	"=d" (data[edx])
	170	: "a" (data[eax]),
	171	"b" (data[ebx]),
	172	"c" (data[ecx]),
	173	"d" (data[edx]));
	174	}
060df5ea	175
55e303ae A	176	static inline void
	177	do_cpuid(uint32_t selector, uint32_t *data)
	178	{
	179	asm("cpuid"
	180	: "=a" (data[0]),
	181	"=b" (data[1]),
	182	"=c" (data[2]),
	183	"=d" (data[3])
060df5ea A	184	: "a"(selector),
	185	"b" (0),
	186	"c" (0),
	187	"d" (0));
55e303ae	188	}
1c79356b A	189
1c79356b A	190	/*
2d21ac55 A	191	* Cache ID descriptor structure, used to parse CPUID leaf 2.
2d21ac55 A	192	* Note: not used in kernel.
1c79356b	193	*/
91447636	194	typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
55e303ae A	195	typedef struct {
	196	unsigned char value; /* Descriptor value */
	197	cache_type_t type; /* Cache type */
	198	unsigned int size; /* Cache size */
	199	unsigned int linesize; /* Cache line size */
	200	#ifdef KERNEL
91447636	201	const char description; / Cache description */
55e303ae A	202	#endif /* KERNEL */
	203	} cpuid_cache_desc_t;
	204
	205	#ifdef KERNEL
	206	#define CACHE_DESC(value,type,size,linesize,text) \
	207	{ value, type, size, linesize, text }
	208	#else
	209	#define CACHE_DESC(value,type,size,linesize,text) \
	210	{ value, type, size, linesize }
	211	#endif /* KERNEL */
	212
7e4a7d39 A	213	/* Monitor/mwait Leaf: */
	214	typedef struct {
	215	uint32_t linesize_min;
	216	uint32_t linesize_max;
	217	uint32_t extensions;
	218	uint32_t sub_Cstates;
	219	} cpuid_mwait_leaf_t;
	220
	221	/* Thermal and Power Management Leaf: */
	222	typedef struct {
	223	boolean_t sensor;
	224	boolean_t dynamic_acceleration;
b7266188	225	boolean_t invariant_APIC_timer;
060df5ea A	226	boolean_t core_power_limits;
	227	boolean_t fine_grain_clock_mod;
	228	boolean_t package_thermal_intr;
7e4a7d39 A	229	uint32_t thresholds;
7e4a7d39 A	230	boolean_t ACNT_MCNT;
060df5ea A	231	boolean_t hardware_feedback;
060df5ea A	232	boolean_t energy_policy;
7e4a7d39 A	233	} cpuid_thermal_leaf_t;
7e4a7d39 A	234
060df5ea A	235
	236	/* XSAVE Feature Leaf: */
	237	typedef struct {
	238	uint32_t extended_state[4]; /* eax .. edx */
	239	} cpuid_xsave_leaf_t;
	240
	241
7e4a7d39 A	242	/* Architectural Performance Monitoring Leaf: */
	243	typedef struct {
	244	uint8_t version;
	245	uint8_t number;
	246	uint8_t width;
	247	uint8_t events_number;
	248	uint32_t events;
	249	uint8_t fixed_number;
	250	uint8_t fixed_width;
	251	} cpuid_arch_perf_leaf_t;
	252
0c530ab8	253	/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
55e303ae A	254	typedef struct {
	255	char cpuid_vendor[16];
	256	char cpuid_brand_string[48];
91447636	257	const char *cpuid_model_string;
55e303ae	258
7e4a7d39	259	cpu_type_t cpuid_type; /* this is not a cpu_type_t in our <mach/machine.h> */
55e303ae A	260	uint8_t cpuid_family;
	261	uint8_t cpuid_model;
	262	uint8_t cpuid_extmodel;
	263	uint8_t cpuid_extfamily;
	264	uint8_t cpuid_stepping;
0c530ab8 A	265	uint64_t cpuid_features;
0c530ab8 A	266	uint64_t cpuid_extfeatures;
55e303ae A	267	uint32_t cpuid_signature;
	268	uint8_t cpuid_brand;
	269
	270	uint32_t cache_size[LCACHE_MAX];
	271	uint32_t cache_linesize;
	272
55e303ae A	273	uint8_t cache_info[64]; /* list of cache descriptors */
55e303ae A	274
0c530ab8 A	275	uint32_t cpuid_cores_per_package;
	276	uint32_t cpuid_logical_per_package;
	277	uint32_t cache_sharing[LCACHE_MAX];
2d21ac55	278	uint32_t cache_partitions[LCACHE_MAX];
0c530ab8	279
2d21ac55	280	cpu_type_t cpuid_cpu_type; /* <mach/machine.h> */
0c530ab8	281	cpu_subtype_t cpuid_cpu_subtype; /* <mach/machine.h> */
2d21ac55	282
7e4a7d39 A	283	/* Per-vendor info */
	284	cpuid_mwait_leaf_t cpuid_mwait_leaf;
	285	#define cpuid_mwait_linesize_max cpuid_mwait_leaf.linesize_max
	286	#define cpuid_mwait_linesize_min cpuid_mwait_leaf.linesize_min
	287	#define cpuid_mwait_extensions cpuid_mwait_leaf.extensions
	288	#define cpuid_mwait_sub_Cstates cpuid_mwait_leaf.sub_Cstates
	289	cpuid_thermal_leaf_t cpuid_thermal_leaf;
	290	cpuid_arch_perf_leaf_t cpuid_arch_perf_leaf;
060df5ea	291	cpuid_xsave_leaf_t cpuid_xsave_leaf;
7e4a7d39	292
2d21ac55 A	293	/* Cache details: */
	294	uint32_t cpuid_cache_linesize;
	295	uint32_t cpuid_cache_L2_associativity;
	296	uint32_t cpuid_cache_size;
	297
	298	/* Virtual and physical address aize: */
	299	uint32_t cpuid_address_bits_physical;
	300	uint32_t cpuid_address_bits_virtual;
593a1d5f A	301
	302	uint32_t cpuid_microcode_version;
	303
b0d623f7 A	304	/* Numbers of tlbs per processor [i\|d, small\|large, level0\|level1] */
	305	uint32_t cpuid_tlb[2][2][2];
	306	#define TLB_INST 0
	307	#define TLB_DATA 1
	308	#define TLB_SMALL 0
	309	#define TLB_LARGE 1
	310	uint32_t cpuid_stlb;
593a1d5f A	311
	312	uint32_t core_count;
	313	uint32_t thread_count;
	314
b0d623f7 A	315	/* Max leaf ids available from CPUID */
	316	uint32_t cpuid_max_basic;
	317	uint32_t cpuid_max_ext;
7e4a7d39 A	318
	319	/* Family-specific info links */
	320	uint32_t cpuid_cpufamily;
	321	cpuid_mwait_leaf_t *cpuid_mwait_leafp;
	322	cpuid_thermal_leaf_t *cpuid_thermal_leafp;
	323	cpuid_arch_perf_leaf_t *cpuid_arch_perf_leafp;
060df5ea	324	cpuid_xsave_leaf_t *cpuid_xsave_leafp;
55e303ae	325	} i386_cpu_info_t;
1c79356b	326
91447636 A	327	#ifdef __cplusplus
	328	extern "C" {
	329	#endif
1c79356b A	330
	331	/*
	332	* External declarations
	333	*/
0c530ab8 A	334	extern cpu_type_t cpuid_cputype(void);
	335	extern cpu_subtype_t cpuid_cpusubtype(void);
	336	extern void cpuid_cpu_display(const char *);
	337	extern void cpuid_feature_display(const char *);
	338	extern void cpuid_extfeature_display(const char *);
	339	extern char * cpuid_get_feature_names(uint64_t, char *, unsigned);
	340	extern char * cpuid_get_extfeature_names(uint64_t, char *, unsigned);
	341
	342	extern uint64_t cpuid_features(void);
	343	extern uint64_t cpuid_extfeatures(void);
55e303ae	344	extern uint32_t cpuid_family(void);
7e4a7d39	345	extern uint32_t cpuid_cpufamily(void);
91447636 A	346
	347	extern void cpuid_get_info(i386_cpu_info_t *info_p);
	348	extern i386_cpu_info_t *cpuid_info(void);
55e303ae	349
0c530ab8	350	extern void cpuid_set_info(void);
1c79356b	351
91447636 A	352	#ifdef __cplusplus
	353	}
	354	#endif
55e303ae	355
1c79356b	356	#endif /* ASSEMBLER */
55e303ae A	357
55e303ae A	358	#endif /* __APPLE_API_PRIVATE */
1c79356b	359	#endif /* _MACHINE_CPUID_H_ */