[apple/xnu.git] / osfmk / i386 / cpuid.h

/*
 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */

/*
 * x86 CPU identification
 *
 */

#ifndef _MACHINE_CPUID_H_
#define _MACHINE_CPUID_H_

#include <sys/appleapiopts.h>

#ifdef __APPLE_API_PRIVATE

#define	CPUID_VID_INTEL		"GenuineIntel"
#define	CPUID_VID_AMD		"AuthenticAMD"

#define CPUID_VMM_ID_VMWARE	"VMwareVMware"

#define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"

#define _Bit(n)			(1ULL << n)
#define _HBit(n)		(1ULL << ((n)+32))

/*
 * The CPUID_FEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 1: 
 */
#define CPUID_FEATURE_FPU       _Bit(0)   /* Floating point unit on-chip */
#define CPUID_FEATURE_VME       _Bit(1)   /* Virtual Mode Extension */
#define CPUID_FEATURE_DE        _Bit(2)   /* Debugging Extension */
#define CPUID_FEATURE_PSE       _Bit(3)   /* Page Size Extension */
#define CPUID_FEATURE_TSC       _Bit(4)   /* Time Stamp Counter */
#define CPUID_FEATURE_MSR       _Bit(5)   /* Model Specific Registers */
#define CPUID_FEATURE_PAE       _Bit(6)   /* Physical Address Extension */
#define CPUID_FEATURE_MCE       _Bit(7)   /* Machine Check Exception */
#define CPUID_FEATURE_CX8       _Bit(8)   /* CMPXCHG8B */
#define CPUID_FEATURE_APIC      _Bit(9)   /* On-chip APIC */
#define CPUID_FEATURE_SEP       _Bit(11)  /* Fast System Call */
#define CPUID_FEATURE_MTRR      _Bit(12)  /* Memory Type Range Register */
#define CPUID_FEATURE_PGE       _Bit(13)  /* Page Global Enable */
#define CPUID_FEATURE_MCA       _Bit(14)  /* Machine Check Architecture */
#define CPUID_FEATURE_CMOV      _Bit(15)  /* Conditional Move Instruction */
#define CPUID_FEATURE_PAT       _Bit(16)  /* Page Attribute Table */
#define CPUID_FEATURE_PSE36     _Bit(17)  /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN       _Bit(18)  /* Processor Serial Number */
#define CPUID_FEATURE_CLFSH     _Bit(19)  /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS        _Bit(21)  /* Debug Store */
#define CPUID_FEATURE_ACPI      _Bit(22)  /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX       _Bit(23)  /* MMX supported */
#define CPUID_FEATURE_FXSR      _Bit(24)  /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE       _Bit(25)  /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2      _Bit(26)  /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS        _Bit(27)  /* Self-Snoop */
#define CPUID_FEATURE_HTT       _Bit(28)  /* Hyper-Threading Technology */
#define CPUID_FEATURE_TM        _Bit(29)  /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE       _Bit(31)  /* Pend Break Enable */
 
#define CPUID_FEATURE_SSE3      _HBit(0)  /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1)  /* PCLMULQDQ instruction */
#define CPUID_FEATURE_DTES64    _HBit(2)  /* 64-bit DS layout */
#define CPUID_FEATURE_MONITOR   _HBit(3)  /* Monitor/mwait */
#define CPUID_FEATURE_DSCPL     _HBit(4)  /* Debug Store CPL */
#define CPUID_FEATURE_VMX       _HBit(5)  /* VMX */
#define CPUID_FEATURE_SMX       _HBit(6)  /* SMX */
#define CPUID_FEATURE_EST       _HBit(7)  /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2       _HBit(8)  /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3     _HBit(9)  /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID       _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMA       _HBit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16      _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR      _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM      _HBit(15) /* Perf/Debug Capability MSR */

#define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA       _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1    _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2    _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIC    _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE     _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT    _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES       _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE     _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE   _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0	_HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_VMM       _HBit(31) /* VMM (Hypervisor) present */
#define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AVX1_0	_HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16C	_HBit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRAND	_HBit(30) /* RDRAND instruction */

/*
 * Leaf 7, subleaf 0 additional features.
 * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
 */
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)	/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_SMEP     _Bit(7)	/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_ENFSTRG  _Bit(9)	/* ENhanced Fast STRinG copy */
#define CPUID_LEAF7_FEATURE_TSCOFF   _Bit(1)	/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1     _Bit(3)	/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLE      _Bit(4)	/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2     _Bit(5)	/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_BMI2     _Bit(8)	/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_INVPCID  _Bit(10)	/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTM      _Bit(11)	/* TBD */

/*
 * The CPUID_EXTFEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: 
 */
#define CPUID_EXTFEATURE_SYSCALL   _Bit(11)	/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD	   _Bit(20)	/* eXecute Disable */

#define CPUID_EXTFEATURE_1GBPAGE   _Bit(26)	/* 1GB pages */
#define CPUID_EXTFEATURE_RDTSCP	   _Bit(27)	/* RDTSCP */
#define CPUID_EXTFEATURE_EM64T	   _Bit(29)	/* Extended Mem 64 Technology */

#define CPUID_EXTFEATURE_LAHF	   _HBit(0)	/* LAFH/SAHF instructions */

/*
 * The CPUID_EXTFEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: 
 */
#define CPUID_EXTFEATURE_TSCI      _Bit(8)	/* TSC Invariant */

#define	CPUID_CACHE_SIZE	16	/* Number of descriptor values */

#define CPUID_MWAIT_EXTENSION	_Bit(0)	/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK	_Bit(1)	/* interrupts are break events	   */

#define CPUID_MODEL_YONAH		0x0E
#define CPUID_MODEL_MEROM		0x0F
#define CPUID_MODEL_PENRYN		0x17
#define CPUID_MODEL_NEHALEM		0x1A
#define CPUID_MODEL_FIELDS		0x1E	/* Lynnfield, Clarksfield */
#define CPUID_MODEL_DALES		0x1F	/* Havendale, Auburndale */
#define CPUID_MODEL_NEHALEM_EX		0x2E
#define CPUID_MODEL_DALES_32NM		0x25	/* Clarkdale, Arrandale */
#define CPUID_MODEL_WESTMERE		0x2C	/* Gulftown, Westmere-EP/-WS */
#define CPUID_MODEL_WESTMERE_EX		0x2F
#define CPUID_MODEL_SANDYBRIDGE		0x2A
#define CPUID_MODEL_JAKETOWN		0x2D
#define CPUID_MODEL_IVYBRIDGE		0x3A
#ifdef PRIVATE
#define CPUID_MODEL_CRYSTALWELL		0x46
#endif
#define CPUID_MODEL_HASWELL		0x3C
#define CPUID_MODEL_HASWELL_SVR		0x3F
#define CPUID_MODEL_HASWELL_ULT		0x45

#define CPUID_VMM_FAMILY_UNKNOWN	0x0
#define CPUID_VMM_FAMILY_VMWARE		0x1

#ifndef ASSEMBLER
#include <stdint.h>
#include <mach/mach_types.h>
#include <kern/kern_types.h>
#include <mach/machine.h>


typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
static inline void
cpuid(uint32_t *data)
{
	asm("cpuid"
		: "=a" (data[eax]),
		  "=b" (data[ebx]),
		  "=c" (data[ecx]),
		  "=d" (data[edx])
		: "a"  (data[eax]),
		  "b"  (data[ebx]),
		  "c"  (data[ecx]),
		  "d"  (data[edx]));
}

static inline void
do_cpuid(uint32_t selector, uint32_t *data)
{
	asm("cpuid"
		: "=a" (data[0]),
		  "=b" (data[1]),
		  "=c" (data[2]),
		  "=d" (data[3])
		: "a"(selector),
		  "b" (0),
		  "c" (0),
		  "d" (0));
}

/*
 * Cache ID descriptor structure, used to parse CPUID leaf 2.
 * Note: not used in kernel.
 */
typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ; 
typedef struct {
	unsigned char	value;          /* Descriptor value */
	cache_type_t 	type;           /* Cache type */
	unsigned int 	size;           /* Cache size */
	unsigned int 	linesize;       /* Cache line size */
#ifdef KERNEL
	const char	*description;   /* Cache description */
#endif /* KERNEL */
} cpuid_cache_desc_t;  

#ifdef KERNEL
#define CACHE_DESC(value,type,size,linesize,text) \
	{ value, type, size, linesize, text }
#else
#define CACHE_DESC(value,type,size,linesize,text) \
	{ value, type, size, linesize }
#endif /* KERNEL */

/* Monitor/mwait Leaf: */
typedef struct {
	uint32_t	linesize_min;
	uint32_t	linesize_max;
	uint32_t	extensions;
	uint32_t	sub_Cstates;
} cpuid_mwait_leaf_t;

/* Thermal and Power Management Leaf: */
typedef struct {
	boolean_t	sensor;
	boolean_t	dynamic_acceleration;
	boolean_t	invariant_APIC_timer;
	boolean_t	core_power_limits;
	boolean_t	fine_grain_clock_mod;
	boolean_t	package_thermal_intr;
	uint32_t	thresholds;
	boolean_t	ACNT_MCNT;
	boolean_t	hardware_feedback;
	boolean_t	energy_policy;
} cpuid_thermal_leaf_t;


/* XSAVE Feature Leaf: */
typedef struct {
	uint32_t	extended_state[4];	/* eax .. edx */
} cpuid_xsave_leaf_t;


/* Architectural Performance Monitoring Leaf: */
typedef struct {
	uint8_t		version;
	uint8_t		number;
	uint8_t		width;
	uint8_t		events_number;
	uint32_t	events;
	uint8_t		fixed_number;
	uint8_t		fixed_width;
} cpuid_arch_perf_leaf_t;

/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
typedef struct {
	char		cpuid_vendor[16];
	char		cpuid_brand_string[48];
	const char	*cpuid_model_string;

	cpu_type_t	cpuid_type;	/* this is *not* a cpu_type_t in our <mach/machine.h> */
	uint8_t		cpuid_family;
	uint8_t		cpuid_model;
	uint8_t		cpuid_extmodel;
	uint8_t		cpuid_extfamily;
	uint8_t		cpuid_stepping;
	uint64_t	cpuid_features;
	uint64_t	cpuid_extfeatures;
	uint32_t	cpuid_signature;
	uint8_t   	cpuid_brand; 
	uint8_t		cpuid_processor_flag;
	
	uint32_t	cache_size[LCACHE_MAX];
	uint32_t	cache_linesize;

	uint8_t		cache_info[64];    /* list of cache descriptors */

	uint32_t	cpuid_cores_per_package;
	uint32_t	cpuid_logical_per_package;
	uint32_t	cache_sharing[LCACHE_MAX];
	uint32_t	cache_partitions[LCACHE_MAX];

	cpu_type_t	cpuid_cpu_type;			/* <mach/machine.h> */
	cpu_subtype_t	cpuid_cpu_subtype;		/* <mach/machine.h> */	

	/* Per-vendor info */
	cpuid_mwait_leaf_t	cpuid_mwait_leaf;	
#define cpuid_mwait_linesize_max	cpuid_mwait_leaf.linesize_max
#define cpuid_mwait_linesize_min	cpuid_mwait_leaf.linesize_min
#define cpuid_mwait_extensions		cpuid_mwait_leaf.extensions
#define cpuid_mwait_sub_Cstates		cpuid_mwait_leaf.sub_Cstates
	cpuid_thermal_leaf_t	cpuid_thermal_leaf;
	cpuid_arch_perf_leaf_t	cpuid_arch_perf_leaf;
	cpuid_xsave_leaf_t	cpuid_xsave_leaf;

	/* Cache details: */
	uint32_t	cpuid_cache_linesize;
	uint32_t	cpuid_cache_L2_associativity;
	uint32_t	cpuid_cache_size;

	/* Virtual and physical address aize: */
	uint32_t	cpuid_address_bits_physical;
	uint32_t	cpuid_address_bits_virtual;

	uint32_t	cpuid_microcode_version;

	/* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
	uint32_t	cpuid_tlb[2][2][2];
			#define	TLB_INST	0
			#define	TLB_DATA	1
			#define	TLB_SMALL	0
			#define	TLB_LARGE	1
	uint32_t	cpuid_stlb;

	uint32_t	core_count;
	uint32_t	thread_count;

	/* Max leaf ids available from CPUID */
	uint32_t	cpuid_max_basic;
	uint32_t	cpuid_max_ext;

	/* Family-specific info links */
	uint32_t		cpuid_cpufamily;
	cpuid_mwait_leaf_t	*cpuid_mwait_leafp;	
	cpuid_thermal_leaf_t	*cpuid_thermal_leafp;
	cpuid_arch_perf_leaf_t	*cpuid_arch_perf_leafp;
	cpuid_xsave_leaf_t	*cpuid_xsave_leafp;
	uint32_t		cpuid_leaf7_features;
} i386_cpu_info_t;

#ifdef MACH_KERNEL_PRIVATE
typedef struct {
	char		cpuid_vmm_vendor[16];
	uint32_t	cpuid_vmm_family;
	uint32_t	cpuid_vmm_bus_frequency;
	uint32_t	cpuid_vmm_tsc_frequency;
} i386_vmm_info_t;
#endif

#ifdef __cplusplus
extern "C" {
#endif

/*
 * External declarations
 */
extern cpu_type_t	cpuid_cputype(void);
extern cpu_subtype_t	cpuid_cpusubtype(void);
extern void		cpuid_cpu_display(const char *);
extern void		cpuid_feature_display(const char *);
extern void		cpuid_extfeature_display(const char *);
extern char *		cpuid_get_feature_names(uint64_t, char *, unsigned);
extern char *		cpuid_get_extfeature_names(uint64_t, char *, unsigned);
extern char *		cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);

extern uint64_t		cpuid_features(void);
extern uint64_t		cpuid_extfeatures(void);
extern uint64_t		cpuid_leaf7_features(void);
extern uint32_t		cpuid_family(void);
extern uint32_t		cpuid_cpufamily(void);
	
extern i386_cpu_info_t	*cpuid_info(void);
extern void		cpuid_set_info(void);

#ifdef MACH_KERNEL_PRIVATE
extern boolean_t	cpuid_vmm_present(void);
extern i386_vmm_info_t	*cpuid_vmm_info(void);
extern uint32_t		cpuid_vmm_family(void);
#endif

#ifdef __cplusplus
}
#endif

#endif /* ASSEMBLER */

#endif /* __APPLE_API_PRIVATE */
#endif /* _MACHINE_CPUID_H_ */
Commit	Line	Data
1c79356b	1	/*
2d21ac55	2	* Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
1c79356b	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
1c79356b	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b A	27	*/
	28	/*
	29	* @OSF_COPYRIGHT@
	30	*/
	31
	32	/*
	33	* x86 CPU identification
	34	*
1c79356b A	35	*/
	36
	37	#ifndef _MACHINE_CPUID_H_
	38	#define _MACHINE_CPUID_H_
	39
55e303ae A	40	#include <sys/appleapiopts.h>
	41
	42	#ifdef __APPLE_API_PRIVATE
	43
1c79356b	44	#define CPUID_VID_INTEL "GenuineIntel"
1c79356b	45	#define CPUID_VID_AMD "AuthenticAMD"
91447636	46
316670eb A	47	#define CPUID_VMM_ID_VMWARE "VMwareVMware"
316670eb A	48
91447636	49	#define CPUID_STRING_UNKNOWN "Unknown CPU Typ"
1c79356b	50
0c530ab8 A	51	#define _Bit(n) (1ULL << n)
	52	#define _HBit(n) (1ULL << ((n)+32))
	53
	54	/*
	55	* The CPUID_FEATURE_XXX values define 64-bit values
	56	* returned in %ecx:%edx to a CPUID request with %eax of 1:
	57	*/
060df5ea A	58	#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
	59	#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
	60	#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
	61	#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
	62	#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
	63	#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
	64	#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
	65	#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
	66	#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
	67	#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
	68	#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
	69	#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
	70	#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
	71	#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
	72	#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
	73	#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
	74	#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
	75	#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
	76	#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
	77	#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
	78	#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
	79	#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
	80	#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
	81	#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
	82	#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
	83	#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
	84	#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
	85	#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
	86	#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
	87
	88	#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
	89	#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
	90	#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
	91	#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
	92	#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
	93	#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
	94	#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
	95	#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
	96	#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
	97	#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
	98	#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
7ddcb079	99	#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
bd504ef0	100	#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
060df5ea A	101	#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
	102	#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
	103	#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
	104
7ddcb079	105	#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
060df5ea A	106	#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
	107	#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
	108	#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
bd504ef0	109	#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
060df5ea A	110	#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
060df5ea A	111	#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
7ddcb079	112	#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
060df5ea A	113	#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
	114	#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
	115	#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
060df5ea	116	#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
7ddcb079	117	#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
316670eb A	118	#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
	119	#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
	120	#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
	121	#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
	122	#define CPUID_FEATURE_F16C _HBit(29) /* Float16 convert instructions */
	123	#define CPUID_FEATURE_RDRAND _HBit(30) /* RDRAND instruction */
7ddcb079 A	124
	125	/*
	126	* Leaf 7, subleaf 0 additional features.
	127	* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
	128	*/
	129	#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */
39236c6e A	130	#define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */
39236c6e A	131	#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9) /* ENhanced Fast STRinG copy */
bd504ef0 A	132	#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1) /* TSC thread offset */
	133	#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3) /* Bit Manipulation Instrs, set 1 */
	134	#define CPUID_LEAF7_FEATURE_HLE _Bit(4) /* Hardware Lock Elision*/
	135	#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5) /* AVX2 Instructions */
bd504ef0	136	#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8) /* Bit Manipulation Instrs, set 2 */
bd504ef0 A	137	#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10) /* INVPCID intruction, TDB */
bd504ef0 A	138	#define CPUID_LEAF7_FEATURE_RTM _Bit(11) /* TBD */
0c530ab8 A	139
	140	/*
	141	* The CPUID_EXTFEATURE_XXX values define 64-bit values
	142	* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
	143	*/
	144	#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
	145	#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
b7266188	146
060df5ea	147	#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1GB pages */
c910b4d9	148	#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
0c530ab8 A	149	#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
0c530ab8 A	150
060df5ea	151	#define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAFH/SAHF instructions */
0c530ab8	152
c910b4d9 A	153	/*
	154	* The CPUID_EXTFEATURE_XXX values define 64-bit values
	155	* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
	156	*/
	157	#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
	158
b0d623f7	159	#define CPUID_CACHE_SIZE 16 /* Number of descriptor values */
1c79356b	160
2d21ac55 A	161	#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
	162	#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
	163
39236c6e A	164	#define CPUID_MODEL_YONAH 0x0E
	165	#define CPUID_MODEL_MEROM 0x0F
	166	#define CPUID_MODEL_PENRYN 0x17
	167	#define CPUID_MODEL_NEHALEM 0x1A
	168	#define CPUID_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield */
	169	#define CPUID_MODEL_DALES 0x1F /* Havendale, Auburndale */
	170	#define CPUID_MODEL_NEHALEM_EX 0x2E
	171	#define CPUID_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */
	172	#define CPUID_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP/-WS */
	173	#define CPUID_MODEL_WESTMERE_EX 0x2F
	174	#define CPUID_MODEL_SANDYBRIDGE 0x2A
	175	#define CPUID_MODEL_JAKETOWN 0x2D
	176	#define CPUID_MODEL_IVYBRIDGE 0x3A
	177	#ifdef PRIVATE
	178	#define CPUID_MODEL_CRYSTALWELL 0x46
	179	#endif
	180	#define CPUID_MODEL_HASWELL 0x3C
	181	#define CPUID_MODEL_HASWELL_SVR 0x3F
	182	#define CPUID_MODEL_HASWELL_ULT 0x45
7ddcb079	183
316670eb A	184	#define CPUID_VMM_FAMILY_UNKNOWN 0x0
	185	#define CPUID_VMM_FAMILY_VMWARE 0x1
	186
1c79356b	187	#ifndef ASSEMBLER
55e303ae A	188	#include <stdint.h>
	189	#include <mach/mach_types.h>
	190	#include <kern/kern_types.h>
1c79356b A	191	#include <mach/machine.h>
1c79356b A	192
1c79356b	193
0c530ab8 A	194	typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
	195	static inline void
	196	cpuid(uint32_t *data)
	197	{
	198	asm("cpuid"
	199	: "=a" (data[eax]),
	200	"=b" (data[ebx]),
	201	"=c" (data[ecx]),
	202	"=d" (data[edx])
	203	: "a" (data[eax]),
	204	"b" (data[ebx]),
	205	"c" (data[ecx]),
	206	"d" (data[edx]));
	207	}
060df5ea	208
55e303ae A	209	static inline void
	210	do_cpuid(uint32_t selector, uint32_t *data)
	211	{
	212	asm("cpuid"
	213	: "=a" (data[0]),
	214	"=b" (data[1]),
	215	"=c" (data[2]),
	216	"=d" (data[3])
060df5ea A	217	: "a"(selector),
	218	"b" (0),
	219	"c" (0),
	220	"d" (0));
55e303ae	221	}
1c79356b A	222
1c79356b A	223	/*
2d21ac55 A	224	* Cache ID descriptor structure, used to parse CPUID leaf 2.
2d21ac55 A	225	* Note: not used in kernel.
1c79356b	226	*/
91447636	227	typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
55e303ae A	228	typedef struct {
	229	unsigned char value; /* Descriptor value */
	230	cache_type_t type; /* Cache type */
	231	unsigned int size; /* Cache size */
	232	unsigned int linesize; /* Cache line size */
	233	#ifdef KERNEL
91447636	234	const char description; / Cache description */
55e303ae A	235	#endif /* KERNEL */
	236	} cpuid_cache_desc_t;
	237
	238	#ifdef KERNEL
	239	#define CACHE_DESC(value,type,size,linesize,text) \
	240	{ value, type, size, linesize, text }
	241	#else
	242	#define CACHE_DESC(value,type,size,linesize,text) \
	243	{ value, type, size, linesize }
	244	#endif /* KERNEL */
	245
7e4a7d39 A	246	/* Monitor/mwait Leaf: */
	247	typedef struct {
	248	uint32_t linesize_min;
	249	uint32_t linesize_max;
	250	uint32_t extensions;
	251	uint32_t sub_Cstates;
	252	} cpuid_mwait_leaf_t;
	253
	254	/* Thermal and Power Management Leaf: */
	255	typedef struct {
	256	boolean_t sensor;
	257	boolean_t dynamic_acceleration;
b7266188	258	boolean_t invariant_APIC_timer;
060df5ea A	259	boolean_t core_power_limits;
	260	boolean_t fine_grain_clock_mod;
	261	boolean_t package_thermal_intr;
7e4a7d39 A	262	uint32_t thresholds;
7e4a7d39 A	263	boolean_t ACNT_MCNT;
060df5ea A	264	boolean_t hardware_feedback;
060df5ea A	265	boolean_t energy_policy;
7e4a7d39 A	266	} cpuid_thermal_leaf_t;
7e4a7d39 A	267
060df5ea A	268
	269	/* XSAVE Feature Leaf: */
	270	typedef struct {
	271	uint32_t extended_state[4]; /* eax .. edx */
	272	} cpuid_xsave_leaf_t;
	273
	274
7e4a7d39 A	275	/* Architectural Performance Monitoring Leaf: */
	276	typedef struct {
	277	uint8_t version;
	278	uint8_t number;
	279	uint8_t width;
	280	uint8_t events_number;
	281	uint32_t events;
	282	uint8_t fixed_number;
	283	uint8_t fixed_width;
	284	} cpuid_arch_perf_leaf_t;
	285
0c530ab8	286	/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
55e303ae A	287	typedef struct {
	288	char cpuid_vendor[16];
	289	char cpuid_brand_string[48];
91447636	290	const char *cpuid_model_string;
55e303ae	291
7e4a7d39	292	cpu_type_t cpuid_type; /* this is not a cpu_type_t in our <mach/machine.h> */
55e303ae A	293	uint8_t cpuid_family;
	294	uint8_t cpuid_model;
	295	uint8_t cpuid_extmodel;
	296	uint8_t cpuid_extfamily;
	297	uint8_t cpuid_stepping;
0c530ab8 A	298	uint64_t cpuid_features;
0c530ab8 A	299	uint64_t cpuid_extfeatures;
55e303ae A	300	uint32_t cpuid_signature;
55e303ae A	301	uint8_t cpuid_brand;
6d2010ae	302	uint8_t cpuid_processor_flag;
55e303ae A	303
	304	uint32_t cache_size[LCACHE_MAX];
	305	uint32_t cache_linesize;
	306
55e303ae A	307	uint8_t cache_info[64]; /* list of cache descriptors */
55e303ae A	308
0c530ab8 A	309	uint32_t cpuid_cores_per_package;
	310	uint32_t cpuid_logical_per_package;
	311	uint32_t cache_sharing[LCACHE_MAX];
2d21ac55	312	uint32_t cache_partitions[LCACHE_MAX];
0c530ab8	313
2d21ac55	314	cpu_type_t cpuid_cpu_type; /* <mach/machine.h> */
0c530ab8	315	cpu_subtype_t cpuid_cpu_subtype; /* <mach/machine.h> */
2d21ac55	316
7e4a7d39 A	317	/* Per-vendor info */
	318	cpuid_mwait_leaf_t cpuid_mwait_leaf;
	319	#define cpuid_mwait_linesize_max cpuid_mwait_leaf.linesize_max
	320	#define cpuid_mwait_linesize_min cpuid_mwait_leaf.linesize_min
	321	#define cpuid_mwait_extensions cpuid_mwait_leaf.extensions
	322	#define cpuid_mwait_sub_Cstates cpuid_mwait_leaf.sub_Cstates
	323	cpuid_thermal_leaf_t cpuid_thermal_leaf;
	324	cpuid_arch_perf_leaf_t cpuid_arch_perf_leaf;
060df5ea	325	cpuid_xsave_leaf_t cpuid_xsave_leaf;
7e4a7d39	326
2d21ac55 A	327	/* Cache details: */
	328	uint32_t cpuid_cache_linesize;
	329	uint32_t cpuid_cache_L2_associativity;
	330	uint32_t cpuid_cache_size;
	331
	332	/* Virtual and physical address aize: */
	333	uint32_t cpuid_address_bits_physical;
	334	uint32_t cpuid_address_bits_virtual;
593a1d5f A	335
	336	uint32_t cpuid_microcode_version;
	337
b0d623f7 A	338	/* Numbers of tlbs per processor [i\|d, small\|large, level0\|level1] */
	339	uint32_t cpuid_tlb[2][2][2];
	340	#define TLB_INST 0
	341	#define TLB_DATA 1
	342	#define TLB_SMALL 0
	343	#define TLB_LARGE 1
	344	uint32_t cpuid_stlb;
593a1d5f A	345
	346	uint32_t core_count;
	347	uint32_t thread_count;
	348
b0d623f7 A	349	/* Max leaf ids available from CPUID */
	350	uint32_t cpuid_max_basic;
	351	uint32_t cpuid_max_ext;
7e4a7d39 A	352
	353	/* Family-specific info links */
	354	uint32_t cpuid_cpufamily;
	355	cpuid_mwait_leaf_t *cpuid_mwait_leafp;
	356	cpuid_thermal_leaf_t *cpuid_thermal_leafp;
	357	cpuid_arch_perf_leaf_t *cpuid_arch_perf_leafp;
060df5ea	358	cpuid_xsave_leaf_t *cpuid_xsave_leafp;
7ddcb079	359	uint32_t cpuid_leaf7_features;
55e303ae	360	} i386_cpu_info_t;
1c79356b	361
316670eb A	362	#ifdef MACH_KERNEL_PRIVATE
	363	typedef struct {
	364	char cpuid_vmm_vendor[16];
	365	uint32_t cpuid_vmm_family;
	366	uint32_t cpuid_vmm_bus_frequency;
	367	uint32_t cpuid_vmm_tsc_frequency;
	368	} i386_vmm_info_t;
	369	#endif
	370
91447636 A	371	#ifdef __cplusplus
	372	extern "C" {
	373	#endif
1c79356b A	374
	375	/*
	376	* External declarations
	377	*/
0c530ab8 A	378	extern cpu_type_t cpuid_cputype(void);
	379	extern cpu_subtype_t cpuid_cpusubtype(void);
	380	extern void cpuid_cpu_display(const char *);
	381	extern void cpuid_feature_display(const char *);
	382	extern void cpuid_extfeature_display(const char *);
	383	extern char * cpuid_get_feature_names(uint64_t, char *, unsigned);
	384	extern char * cpuid_get_extfeature_names(uint64_t, char *, unsigned);
7ddcb079	385	extern char * cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);
0c530ab8 A	386
	387	extern uint64_t cpuid_features(void);
	388	extern uint64_t cpuid_extfeatures(void);
7ddcb079	389	extern uint64_t cpuid_leaf7_features(void);
55e303ae	390	extern uint32_t cpuid_family(void);
7e4a7d39	391	extern uint32_t cpuid_cpufamily(void);
91447636	392
91447636	393	extern i386_cpu_info_t *cpuid_info(void);
0c530ab8	394	extern void cpuid_set_info(void);
1c79356b	395
316670eb A	396	#ifdef MACH_KERNEL_PRIVATE
	397	extern boolean_t cpuid_vmm_present(void);
	398	extern i386_vmm_info_t *cpuid_vmm_info(void);
	399	extern uint32_t cpuid_vmm_family(void);
	400	#endif
	401
91447636 A	402	#ifdef __cplusplus
	403	}
	404	#endif
55e303ae	405
1c79356b	406	#endif /* ASSEMBLER */
55e303ae A	407
55e303ae A	408	#endif /* __APPLE_API_PRIVATE */
1c79356b	409	#endif /* _MACHINE_CPUID_H_ */