[apple/xnu.git] / osfmk / i386 / cpuid.h

/*
 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */

/*
 * x86 CPU identification
 *
 */

#ifndef _MACHINE_CPUID_H_
#define _MACHINE_CPUID_H_

#include <sys/appleapiopts.h>

#ifdef __APPLE_API_PRIVATE

#define	CPUID_VID_INTEL		"GenuineIntel"
#define	CPUID_VID_AMD		"AuthenticAMD"

#define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"

#define _Bit(n)			(1ULL << n)
#define _HBit(n)		(1ULL << ((n)+32))

/*
 * The CPUID_FEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 1: 
 */
#define	CPUID_FEATURE_FPU     _Bit(0)	/* Floating point unit on-chip */
#define	CPUID_FEATURE_VME     _Bit(1)	/* Virtual Mode Extension */
#define	CPUID_FEATURE_DE      _Bit(2)	/* Debugging Extension */
#define	CPUID_FEATURE_PSE     _Bit(3)	/* Page Size Extension */
#define	CPUID_FEATURE_TSC     _Bit(4)	/* Time Stamp Counter */
#define	CPUID_FEATURE_MSR     _Bit(5)	/* Model Specific Registers */
#define CPUID_FEATURE_PAE     _Bit(6)	/* Physical Address Extension */
#define	CPUID_FEATURE_MCE     _Bit(7)	/* Machine Check Exception */
#define	CPUID_FEATURE_CX8     _Bit(8)	/* CMPXCHG8B */
#define	CPUID_FEATURE_APIC    _Bit(9)	/* On-chip APIC */
#define CPUID_FEATURE_SEP     _Bit(11)	/* Fast System Call */
#define	CPUID_FEATURE_MTRR    _Bit(12)	/* Memory Type Range Register */
#define	CPUID_FEATURE_PGE     _Bit(13)	/* Page Global Enable */
#define	CPUID_FEATURE_MCA     _Bit(14)	/* Machine Check Architecture */
#define	CPUID_FEATURE_CMOV    _Bit(15)	/* Conditional Move Instruction */
#define CPUID_FEATURE_PAT     _Bit(16)	/* Page Attribute Table */
#define CPUID_FEATURE_PSE36   _Bit(17)	/* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN     _Bit(18)	/* Processor Serial Number */
#define CPUID_FEATURE_CLFSH   _Bit(19)	/* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS      _Bit(21)	/* Debug Store */
#define CPUID_FEATURE_ACPI    _Bit(22)	/* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX     _Bit(23)	/* MMX supported */
#define CPUID_FEATURE_FXSR    _Bit(24)	/* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE     _Bit(25)	/* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2    _Bit(26)	/* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS      _Bit(27)	/* Self-Snoop */
#define CPUID_FEATURE_HTT     _Bit(28)	/* Hyper-Threading Technology */
#define CPUID_FEATURE_TM      _Bit(29)	/* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE     _Bit(31)	/* Pend Break Enable */

#define CPUID_FEATURE_SSE3    _HBit(0)	/* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_MONITOR _HBit(3)	/* Monitor/mwait */
#define CPUID_FEATURE_DSCPL   _HBit(4)	/* Debug Store CPL */
#define CPUID_FEATURE_VMX     _HBit(5)	/* VMX */
#define CPUID_FEATURE_SMX     _HBit(6)	/* SMX */
#define CPUID_FEATURE_EST     _HBit(7)	/* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2     _HBit(8)	/* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3   _HBit(9)	/* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID     _HBit(10)	/* L1 Context ID */
#define CPUID_FEATURE_CX16    _HBit(13)	/* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR    _HBit(14)	/* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM    _HBit(15)	/* Perf/Debug Capability MSR */
#define CPUID_FEATURE_DCA     _HBit(18)	/* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1  _HBit(19)	/* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2  _HBit(20)	/* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_xAPIC   _HBit(21)	/* Extended APIC Mode */
#define CPUID_FEATURE_POPCNT  _HBit(23)	/* POPCNT instruction */

/*
 * The CPUID_EXTFEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: 
 */
#define CPUID_EXTFEATURE_SYSCALL   _Bit(11)	/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD	   _Bit(20)	/* eXecute Disable */
#define CPUID_EXTFEATURE_RDTSCP	   _Bit(27)	/* RDTSCP */
#define CPUID_EXTFEATURE_EM64T	   _Bit(29)	/* Extended Mem 64 Technology */

#define CPUID_EXTFEATURE_LAHF	   _HBit(20)	/* LAFH/SAHF instructions */

/*
 * The CPUID_EXTFEATURE_XXX values define 64-bit values
 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: 
 */
#define CPUID_EXTFEATURE_TSCI      _Bit(8)	/* TSC Invariant */


#define	CPUID_CACHE_SIZE	16	/* Number of descriptor vales */

#define	CPUID_CACHE_NULL	   0x00	/* NULL */
#define	CPUID_CACHE_ITLB_4K_32_4   0x01	/* Inst TLB: 4K pages, 32 ents, 4-way */
#define	CPUID_CACHE_ITLB_4M_2	   0x02	/* Inst TLB: 4M pages, 2 ents */
#define	CPUID_CACHE_DTLB_4K_64_4   0x03	/* Data TLB: 4K pages, 64 ents, 4-way */
#define	CPUID_CACHE_DTLB_4M_8_4	   0x04	/* Data TLB: 4M pages, 8 ents, 4-way */
#define	CPUID_CACHE_DTLB_4M_32_4   0x05	/* Data TLB: 4M pages, 32 ents, 4-way */
#define	CPUID_CACHE_L1I_8K	   0x06	/* Icache: 8K */
#define	CPUID_CACHE_L1I_16K	   0x08	/* Icache: 16K */
#define	CPUID_CACHE_L1I_32K	   0x09	/* Icache: 32K, 4-way, 64 bytes */
#define	CPUID_CACHE_L1D_8K	   0x0A	/* Dcache: 8K */
#define	CPUID_CACHE_L1D_16K        0x0C	/* Dcache: 16K */
#define	CPUID_CACHE_L1D_16K_4_32   0x0D /* Dcache: 16K, 4-way, 64 byte, ECC */
#define CPUID_CACHE_L2_256K_8_64   0x21 /* L2: 256K, 8-way, 64 bytes */
#define CPUID_CACHE_L3_512K        0x22 /* L3: 512K */
#define CPUID_CACHE_L3_1M          0x23 /* L3: 1M */
#define CPUID_CACHE_L3_2M          0x25 /* L3: 2M */
#define CPUID_CACHE_L3_4M          0x29 /* L3: 4M */
#define CPUID_CACHE_L1D_32K_8      0x2C /* Dcache: 32K, 8-way, 64 byte */
#define CPUID_CACHE_L1I_32K_8      0x30 /* Icache: 32K, 8-way */
#define CPUID_CACHE_L2_128K_S4     0x39 /* L2: 128K, 4-way, sectored */
#define CPUID_CACHE_L2_128K_S2     0x3B /* L2: 128K, 2-way, sectored */
#define CPUID_CACHE_L2_256K_S4     0x3C /* L2: 256K, 4-way, sectored */
#define CPUID_CACHE_NOCACHE        0x40 /* No 2nd level or 3rd-level cache */
#define	CPUID_CACHE_L2_128K	   0x41	/* L2: 128K */
#define	CPUID_CACHE_L2_256K	   0x42	/* L2: 256K */
#define	CPUID_CACHE_L2_512K	   0x43	/* L2: 512K */
#define	CPUID_CACHE_L2_1M_4	   0x44	/* L2: 1M, 4-way */
#define	CPUID_CACHE_L2_2M_4	   0x45	/* L2: 2M, 4-way */
#define CPUID_CACHE_L3_4M_4_64     0x46 /* L3:  4M,  4-way, 64 bytes */
#define CPUID_CACHE_L3_8M_8_64     0x47 /* L3:  8M,  8-way, 64 bytes*/
#define CPUID_CACHE_L2_3M_12_64    0x48 /* L3:  3M,  8-way, 64 bytes*/
#define CPUID_CACHE_L2_4M_16_64    0x49 /* L2:  4M, 16-way, 64 bytes */
#define CPUID_CACHE_L2_6M_12_64    0x4A /* L2:  6M, 12-way, 64 bytes */
#define CPUID_CACHE_L2_8M_16_64    0x4B /* L2:  8M, 16-way, 64 bytes */
#define CPUID_CACHE_L2_12M_12_64   0x4C /* L2: 12M, 12-way, 64 bytes */
#define CPUID_CACHE_L2_16M_16_64   0x4D /* L2: 16M, 16-way, 64 bytes */
#define CPUID_CACHE_L2_6M_24_64    0x4E /* L2:  6M, 24-way, 64 bytes */
#define CPUID_CACHE_ITLB_64        0x50 /* Inst TLB: 64 entries */
#define CPUID_CACHE_ITLB_128       0x51 /* Inst TLB: 128 entries */
#define CPUID_CACHE_ITLB_256       0x52 /* Inst TLB: 256 entries */
#define CPUID_CACHE_ITLB_4M2M_7    0x55 /* Inst TLB: 4M/2M, 7 entries */
#define CPUID_CACHE_DTLB_4M_16_4   0x56 /* Data TLB: 4M, 16 entries, 4-way */
#define CPUID_CACHE_DTLB_4K_16_4   0x57 /* Data TLB: 4K, 16 entries, 4-way */
#define CPUID_CACHE_DTLB_4M2M_32_4 0x5A /* Data TLB: 4M/2M, 32 entries */
#define CPUID_CACHE_DTLB_64        0x5B /* Data TLB: 64 entries */
#define CPUID_CACHE_DTLB_128       0x5C /* Data TLB: 128 entries */
#define CPUID_CACHE_DTLB_256       0x5D /* Data TLB: 256 entries */
#define	CPUID_CACHE_L1D_16K_8_64   0x60 /* Data cache: 16K, 8-way, 64 bytes */
#define	CPUID_CACHE_L1D_8K_4_64    0x66 /* Data cache:  8K, 4-way, 64 bytes */
#define	CPUID_CACHE_L1D_16K_4_64   0x67 /* Data cache: 16K, 4-way, 64 bytes */
#define	CPUID_CACHE_L1D_32K_4_64   0x68 /* Data cache: 32K, 4-way, 64 bytes */
#define CPUID_CACHE_TRACE_12K_8    0x70 /* Trace cache 12K-uop, 8-way */
#define CPUID_CACHE_TRACE_16K_8    0x71 /* Trace cache 16K-uop, 8-way */
#define CPUID_CACHE_TRACE_32K_8    0x72 /* Trace cache 32K-uop, 8-way */
#define	CPUID_CACHE_L2_1M_4_64     0x78 /* L2:   1M, 4-way, 64 bytes */
#define	CPUID_CACHE_L2_128K_8_64_2 0x79 /* L2: 128K, 8-way, 64b, 2 lines/sec */
#define	CPUID_CACHE_L2_256K_8_64_2 0x7A /* L2: 256K, 8-way, 64b, 2 lines/sec */
#define	CPUID_CACHE_L2_512K_8_64_2 0x7B /* L2: 512K, 8-way, 64b, 2 lines/sec */
#define	CPUID_CACHE_L2_1M_8_64_2   0x7C /* L2:   1M, 8-way, 64b, 2 lines/sec */
#define	CPUID_CACHE_L2_2M_8_64     0x7D /* L2:   2M, 8-way, 64 bytes */
#define	CPUID_CACHE_L2_512K_2_64   0x7F /* L2: 512K, 2-way, 64 bytes */
#define CPUID_CACHE_L2_256K_8_32   0x82 /* L2: 256K, 8-way, 32 bytes */
#define CPUID_CACHE_L2_512K_8_32   0x83 /* L2: 512K, 8-way, 32 bytes */
#define CPUID_CACHE_L2_1M_8_32     0x84 /* L2:   1M, 8-way, 32 bytes */
#define CPUID_CACHE_L2_2M_8_32     0x85 /* L2:   2M, 8-way, 32 bytes */
#define CPUID_CACHE_L2_512K_4_64   0x86 /* L2: 512K, 4-way, 64 bytes */
#define CPUID_CACHE_L2_1M_8_64     0x87 /* L2:   1M, 8-way, 64 bytes */
#define CPUID_CACHE_ITLB_4K_128_4  0xB0 /* ITLB: 4KB, 128 entries, 4-way */
#define CPUID_CACHE_ITLB_4M_4_4    0xB1 /* ITLB: 4MB,   4 entries, 4-way, or  */
#define CPUID_CACHE_ITLB_2M_8_4    0xB1 /* ITLB: 2MB,   8 entries, 4-way, or  */
#define CPUID_CACHE_ITLB_4M_8      0xB1 /* ITLB: 4MB,   8 entries */
#define CPUID_CACHE_ITLB_4K_64_4   0xB2 /* ITLB: 4KB,  64 entries, 4-way */
#define CPUID_CACHE_DTLB_4K_128_4  0xB3 /* DTLB: 4KB, 128 entries, 4-way */
#define CPUID_CACHE_DTLB_4K_256_4  0xB4 /* DTLB: 4KB, 256 entries, 4-way */
#define CPUID_CACHE_2TLB_4K_512_4  0xB4 /* 2nd-level TLB: 4KB, 512, 4-way */
#define CPUID_CACHE_L3_512K_4_64   0xD0 /* L3: 512KB, 4-way, 64 bytes */
#define CPUID_CACHE_L3_1M_4_64     0xD1 /* L3:    1M, 4-way, 64 bytes */
#define CPUID_CACHE_L3_2M_4_64     0xD2 /* L3:    2M, 4-way, 64 bytes */
#define CPUID_CACHE_L3_1M_8_64     0xD6 /* L3:    1M, 8-way, 64 bytes */
#define CPUID_CACHE_L3_2M_8_64     0xD7 /* L3:    2M, 8-way, 64 bytes */
#define CPUID_CACHE_L3_4M_8_64     0xD8 /* L3:    4M, 8-way, 64 bytes */
#define CPUID_CACHE_L3_1M5_12_64   0xDC /* L3:  1.5M, 12-way, 64 bytes */
#define CPUID_CACHE_L3_3M_12_64    0xDD /* L3:    3M, 12-way, 64 bytes */
#define CPUID_CACHE_L3_6M_12_64    0xDE /* L3:    6M, 12-way, 64 bytes */
#define CPUID_CACHE_L3_2M_16_64    0xE2 /* L3:    2M, 16-way, 64 bytes */
#define CPUID_CACHE_L3_4M_16_64    0xE3 /* L3:    4M, 16-way, 64 bytes */
#define CPUID_CACHE_L3_8M_16_64    0xE4 /* L3:    8M, 16-way, 64 bytes */
#define CPUID_CACHE_PREFETCH_64    0xF0 /* 64-Byte Prefetching */
#define CPUID_CACHE_PREFETCH_128   0xF1 /* 128-Byte Prefetching */

#define CPUID_MWAIT_EXTENSION	_Bit(0)	/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK	_Bit(1)	/* interrupts are break events	   */

#define CPUID_MODEL_YONAH	14
#define CPUID_MODEL_MEROM	15
#define CPUID_MODEL_PENRYN	23
#define CPUID_MODEL_NEHALEM	26

#ifndef ASSEMBLER
#include <stdint.h>
#include <mach/mach_types.h>
#include <kern/kern_types.h>
#include <mach/machine.h>


typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
static inline void
cpuid(uint32_t *data)
{
	asm("cpuid"
		: "=a" (data[eax]),
		  "=b" (data[ebx]),
		  "=c" (data[ecx]),
		  "=d" (data[edx])
		: "a"  (data[eax]),
		  "b"  (data[ebx]),
		  "c"  (data[ecx]),
		  "d"  (data[edx]));
}
static inline void
do_cpuid(uint32_t selector, uint32_t *data)
{
	asm("cpuid"
		: "=a" (data[0]),
		  "=b" (data[1]),
		  "=c" (data[2]),
		  "=d" (data[3])
		: "a"(selector));
}

/*
 * Cache ID descriptor structure, used to parse CPUID leaf 2.
 * Note: not used in kernel.
 */
typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ; 
typedef struct {
	unsigned char	value;          /* Descriptor value */
	cache_type_t 	type;           /* Cache type */
	unsigned int 	size;           /* Cache size */
	unsigned int 	linesize;       /* Cache line size */
#ifdef KERNEL
	const char	*description;   /* Cache description */
#endif /* KERNEL */
} cpuid_cache_desc_t;  

#ifdef KERNEL
#define CACHE_DESC(value,type,size,linesize,text) \
	{ value, type, size, linesize, text }
#else
#define CACHE_DESC(value,type,size,linesize,text) \
	{ value, type, size, linesize }
#endif /* KERNEL */

/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
typedef struct {
	char		cpuid_vendor[16];
	char		cpuid_brand_string[48];
	const char	*cpuid_model_string;

	cpu_type_t	cpuid_type;					/* this is *not* a cpu_type_t in our <mach/machine.h> */
	uint8_t		cpuid_family;
	uint8_t		cpuid_model;
	uint8_t		cpuid_extmodel;
	uint8_t		cpuid_extfamily;
	uint8_t		cpuid_stepping;
	uint64_t	cpuid_features;
	uint64_t	cpuid_extfeatures;
	uint32_t	cpuid_signature;
	uint8_t   	cpuid_brand; 
	
	uint32_t	cache_size[LCACHE_MAX];
	uint32_t	cache_linesize;

	uint8_t		cache_info[64];    /* list of cache descriptors */

	uint32_t	cpuid_cores_per_package;
	uint32_t	cpuid_logical_per_package;
	uint32_t	cache_sharing[LCACHE_MAX];
	uint32_t	cache_partitions[LCACHE_MAX];

	cpu_type_t	cpuid_cpu_type;			/* <mach/machine.h> */
	cpu_subtype_t	cpuid_cpu_subtype;		/* <mach/machine.h> */	

	/* Monitor/mwait Leaf: */
	uint32_t	cpuid_mwait_linesize_min;
	uint32_t	cpuid_mwait_linesize_max;
	uint32_t	cpuid_mwait_extensions;
	uint32_t	cpuid_mwait_sub_Cstates;

	/* Thermal and Power Management Leaf: */
	boolean_t	cpuid_thermal_sensor;
	boolean_t	cpuid_thermal_dynamic_acceleration;
	uint32_t	cpuid_thermal_thresholds;
	boolean_t	cpuid_thermal_ACNT_MCNT;

	/* Architectural Performance Monitoring Leaf: */
	uint8_t		cpuid_arch_perf_version;
	uint8_t		cpuid_arch_perf_number;
	uint8_t		cpuid_arch_perf_width;
	uint8_t		cpuid_arch_perf_events_number;
	uint32_t	cpuid_arch_perf_events;
	uint8_t		cpuid_arch_perf_fixed_number;
	uint8_t		cpuid_arch_perf_fixed_width;
	
	/* Cache details: */
	uint32_t	cpuid_cache_linesize;
	uint32_t	cpuid_cache_L2_associativity;
	uint32_t	cpuid_cache_size;

	/* Virtual and physical address aize: */
	uint32_t	cpuid_address_bits_physical;
	uint32_t	cpuid_address_bits_virtual;

	uint32_t	cpuid_microcode_version;

	/* Numbers of tlbs per processor */
	uint32_t	cpuid_itlb_small;
	uint32_t	cpuid_dtlb_small;
	uint32_t	cpuid_itlb_large;
	uint32_t	cpuid_dtlb_large;

	uint32_t	core_count;
	uint32_t	thread_count;

} i386_cpu_info_t;

#ifdef __cplusplus
extern "C" {
#endif

/*
 * External declarations
 */
extern cpu_type_t	cpuid_cputype(void);
extern cpu_subtype_t	cpuid_cpusubtype(void);
extern void		cpuid_cpu_display(const char *);
extern void		cpuid_feature_display(const char *);
extern void		cpuid_extfeature_display(const char *);
extern char *		cpuid_get_feature_names(uint64_t, char *, unsigned);
extern char *		cpuid_get_extfeature_names(uint64_t, char *, unsigned);

extern uint64_t		cpuid_features(void);
extern uint64_t		cpuid_extfeatures(void);
extern uint32_t		cpuid_family(void);
	
extern void		cpuid_get_info(i386_cpu_info_t *info_p);
extern i386_cpu_info_t	*cpuid_info(void);

extern void		cpuid_set_info(void);

#ifdef __cplusplus
}
#endif

#endif /* ASSEMBLER */

#endif /* __APPLE_API_PRIVATE */
#endif /* _MACHINE_CPUID_H_ */
Commit	Line	Data
1c79356b	1	/*
2d21ac55	2	* Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
1c79356b	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
1c79356b	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b A	27	*/
	28	/*
	29	* @OSF_COPYRIGHT@
	30	*/
	31
	32	/*
	33	* x86 CPU identification
	34	*
1c79356b A	35	*/
	36
	37	#ifndef _MACHINE_CPUID_H_
	38	#define _MACHINE_CPUID_H_
	39
55e303ae A	40	#include <sys/appleapiopts.h>
	41
	42	#ifdef __APPLE_API_PRIVATE
	43
1c79356b	44	#define CPUID_VID_INTEL "GenuineIntel"
1c79356b	45	#define CPUID_VID_AMD "AuthenticAMD"
91447636 A	46
91447636 A	47	#define CPUID_STRING_UNKNOWN "Unknown CPU Typ"
1c79356b	48
0c530ab8 A	49	#define _Bit(n) (1ULL << n)
	50	#define _HBit(n) (1ULL << ((n)+32))
	51
	52	/*
	53	* The CPUID_FEATURE_XXX values define 64-bit values
	54	* returned in %ecx:%edx to a CPUID request with %eax of 1:
	55	*/
	56	#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
	57	#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
	58	#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
	59	#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
	60	#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
	61	#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
	62	#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
	63	#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
	64	#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
	65	#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
	66	#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
	67	#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
	68	#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
	69	#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
	70	#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
	71	#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
	72	#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
	73	#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
	74	#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
	75	#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
	76	#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
	77	#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
	78	#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
	79	#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
	80	#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
	81	#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
	82	#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
	83	#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
	84	#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
	85
2d21ac55	86	#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
0c530ab8 A	87	#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
	88	#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
	89	#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
	90	#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
	91	#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
	92	#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
	93	#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
0c530ab8 A	94	#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
	95	#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
	96	#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
	97	#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
593a1d5f	98	#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
0c530ab8	99	#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
593a1d5f A	100	#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
593a1d5f A	101	#define CPUID_FEATURE_xAPIC _HBit(21) /* Extended APIC Mode */
0c530ab8 A	102	#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
	103
	104	/*
	105	* The CPUID_EXTFEATURE_XXX values define 64-bit values
	106	* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
	107	*/
	108	#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
	109	#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
c910b4d9	110	#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
0c530ab8 A	111	#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
	112
	113	#define CPUID_EXTFEATURE_LAHF _HBit(20) /* LAFH/SAHF instructions */
	114
c910b4d9 A	115	/*
	116	* The CPUID_EXTFEATURE_XXX values define 64-bit values
	117	* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
	118	*/
	119	#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
	120
	121
1c79356b	122	#define CPUID_CACHE_SIZE 16 /* Number of descriptor vales */
1c79356b A	123
1c79356b A	124	#define CPUID_CACHE_NULL 0x00 /* NULL */
593a1d5f A	125	#define CPUID_CACHE_ITLB_4K_32_4 0x01 /* Inst TLB: 4K pages, 32 ents, 4-way */
	126	#define CPUID_CACHE_ITLB_4M_2 0x02 /* Inst TLB: 4M pages, 2 ents */
	127	#define CPUID_CACHE_DTLB_4K_64_4 0x03 /* Data TLB: 4K pages, 64 ents, 4-way */
	128	#define CPUID_CACHE_DTLB_4M_8_4 0x04 /* Data TLB: 4M pages, 8 ents, 4-way */
	129	#define CPUID_CACHE_DTLB_4M_32_4 0x05 /* Data TLB: 4M pages, 32 ents, 4-way */
	130	#define CPUID_CACHE_L1I_8K 0x06 /* Icache: 8K */
	131	#define CPUID_CACHE_L1I_16K 0x08 /* Icache: 16K */
	132	#define CPUID_CACHE_L1I_32K 0x09 /* Icache: 32K, 4-way, 64 bytes */
	133	#define CPUID_CACHE_L1D_8K 0x0A /* Dcache: 8K */
	134	#define CPUID_CACHE_L1D_16K 0x0C /* Dcache: 16K */
	135	#define CPUID_CACHE_L1D_16K_4_32 0x0D /* Dcache: 16K, 4-way, 64 byte, ECC */
	136	#define CPUID_CACHE_L2_256K_8_64 0x21 /* L2: 256K, 8-way, 64 bytes */
0c530ab8 A	137	#define CPUID_CACHE_L3_512K 0x22 /* L3: 512K */
	138	#define CPUID_CACHE_L3_1M 0x23 /* L3: 1M */
	139	#define CPUID_CACHE_L3_2M 0x25 /* L3: 2M */
	140	#define CPUID_CACHE_L3_4M 0x29 /* L3: 4M */
593a1d5f A	141	#define CPUID_CACHE_L1D_32K_8 0x2C /* Dcache: 32K, 8-way, 64 byte */
593a1d5f A	142	#define CPUID_CACHE_L1I_32K_8 0x30 /* Icache: 32K, 8-way */
0c530ab8 A	143	#define CPUID_CACHE_L2_128K_S4 0x39 /* L2: 128K, 4-way, sectored */
	144	#define CPUID_CACHE_L2_128K_S2 0x3B /* L2: 128K, 2-way, sectored */
	145	#define CPUID_CACHE_L2_256K_S4 0x3C /* L2: 256K, 4-way, sectored */
91447636	146	#define CPUID_CACHE_NOCACHE 0x40 /* No 2nd level or 3rd-level cache */
0c530ab8 A	147	#define CPUID_CACHE_L2_128K 0x41 /* L2: 128K */
	148	#define CPUID_CACHE_L2_256K 0x42 /* L2: 256K */
	149	#define CPUID_CACHE_L2_512K 0x43 /* L2: 512K */
	150	#define CPUID_CACHE_L2_1M_4 0x44 /* L2: 1M, 4-way */
	151	#define CPUID_CACHE_L2_2M_4 0x45 /* L2: 2M, 4-way */
	152	#define CPUID_CACHE_L3_4M_4_64 0x46 /* L3: 4M, 4-way, 64 bytes */
	153	#define CPUID_CACHE_L3_8M_8_64 0x47 /* L3: 8M, 8-way, 64 bytes*/
2d21ac55	154	#define CPUID_CACHE_L2_3M_12_64 0x48 /* L3: 3M, 8-way, 64 bytes*/
0c530ab8 A	155	#define CPUID_CACHE_L2_4M_16_64 0x49 /* L2: 4M, 16-way, 64 bytes */
	156	#define CPUID_CACHE_L2_6M_12_64 0x4A /* L2: 6M, 12-way, 64 bytes */
	157	#define CPUID_CACHE_L2_8M_16_64 0x4B /* L2: 8M, 16-way, 64 bytes */
	158	#define CPUID_CACHE_L2_12M_12_64 0x4C /* L2: 12M, 12-way, 64 bytes */
	159	#define CPUID_CACHE_L2_16M_16_64 0x4D /* L2: 16M, 16-way, 64 bytes */
	160	#define CPUID_CACHE_L2_6M_24_64 0x4E /* L2: 6M, 24-way, 64 bytes */
593a1d5f A	161	#define CPUID_CACHE_ITLB_64 0x50 /* Inst TLB: 64 entries */
	162	#define CPUID_CACHE_ITLB_128 0x51 /* Inst TLB: 128 entries */
	163	#define CPUID_CACHE_ITLB_256 0x52 /* Inst TLB: 256 entries */
	164	#define CPUID_CACHE_ITLB_4M2M_7 0x55 /* Inst TLB: 4M/2M, 7 entries */
2d21ac55	165	#define CPUID_CACHE_DTLB_4M_16_4 0x56 /* Data TLB: 4M, 16 entries, 4-way */
593a1d5f A	166	#define CPUID_CACHE_DTLB_4K_16_4 0x57 /* Data TLB: 4K, 16 entries, 4-way */
593a1d5f A	167	#define CPUID_CACHE_DTLB_4M2M_32_4 0x5A /* Data TLB: 4M/2M, 32 entries */
0c530ab8 A	168	#define CPUID_CACHE_DTLB_64 0x5B /* Data TLB: 64 entries */
	169	#define CPUID_CACHE_DTLB_128 0x5C /* Data TLB: 128 entries */
	170	#define CPUID_CACHE_DTLB_256 0x5D /* Data TLB: 256 entries */
593a1d5f A	171	#define CPUID_CACHE_L1D_16K_8_64 0x60 /* Data cache: 16K, 8-way, 64 bytes */
	172	#define CPUID_CACHE_L1D_8K_4_64 0x66 /* Data cache: 8K, 4-way, 64 bytes */
	173	#define CPUID_CACHE_L1D_16K_4_64 0x67 /* Data cache: 16K, 4-way, 64 bytes */
	174	#define CPUID_CACHE_L1D_32K_4_64 0x68 /* Data cache: 32K, 4-way, 64 bytes */
0c530ab8 A	175	#define CPUID_CACHE_TRACE_12K_8 0x70 /* Trace cache 12K-uop, 8-way */
	176	#define CPUID_CACHE_TRACE_16K_8 0x71 /* Trace cache 16K-uop, 8-way */
	177	#define CPUID_CACHE_TRACE_32K_8 0x72 /* Trace cache 32K-uop, 8-way */
	178	#define CPUID_CACHE_L2_1M_4_64 0x78 /* L2: 1M, 4-way, 64 bytes */
	179	#define CPUID_CACHE_L2_128K_8_64_2 0x79 /* L2: 128K, 8-way, 64b, 2 lines/sec */
	180	#define CPUID_CACHE_L2_256K_8_64_2 0x7A /* L2: 256K, 8-way, 64b, 2 lines/sec */
	181	#define CPUID_CACHE_L2_512K_8_64_2 0x7B /* L2: 512K, 8-way, 64b, 2 lines/sec */
	182	#define CPUID_CACHE_L2_1M_8_64_2 0x7C /* L2: 1M, 8-way, 64b, 2 lines/sec */
	183	#define CPUID_CACHE_L2_2M_8_64 0x7D /* L2: 2M, 8-way, 64 bytes */
	184	#define CPUID_CACHE_L2_512K_2_64 0x7F /* L2: 512K, 2-way, 64 bytes */
	185	#define CPUID_CACHE_L2_256K_8_32 0x82 /* L2: 256K, 8-way, 32 bytes */
	186	#define CPUID_CACHE_L2_512K_8_32 0x83 /* L2: 512K, 8-way, 32 bytes */
	187	#define CPUID_CACHE_L2_1M_8_32 0x84 /* L2: 1M, 8-way, 32 bytes */
	188	#define CPUID_CACHE_L2_2M_8_32 0x85 /* L2: 2M, 8-way, 32 bytes */
	189	#define CPUID_CACHE_L2_512K_4_64 0x86 /* L2: 512K, 4-way, 64 bytes */
	190	#define CPUID_CACHE_L2_1M_8_64 0x87 /* L2: 1M, 8-way, 64 bytes */
	191	#define CPUID_CACHE_ITLB_4K_128_4 0xB0 /* ITLB: 4KB, 128 entries, 4-way */
	192	#define CPUID_CACHE_ITLB_4M_4_4 0xB1 /* ITLB: 4MB, 4 entries, 4-way, or */
593a1d5f A	193	#define CPUID_CACHE_ITLB_2M_8_4 0xB1 /* ITLB: 2MB, 8 entries, 4-way, or */
	194	#define CPUID_CACHE_ITLB_4M_8 0xB1 /* ITLB: 4MB, 8 entries */
	195	#define CPUID_CACHE_ITLB_4K_64_4 0xB2 /* ITLB: 4KB, 64 entries, 4-way */
0c530ab8	196	#define CPUID_CACHE_DTLB_4K_128_4 0xB3 /* DTLB: 4KB, 128 entries, 4-way */
2d21ac55	197	#define CPUID_CACHE_DTLB_4K_256_4 0xB4 /* DTLB: 4KB, 256 entries, 4-way */
593a1d5f A	198	#define CPUID_CACHE_2TLB_4K_512_4 0xB4 /* 2nd-level TLB: 4KB, 512, 4-way */
	199	#define CPUID_CACHE_L3_512K_4_64 0xD0 /* L3: 512KB, 4-way, 64 bytes */
	200	#define CPUID_CACHE_L3_1M_4_64 0xD1 /* L3: 1M, 4-way, 64 bytes */
	201	#define CPUID_CACHE_L3_2M_4_64 0xD2 /* L3: 2M, 4-way, 64 bytes */
	202	#define CPUID_CACHE_L3_1M_8_64 0xD6 /* L3: 1M, 8-way, 64 bytes */
	203	#define CPUID_CACHE_L3_2M_8_64 0xD7 /* L3: 2M, 8-way, 64 bytes */
	204	#define CPUID_CACHE_L3_4M_8_64 0xD8 /* L3: 4M, 8-way, 64 bytes */
	205	#define CPUID_CACHE_L3_1M5_12_64 0xDC /* L3: 1.5M, 12-way, 64 bytes */
	206	#define CPUID_CACHE_L3_3M_12_64 0xDD /* L3: 3M, 12-way, 64 bytes */
	207	#define CPUID_CACHE_L3_6M_12_64 0xDE /* L3: 6M, 12-way, 64 bytes */
	208	#define CPUID_CACHE_L3_2M_16_64 0xE2 /* L3: 2M, 16-way, 64 bytes */
	209	#define CPUID_CACHE_L3_4M_16_64 0xE3 /* L3: 4M, 16-way, 64 bytes */
	210	#define CPUID_CACHE_L3_8M_16_64 0xE4 /* L3: 8M, 16-way, 64 bytes */
91447636 A	211	#define CPUID_CACHE_PREFETCH_64 0xF0 /* 64-Byte Prefetching */
91447636 A	212	#define CPUID_CACHE_PREFETCH_128 0xF1 /* 128-Byte Prefetching */
1c79356b	213
2d21ac55 A	214	#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
	215	#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
	216
593a1d5f A	217	#define CPUID_MODEL_YONAH 14
	218	#define CPUID_MODEL_MEROM 15
	219	#define CPUID_MODEL_PENRYN 23
	220	#define CPUID_MODEL_NEHALEM 26
	221
1c79356b	222	#ifndef ASSEMBLER
55e303ae A	223	#include <stdint.h>
	224	#include <mach/mach_types.h>
	225	#include <kern/kern_types.h>
1c79356b A	226	#include <mach/machine.h>
1c79356b A	227
1c79356b	228
0c530ab8 A	229	typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
	230	static inline void
	231	cpuid(uint32_t *data)
	232	{
	233	asm("cpuid"
	234	: "=a" (data[eax]),
	235	"=b" (data[ebx]),
	236	"=c" (data[ecx]),
	237	"=d" (data[edx])
	238	: "a" (data[eax]),
	239	"b" (data[ebx]),
	240	"c" (data[ecx]),
	241	"d" (data[edx]));
	242	}
55e303ae A	243	static inline void
	244	do_cpuid(uint32_t selector, uint32_t *data)
	245	{
	246	asm("cpuid"
	247	: "=a" (data[0]),
	248	"=b" (data[1]),
	249	"=c" (data[2]),
	250	"=d" (data[3])
	251	: "a"(selector));
	252	}
1c79356b A	253
1c79356b A	254	/*
2d21ac55 A	255	* Cache ID descriptor structure, used to parse CPUID leaf 2.
2d21ac55 A	256	* Note: not used in kernel.
1c79356b	257	*/
91447636	258	typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
55e303ae A	259	typedef struct {
	260	unsigned char value; /* Descriptor value */
	261	cache_type_t type; /* Cache type */
	262	unsigned int size; /* Cache size */
	263	unsigned int linesize; /* Cache line size */
	264	#ifdef KERNEL
91447636	265	const char description; / Cache description */
55e303ae A	266	#endif /* KERNEL */
	267	} cpuid_cache_desc_t;
	268
	269	#ifdef KERNEL
	270	#define CACHE_DESC(value,type,size,linesize,text) \
	271	{ value, type, size, linesize, text }
	272	#else
	273	#define CACHE_DESC(value,type,size,linesize,text) \
	274	{ value, type, size, linesize }
	275	#endif /* KERNEL */
	276
0c530ab8	277	/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
55e303ae A	278	typedef struct {
	279	char cpuid_vendor[16];
	280	char cpuid_brand_string[48];
91447636	281	const char *cpuid_model_string;
55e303ae	282
0c530ab8	283	cpu_type_t cpuid_type; /* this is not a cpu_type_t in our <mach/machine.h> */
55e303ae A	284	uint8_t cpuid_family;
	285	uint8_t cpuid_model;
	286	uint8_t cpuid_extmodel;
	287	uint8_t cpuid_extfamily;
	288	uint8_t cpuid_stepping;
0c530ab8 A	289	uint64_t cpuid_features;
0c530ab8 A	290	uint64_t cpuid_extfeatures;
55e303ae A	291	uint32_t cpuid_signature;
	292	uint8_t cpuid_brand;
	293
	294	uint32_t cache_size[LCACHE_MAX];
	295	uint32_t cache_linesize;
	296
55e303ae A	297	uint8_t cache_info[64]; /* list of cache descriptors */
55e303ae A	298
0c530ab8 A	299	uint32_t cpuid_cores_per_package;
	300	uint32_t cpuid_logical_per_package;
	301	uint32_t cache_sharing[LCACHE_MAX];
2d21ac55	302	uint32_t cache_partitions[LCACHE_MAX];
0c530ab8	303
2d21ac55	304	cpu_type_t cpuid_cpu_type; /* <mach/machine.h> */
0c530ab8	305	cpu_subtype_t cpuid_cpu_subtype; /* <mach/machine.h> */
2d21ac55 A	306
	307	/* Monitor/mwait Leaf: */
	308	uint32_t cpuid_mwait_linesize_min;
	309	uint32_t cpuid_mwait_linesize_max;
	310	uint32_t cpuid_mwait_extensions;
	311	uint32_t cpuid_mwait_sub_Cstates;
	312
	313	/* Thermal and Power Management Leaf: */
	314	boolean_t cpuid_thermal_sensor;
	315	boolean_t cpuid_thermal_dynamic_acceleration;
	316	uint32_t cpuid_thermal_thresholds;
	317	boolean_t cpuid_thermal_ACNT_MCNT;
	318
	319	/* Architectural Performance Monitoring Leaf: */
	320	uint8_t cpuid_arch_perf_version;
	321	uint8_t cpuid_arch_perf_number;
	322	uint8_t cpuid_arch_perf_width;
	323	uint8_t cpuid_arch_perf_events_number;
	324	uint32_t cpuid_arch_perf_events;
	325	uint8_t cpuid_arch_perf_fixed_number;
	326	uint8_t cpuid_arch_perf_fixed_width;
	327
	328	/* Cache details: */
	329	uint32_t cpuid_cache_linesize;
	330	uint32_t cpuid_cache_L2_associativity;
	331	uint32_t cpuid_cache_size;
	332
	333	/* Virtual and physical address aize: */
	334	uint32_t cpuid_address_bits_physical;
	335	uint32_t cpuid_address_bits_virtual;
593a1d5f A	336
	337	uint32_t cpuid_microcode_version;
	338
	339	/* Numbers of tlbs per processor */
	340	uint32_t cpuid_itlb_small;
	341	uint32_t cpuid_dtlb_small;
	342	uint32_t cpuid_itlb_large;
	343	uint32_t cpuid_dtlb_large;
	344
	345	uint32_t core_count;
	346	uint32_t thread_count;
	347
55e303ae	348	} i386_cpu_info_t;
1c79356b	349
91447636 A	350	#ifdef __cplusplus
	351	extern "C" {
	352	#endif
1c79356b A	353
	354	/*
	355	* External declarations
	356	*/
0c530ab8 A	357	extern cpu_type_t cpuid_cputype(void);
	358	extern cpu_subtype_t cpuid_cpusubtype(void);
	359	extern void cpuid_cpu_display(const char *);
	360	extern void cpuid_feature_display(const char *);
	361	extern void cpuid_extfeature_display(const char *);
	362	extern char * cpuid_get_feature_names(uint64_t, char *, unsigned);
	363	extern char * cpuid_get_extfeature_names(uint64_t, char *, unsigned);
	364
	365	extern uint64_t cpuid_features(void);
	366	extern uint64_t cpuid_extfeatures(void);
55e303ae	367	extern uint32_t cpuid_family(void);
91447636 A	368
	369	extern void cpuid_get_info(i386_cpu_info_t *info_p);
	370	extern i386_cpu_info_t *cpuid_info(void);
55e303ae	371
0c530ab8	372	extern void cpuid_set_info(void);
1c79356b	373
91447636 A	374	#ifdef __cplusplus
	375	}
	376	#endif
55e303ae	377
1c79356b	378	#endif /* ASSEMBLER */
55e303ae A	379
55e303ae A	380	#endif /* __APPLE_API_PRIVATE */
1c79356b	381	#endif /* _MACHINE_CPUID_H_ */