osfmk/i386/cpuid.c

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31
  32 #include <pexpert/pexpert.h>
  33
  34 #include "cpuid.h"
  35
  36 #define min(a,b) ((a) < (b) ? (a) : (b))
  37
  38 /*
  39  * CPU identification routines.
  40  *
  41  * Note that this code assumes a processor that supports the
  42  * 'cpuid' instruction.
  43  */
  44
  45 static unsigned int     cpuid_maxcpuid;
  46
  47 static i386_cpu_info_t  cpuid_cpu_info;
  48
  49 uint32_t                cpuid_feature;          /* XXX obsolescent for compat */
  50
  51 /*
  52  * We only identify Intel CPUs here.  Adding support
  53  * for others would be straightforward.
  54  */
  55 static void     set_cpu_generic(i386_cpu_info_t *);
  56 static void     set_cpu_intel(i386_cpu_info_t *);
  57 static void     set_cpu_amd(i386_cpu_info_t *);
  58 static void     set_cpu_nsc(i386_cpu_info_t *);
  59 static void     set_cpu_unknown(i386_cpu_info_t *);
  60
  61 struct {
  62         const char      *vendor;
  63         void            (* func)(i386_cpu_info_t *);
  64 } cpu_vendors[] = {
  65         {CPUID_VID_INTEL,       set_cpu_intel},
  66         {CPUID_VID_AMD,         set_cpu_amd},
  67         {CPUID_VID_NSC,         set_cpu_nsc},
  68         {0,                     set_cpu_unknown}
  69 };
  70
  71 void
  72 cpuid_get_info(i386_cpu_info_t *info_p)
  73 {
  74         uint32_t        cpuid_result[4];
  75         int             i;
  76
  77         bzero((void *)info_p, sizeof(i386_cpu_info_t));
  78
  79         /* do cpuid 0 to get vendor */
  80         do_cpuid(0, cpuid_result);
  81         cpuid_maxcpuid = cpuid_result[0];
  82         bcopy((char *)&cpuid_result[1], &info_p->cpuid_vendor[0], 4); /* ugh */
  83         bcopy((char *)&cpuid_result[2], &info_p->cpuid_vendor[8], 4);
  84         bcopy((char *)&cpuid_result[3], &info_p->cpuid_vendor[4], 4);
  85         info_p->cpuid_vendor[12] = 0;
  86
  87         /* look up vendor */
  88         for (i = 0; ; i++) {
  89                 if ((cpu_vendors[i].vendor == 0) ||
  90                     (!strcmp(cpu_vendors[i].vendor, info_p->cpuid_vendor))) {
  91                         cpu_vendors[i].func(info_p);
  92                         break;
  93                 }
  94         }
  95 }
  96
  97 /*
  98  * Cache descriptor table. Each row has the form:
  99  *         (descriptor_value,           cache,  size,           linesize,
 100  *                              description)
 101  * Note: the CACHE_DESC macro does not expand description text in the kernel.
 102  */
 103 static cpuid_cache_desc_t cpuid_cache_desc_tab[] = {
 104 CACHE_DESC(CPUID_CACHE_ITLB_4K,         Lnone,  0,              0, \
 105         "Instruction TLB, 4K, pages 4-way set associative, 64 entries"),
 106 CACHE_DESC(CPUID_CACHE_ITLB_4M,         Lnone,  0,              0, \
 107         "Instruction TLB, 4M, pages 4-way set associative, 2 entries"),
 108 CACHE_DESC(CPUID_CACHE_DTLB_4K,         Lnone,  0,              0, \
 109         "Data TLB, 4K pages, 4-way set associative, 64 entries"),
 110 CACHE_DESC(CPUID_CACHE_DTLB_4M,         Lnone,  0,              0, \
 111         "Data TLB, 4M pages, 4-way set associative, 8 entries"),
 112 CACHE_DESC(CPUID_CACHE_ITLB_64,         Lnone,  0,              0, \
 113         "Instruction TLB, 4K and 2M or 4M pages, 64 entries"),
 114 CACHE_DESC(CPUID_CACHE_ITLB_128,        Lnone,  0,              0, \
 115         "Instruction TLB, 4K and 2M or 4M pages, 128 entries"),
 116 CACHE_DESC(CPUID_CACHE_ITLB_256,        Lnone,  0,              0, \
 117         "Instruction TLB, 4K and 2M or 4M pages, 256 entries"),
 118 CACHE_DESC(CPUID_CACHE_DTLB_64,         Lnone,  0,              0, \
 119         "Data TLB, 4K and 4M pages, 64 entries"),
 120 CACHE_DESC(CPUID_CACHE_DTLB_128,        Lnone,  0,              0, \
 121         "Data TLB, 4K and 4M pages, 128 entries"),
 122 CACHE_DESC(CPUID_CACHE_DTLB_256,        Lnone,  0,              0, \
 123         "Data TLB, 4K and 4M pages, 256 entries"),
 124 CACHE_DESC(CPUID_CACHE_ITLB_128_4,      Lnone,  0,              0, \
 125         "Instruction TLB, 4K pages, 4-way set associative, 128 entries"),
 126 CACHE_DESC(CPUID_CACHE_DTLB_128_4,      Lnone,  0,              0, \
 127         "Data TLB, 4K pages, 4-way set associative, 128 entries"),
 128 CACHE_DESC(CPUID_CACHE_ICACHE_8K,       L1I,    8*1024,         32, \
 129         "Instruction L1 cache, 8K, 4-way set associative, 32byte line size"),
 130 CACHE_DESC(CPUID_CACHE_DCACHE_8K,       L1D,    8*1024,         32, \
 131         "Data L1 cache, 8K, 2-way set associative, 32byte line size"),
 132 CACHE_DESC(CPUID_CACHE_ICACHE_16K,      L1I,    16*1024,         32, \
 133         "Instruction L1 cache, 16K, 4-way set associative, 32byte line size"),
 134 CACHE_DESC(CPUID_CACHE_DCACHE_16K,      L1D,    16*1024,        32, \
 135         "Data L1 cache, 16K, 4-way set associative, 32byte line size"),
 136 CACHE_DESC(CPUID_CACHE_DCACHE_8K_64,    L1D,    8*1024,         64, \
 137         "Data L1 cache, 8K, 4-way set associative, 64byte line size"),
 138 CACHE_DESC(CPUID_CACHE_DCACHE_16K_64,   L1D,    16*1024,        64, \
 139         "Data L1 cache, 16K, 4-way set associative, 64byte line size"),
 140 CACHE_DESC(CPUID_CACHE_DCACHE_32K_64,   L1D,    32*1024,        64, \
 141         "Data L1 cache, 32K, 4-way set associative, 64byte line size"),
 142 CACHE_DESC(CPUID_CACHE_DCACHE_32K,      L1D,    32*1024,        64, \
 143         "Data L1 cache, 32K, 8-way set assocative, 64byte line size"),
 144 CACHE_DESC(CPUID_CACHE_ICACHE_32K,      L1I,    32*1024,        64, \
 145         "Instruction L1 cache, 32K, 8-way set associative, 64byte line size"),
 146 CACHE_DESC(CPUID_CACHE_DCACHE_16K_8,    L1D,    16*1024,        64, \
 147         "Data L1 cache, 16K, 8-way set associative, 64byte line size"),
 148 CACHE_DESC(CPUID_CACHE_TRACE_12K,       L1I,    12*1024,        64, \
 149         "Trace cache, 12K-uop, 8-way set associative"),
 150 CACHE_DESC(CPUID_CACHE_TRACE_16K,       L1I,    16*1024,        64, \
 151         "Trace cache, 16K-uop, 8-way set associative"),
 152 CACHE_DESC(CPUID_CACHE_TRACE_32K,       L1I,    32*1024,        64, \
 153         "Trace cache, 32K-uop, 8-way set associative"),
 154 CACHE_DESC(CPUID_CACHE_UCACHE_128K,     L2U,    128*1024,       32, \
 155         "Unified L2 cache, 128K, 4-way set associative, 32byte line size"),
 156 CACHE_DESC(CPUID_CACHE_UCACHE_256K,     L2U,    128*1024,       32, \
 157         "Unified L2 cache, 256K, 4-way set associative, 32byte line size"),
 158 CACHE_DESC(CPUID_CACHE_UCACHE_512K,     L2U,    512*1024,       32, \
 159         "Unified L2 cache, 512K, 4-way set associative, 32byte line size"),
 160 CACHE_DESC(CPUID_CACHE_UCACHE_1M,       L2U,    1*1024*1024,    32, \
 161         "Unified L2 cache, 1M, 4-way set associative, 32byte line size"),
 162 CACHE_DESC(CPUID_CACHE_UCACHE_2M,       L2U,    2*1024*1024,    32, \
 163         "Unified L2 cache, 2M, 4-way set associative, 32byte line size"),
 164 CACHE_DESC(CPUID_CACHE_UCACHE_128K_64,  L2U,    128*1024,       64, \
 165         "Unified L2 cache, 128K, 8-way set associative, 64byte line size"),
 166 CACHE_DESC(CPUID_CACHE_UCACHE_256K_64,  L2U,    256*1024,       64, \
 167         "Unified L2 cache, 256K, 8-way set associative, 64byte line size"),
 168 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64,  L2U,    512*1024,       64, \
 169         "Unified L2 cache, 512K, 8-way set associative, 64byte line size"),
 170 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64,    L2U,    1*1024*1024,    64, \
 171         "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
 172 CACHE_DESC(CPUID_CACHE_UCACHE_256K_32,  L2U,    256*1024,       32, \
 173         "Unified L2 cache, 256K, 8-way set associative, 32byte line size"),
 174 CACHE_DESC(CPUID_CACHE_UCACHE_512K_32,  L2U,    512*1024,       32, \
 175         "Unified L2 cache, 512K, 8-way set associative, 32byte line size"),
 176 CACHE_DESC(CPUID_CACHE_UCACHE_1M_32,    L2U,    1*1024*1024,    32, \
 177         "Unified L2 cache, 1M, 8-way set associative, 32byte line size"),
 178 CACHE_DESC(CPUID_CACHE_UCACHE_2M_32,    L2U,    2*1024*1024,    32, \
 179         "Unified L2 cache, 2M, 8-way set associative, 32byte line size"),
 180 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_4,  L2U,    1*1024*1024,    64, \
 181         "Unified L2 cache, 1M, 4-way set associative, 64byte line size"),
 182 CACHE_DESC(CPUID_CACHE_UCACHE_2M_64,    L2U,    2*1024*1024,    64, \
 183         "Unified L2 cache, 2M, 8-way set associative, 64byte line size"),
 184 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_2,L2U,    512*1024,       64, \
 185         "Unified L2 cache, 512K, 2-way set associative, 64byte line size"),
 186 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_4,L2U,    512*1024,       64, \
 187         "Unified L2 cache, 512K, 4-way set associative, 64byte line size"),
 188 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_8,  L2U,    1*1024*1024,    64, \
 189         "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
 190 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S4,  L2U,    128*1024,       64, \
 191         "Unified L2 sectored cache, 128K, 4-way set associative, 64byte line size"),
 192 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S2,  L2U,    128*1024,       64, \
 193         "Unified L2 sectored cache, 128K, 2-way set associative, 64byte line size"),
 194 CACHE_DESC(CPUID_CACHE_UCACHE_256K_S4,  L2U,    256*1024,       64, \
 195         "Unified L2 sectored cache, 256K, 4-way set associative, 64byte line size"),
 196 CACHE_DESC(CPUID_CACHE_L3CACHE_512K,    L3U,    512*1024,       64, \
 197         "Unified L3 cache, 512K, 4-way set associative, 64byte line size"),
 198 CACHE_DESC(CPUID_CACHE_L3CACHE_1M,      L3U,    1*1024*1024,    64, \
 199         "Unified L3 cache, 1M, 8-way set associative, 64byte line size"),
 200 CACHE_DESC(CPUID_CACHE_L3CACHE_2M,      L3U,    2*1024*1024,    64, \
 201         "Unified L3 cache, 2M, 8-way set associative, 64byte line size"),
 202 CACHE_DESC(CPUID_CACHE_L3CACHE_4M,      L3U,    4*1024*1024,    64, \
 203         "Unified L3 cache, 4M, 8-way set associative, 64byte line size"),
 204 CACHE_DESC(CPUID_CACHE_PREFETCH_64,     Lnone,  0,              0,  \
 205         "64-Byte Prefetching"),
 206 CACHE_DESC(CPUID_CACHE_PREFETCH_128,    Lnone,  0,              0,  \
 207         "128-Byte Prefetching"),
 208 CACHE_DESC(CPUID_CACHE_NOCACHE, Lnone, 0, 0, \
 209         "No L2 cache or, if valid L2 cache, no L3 cache"),
 210 CACHE_DESC(CPUID_CACHE_NULL, Lnone, 0, 0, \
 211         (char *)0),
 212 };
 213
 214 static const char * get_intel_model_string( i386_cpu_info_t * info_p )
 215 {
 216     /* check for brand id */
 217     switch(info_p->cpuid_brand) {
 218         case CPUID_BRAND_UNSUPPORTED:
 219             /* brand ID not supported; use alternate method. */
 220             switch(info_p->cpuid_family) {
 221                 case CPUID_FAMILY_486:
 222                     return "Intel 486";
 223                 case CPUID_FAMILY_586:
 224                     return "Intel Pentium";
 225                 case CPUID_FAMILY_686:
 226                     switch(info_p->cpuid_model) {
 227                         case CPUID_MODEL_P6:
 228                             return "Intel Pentium Pro";
 229                         case CPUID_MODEL_PII:
 230                             return "Intel Pentium II";
 231                         case CPUID_MODEL_P65:
 232                         case CPUID_MODEL_P66:
 233                             return "Intel Celeron";
 234                         case CPUID_MODEL_P67:
 235                         case CPUID_MODEL_P68:
 236                         case CPUID_MODEL_P6A:
 237                         case CPUID_MODEL_P6B:
 238                             return "Intel Pentium III";
 239                         case CPUID_MODEL_PM9:
 240                         case CPUID_MODEL_PMD:
 241                             return "Intel Pentium M";
 242                         default:
 243                             return "Unknown Intel P6 Family";
 244                     }
 245                 case CPUID_FAMILY_ITANIUM:
 246                     return "Intel Itanium";
 247                 case CPUID_FAMILY_EXTENDED:
 248                     switch (info_p->cpuid_extfamily) {
 249                         case CPUID_EXTFAMILY_PENTIUM4:
 250                             return "Intel Pentium 4";
 251                         case CPUID_EXTFAMILY_ITANIUM2:
 252                             return "Intel Itanium 2";
 253                     }
 254                 default:
 255                     return "Unknown Intel Family";
 256             }
 257             break;
 258         case CPUID_BRAND_CELERON_1:
 259         case CPUID_BRAND_CELERON_A:
 260         case CPUID_BRAND_CELERON_14:
 261             return "Intel Celeron";
 262         case CPUID_BRAND_PENTIUM_III_2:
 263         case CPUID_BRAND_PENTIUM_III_4:
 264             return "Pentium III";
 265         case CPUID_BRAND_PIII_XEON:
 266             if (info_p->cpuid_signature == 0x6B1)
 267                 return "Intel Celeron";
 268             else
 269                 return "Intel Pentium III Xeon";
 270         case CPUID_BRAND_PENTIUM_III_M:
 271             return "Mobile Intel Pentium III-M";
 272         case CPUID_BRAND_M_CELERON_7:
 273         case CPUID_BRAND_M_CELERON_F:
 274         case CPUID_BRAND_M_CELERON_13:
 275         case CPUID_BRAND_M_CELERON_17:
 276             return "Mobile Intel Celeron";
 277         case CPUID_BRAND_PENTIUM4_8:
 278         case CPUID_BRAND_PENTIUM4_9:
 279             return "Intel Pentium 4";
 280         case CPUID_BRAND_XEON:
 281             return "Intel Xeon";
 282         case CPUID_BRAND_XEON_MP:
 283             return "Intel Xeon MP";
 284         case CPUID_BRAND_PENTIUM4_M:
 285             if (info_p->cpuid_signature == 0xF13)
 286                 return "Intel Xeon";
 287             else
 288                 return "Mobile Intel Pentium 4";
 289         case CPUID_BRAND_CELERON_M:
 290             return "Intel Celeron M";
 291         case CPUID_BRAND_PENTIUM_M:
 292             return "Intel Pentium M";
 293         case CPUID_BRAND_MOBILE_15:
 294         case CPUID_BRAND_MOBILE_17:
 295             return "Mobile Intel";
 296     }
 297
 298     return "Unknown Intel";
 299 }
 300
 301 static void set_intel_cache_info( i386_cpu_info_t * info_p )
 302 {
 303         uint32_t        cpuid_result[4];
 304         uint32_t        l1d_cache_linesize = 0;
 305         unsigned int    i;
 306         unsigned int    j;
 307
 308         /* get processor cache descriptor info */
 309         do_cpuid(2, cpuid_result);
 310         for (j = 0; j < 4; j++) {
 311                 if ((cpuid_result[j] >> 31) == 1)       /* bit31 is validity */
 312                         continue;
 313                 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j];
 314         }
 315         /* first byte gives number of cpuid calls to get all descriptors */
 316         for (i = 1; i < info_p->cache_info[0]; i++) {
 317                 if (i*16 > sizeof(info_p->cache_info))
 318                         break;
 319                 do_cpuid(2, cpuid_result);
 320                 for (j = 0; j < 4; j++) {
 321                         if ((cpuid_result[j] >> 31) == 1)
 322                                 continue;
 323                         ((uint32_t *) info_p->cache_info)[4*i+j] =
 324                                 cpuid_result[j];
 325                 }
 326         }
 327
 328         /* decode the descriptors looking for L1/L2/L3 size info */
 329         for (i = 1; i < sizeof(info_p->cache_info); i++) {
 330                 cpuid_cache_desc_t      *descp;
 331                 uint8_t                 desc = info_p->cache_info[i];
 332
 333                 if (desc == CPUID_CACHE_NULL)
 334                         continue;
 335                 for (descp = cpuid_cache_desc_tab;
 336                         descp->value != CPUID_CACHE_NULL; descp++) {
 337                         if (descp->value != desc)
 338                                 continue;
 339                         info_p->cache_size[descp->type] = descp->size;
 340                         if (descp->type == L2U)
 341                                 info_p->cache_linesize = descp->linesize;
 342                         if (descp->type == L1D)
 343                                 l1d_cache_linesize = descp->linesize;
 344                         break;
 345                 }
 346         }
 347         /* For P-IIIs, L2 could be 256k or 512k but we can't tell */
 348         if (info_p->cache_size[L2U] == 0 &&
 349             info_p->cpuid_family == 0x6 && info_p->cpuid_model == 0xb) {
 350                 info_p->cache_size[L2U] = 256*1024;
 351                 info_p->cache_linesize = 32;
 352         }
 353         /* If we have no L2 cache, use the L1 data cache line size */
 354         if (info_p->cache_size[L2U] == 0)
 355             info_p->cache_linesize = l1d_cache_linesize;
 356 }
 357
 358 static void set_cpu_intel( i386_cpu_info_t * info_p )
 359 {
 360     set_cpu_generic(info_p);
 361     set_intel_cache_info(info_p);
 362     info_p->cpuid_model_string = get_intel_model_string(info_p);
 363 }
 364
 365 static const char * get_amd_model_string( i386_cpu_info_t * info_p )
 366 {
 367     switch (info_p->cpuid_family)
 368     {
 369         case CPUID_FAMILY_486:
 370             switch (info_p->cpuid_model) {
 371                 case CPUID_MODEL_AM486_DX:
 372                 case CPUID_MODEL_AM486_DX2:
 373                 case CPUID_MODEL_AM486_DX2WB:
 374                 case CPUID_MODEL_AM486_DX4:
 375                 case CPUID_MODEL_AM486_DX4WB:
 376                     return "Am486";
 377                 case CPUID_MODEL_AM486_5X86:
 378                 case CPUID_MODEL_AM486_5X86WB:
 379                     return "Am5x86";
 380             }
 381             break;
 382         case CPUID_FAMILY_586:
 383             switch (info_p->cpuid_model) {
 384                 case CPUID_MODEL_K5M0:
 385                 case CPUID_MODEL_K5M1:
 386                 case CPUID_MODEL_K5M2:
 387                 case CPUID_MODEL_K5M3:
 388                     return "AMD-K5";
 389                 case CPUID_MODEL_K6M6:
 390                 case CPUID_MODEL_K6M7:
 391                     return "AMD-K6";
 392                 case CPUID_MODEL_K6_2:
 393                     return "AMD-K6-2";
 394                 case CPUID_MODEL_K6_III:
 395                     return "AMD-K6-III";
 396             }
 397             break;
 398         case CPUID_FAMILY_686:
 399             switch (info_p->cpuid_model) {
 400                 case CPUID_MODEL_ATHLON_M1:
 401                 case CPUID_MODEL_ATHLON_M2:
 402                 case CPUID_MODEL_ATHLON_M4:
 403                 case CPUID_MODEL_ATHLON_M6:
 404                 case CPUID_MODEL_ATHLON_M8:
 405                 case CPUID_MODEL_ATHLON_M10:
 406                     return "AMD Athlon";
 407                 case CPUID_MODEL_DURON_M3:
 408                 case CPUID_MODEL_DURON_M7:
 409                     return "AMD Duron";
 410                 default:
 411                     return "Unknown AMD Athlon";
 412             }
 413         case CPUID_FAMILY_EXTENDED:
 414             switch (info_p->cpuid_model) {
 415                 case CPUID_MODEL_ATHLON64:
 416                     return "AMD Athlon 64";
 417                 case CPUID_MODEL_OPTERON:
 418                     return "AMD Opteron";
 419                 default:
 420                     return "Unknown AMD-64";
 421             }
 422     }
 423     return "Unknown AMD";
 424 }
 425
 426 static void set_amd_cache_info( i386_cpu_info_t * info_p )
 427 {
 428     uint32_t    cpuid_result[4];
 429
 430     /* It would make sense to fill in info_p->cache_info with complete information
 431      * on the TLBs and data cache associativity, lines, etc, either by mapping
 432      * to the Intel tags (if possible), or replacing cache_info with a generic
 433      * mechanism.  But right now, nothing makes use of that information (that I know
 434      * of).
 435      */
 436
 437     /* L1 Cache and TLB Information */
 438     do_cpuid(0x80000005, cpuid_result);
 439
 440     /* EAX: TLB Information for 2-Mbyte and 4-MByte Pages */
 441     /* (ignore) */
 442
 443     /* EBX: TLB Information for 4-Kbyte Pages */
 444     /* (ignore) */
 445
 446     /* ECX: L1 Data Cache Information */
 447     info_p->cache_size[L1D] = ((cpuid_result[2] >> 24) & 0xFF) * 1024;
 448     info_p->cache_linesize = (cpuid_result[2] & 0xFF);
 449
 450     /* EDX: L1 Instruction Cache Information */
 451     info_p->cache_size[L1I] = ((cpuid_result[3] >> 24) & 0xFF) * 1024;
 452
 453     /* L2 Cache Information */
 454     do_cpuid(0x80000006, cpuid_result);
 455
 456     /* EAX: L2 TLB Information for 2-Mbyte and 4-Mbyte Pages */
 457     /* (ignore) */
 458
 459     /* EBX: L2 TLB Information for 4-Kbyte Pages */
 460     /* (ignore) */
 461
 462     /* ECX: L2 Cache Information */
 463     info_p->cache_size[L2U] = ((cpuid_result[2] >> 16) & 0xFFFF) * 1024;
 464     if (info_p->cache_size[L2U] > 0)
 465         info_p->cache_linesize = cpuid_result[2] & 0xFF;
 466 }
 467
 468 static void set_cpu_amd( i386_cpu_info_t * info_p )
 469 {
 470     set_cpu_generic(info_p);
 471     set_amd_cache_info(info_p);
 472     info_p->cpuid_model_string = get_amd_model_string(info_p);
 473 }
 474
 475 static void set_cpu_nsc( i386_cpu_info_t * info_p )
 476 {
 477     set_cpu_generic(info_p);
 478     set_amd_cache_info(info_p);
 479
 480     if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX1)
 481         info_p->cpuid_model_string = "AMD Geode GX1";
 482     else if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX2)
 483         info_p->cpuid_model_string = "AMD Geode GX";
 484     else
 485         info_p->cpuid_model_string = "Unknown National Semiconductor";
 486 }
 487
 488 static void
 489 set_cpu_generic(i386_cpu_info_t *info_p)
 490 {
 491         uint32_t        cpuid_result[4];
 492         uint32_t        max_extid;
 493         char            str[128], *p;
 494
 495         /* get extended cpuid results */
 496         do_cpuid(0x80000000, cpuid_result);
 497         max_extid = cpuid_result[0];
 498
 499         /* check to see if we can get brand string */
 500         if (max_extid >= 0x80000004) {
 501                 /*
 502                  * The brand string 48 bytes (max), guaranteed to
 503                  * be NUL terminated.
 504                  */
 505                 do_cpuid(0x80000002, cpuid_result);
 506                 bcopy((char *)cpuid_result, &str[0], 16);
 507                 do_cpuid(0x80000003, cpuid_result);
 508                 bcopy((char *)cpuid_result, &str[16], 16);
 509                 do_cpuid(0x80000004, cpuid_result);
 510                 bcopy((char *)cpuid_result, &str[32], 16);
 511                 for (p = str; *p != '\0'; p++) {
 512                         if (*p != ' ') break;
 513                 }
 514                 strncpy(info_p->cpuid_brand_string,
 515                         p, sizeof(info_p->cpuid_brand_string)-1);
 516                 info_p->cpuid_brand_string[sizeof(info_p->cpuid_brand_string)-1] = '\0';
 517
 518                 if (!strcmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN)) {
 519                     /*
 520                      * This string means we have a BIOS-programmable brand string,
 521                      * and the BIOS couldn't figure out what sort of CPU we have.
 522                      */
 523                     info_p->cpuid_brand_string[0] = '\0';
 524                 }
 525         }
 526
 527         /* get processor signature and decode */
 528         do_cpuid(1, cpuid_result);
 529         info_p->cpuid_signature =  cpuid_result[0];
 530         info_p->cpuid_stepping  =  cpuid_result[0]        & 0x0f;
 531         info_p->cpuid_model     = (cpuid_result[0] >> 4)  & 0x0f;
 532         info_p->cpuid_family    = (cpuid_result[0] >> 8)  & 0x0f;
 533         info_p->cpuid_type      = (cpuid_result[0] >> 12) & 0x03;
 534         info_p->cpuid_extmodel  = (cpuid_result[0] >> 16) & 0x0f;
 535         info_p->cpuid_extfamily = (cpuid_result[0] >> 20) & 0xff;
 536         info_p->cpuid_brand     =  cpuid_result[1]        & 0xff;
 537         info_p->cpuid_features  =  cpuid_result[3];
 538
 539         return;
 540 }
 541
 542 static void
 543 set_cpu_unknown(__unused i386_cpu_info_t *info_p)
 544 {
 545     info_p->cpuid_model_string = "Unknown";
 546 }
 547
 548
 549 static struct {
 550         uint32_t        mask;
 551         const char      *name;
 552 } feature_names[] = {
 553         {CPUID_FEATURE_FPU,   "FPU",},
 554         {CPUID_FEATURE_VME,   "VME",},
 555         {CPUID_FEATURE_DE,    "DE",},
 556         {CPUID_FEATURE_PSE,   "PSE",},
 557         {CPUID_FEATURE_TSC,   "TSC",},
 558         {CPUID_FEATURE_MSR,   "MSR",},
 559         {CPUID_FEATURE_PAE,   "PAE",},
 560         {CPUID_FEATURE_MCE,   "MCE",},
 561         {CPUID_FEATURE_CX8,   "CX8",},
 562         {CPUID_FEATURE_APIC,  "APIC",},
 563         {CPUID_FEATURE_SEP,   "SEP",},
 564         {CPUID_FEATURE_MTRR,  "MTRR",},
 565         {CPUID_FEATURE_PGE,   "PGE",},
 566         {CPUID_FEATURE_MCA,   "MCA",},
 567         {CPUID_FEATURE_CMOV,  "CMOV",},
 568         {CPUID_FEATURE_PAT,   "PAT",},
 569         {CPUID_FEATURE_PSE36, "PSE36",},
 570         {CPUID_FEATURE_PSN,   "PSN",},
 571         {CPUID_FEATURE_CLFSH, "CLFSH",},
 572         {CPUID_FEATURE_DS,    "DS",},
 573         {CPUID_FEATURE_ACPI,  "ACPI",},
 574         {CPUID_FEATURE_MMX,   "MMX",},
 575         {CPUID_FEATURE_FXSR,  "FXSR",},
 576         {CPUID_FEATURE_SSE,   "SSE",},
 577         {CPUID_FEATURE_SSE2,  "SSE2",},
 578         {CPUID_FEATURE_SS,    "SS",},
 579         {CPUID_FEATURE_HTT,   "HTT",},
 580         {CPUID_FEATURE_TM,    "TM",},
 581         {0, 0}
 582 };
 583
 584 char *
 585 cpuid_get_feature_names(uint32_t feature, char *buf, unsigned buf_len)
 586 {
 587         int     i;
 588         int     len;
 589         char    *p = buf;
 590
 591         for (i = 0; feature_names[i].mask != 0; i++) {
 592                 if ((feature & feature_names[i].mask) == 0)
 593                         continue;
 594                 if (i > 0)
 595                         *p++ = ' ';
 596                 len = min(strlen(feature_names[i].name), (buf_len-1) - (p-buf));
 597                 if (len == 0)
 598                         break;
 599                 bcopy(feature_names[i].name, p, len);
 600                 p += len;
 601         }
 602         *p = '\0';
 603         return buf;
 604 }
 605
 606 void
 607 cpuid_feature_display(
 608         const char      *header,
 609         __unused int    my_cpu)
 610 {
 611         char    buf[256];
 612
 613         printf("%s: %s\n", header,
 614                   cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf)));
 615 }
 616
 617 void
 618 cpuid_cpu_display(
 619         const char      *header,
 620         __unused int    my_cpu)
 621 {
 622     if (cpuid_cpu_info.cpuid_brand_string[0] != '\0') {
 623         printf("%s: %s\n", header,
 624                cpuid_cpu_info.cpuid_brand_string);
 625     }
 626 }
 627
 628 unsigned int
 629 cpuid_family(void)
 630 {
 631         return cpuid_cpu_info.cpuid_family;
 632 }
 633
 634 unsigned int
 635 cpuid_features(void)
 636 {
 637         static int checked = 0;
 638         char    fpu_arg[16] = { 0 };
 639         if (!checked) {
 640                     /* check for boot-time fpu limitations */
 641                         if (PE_parse_boot_arg("_fpu", &fpu_arg[0])) {
 642                                 printf("limiting fpu features to: %s\n", fpu_arg);
 643                                 if (!strncmp("387", fpu_arg, sizeof "387") || !strncmp("mmx", fpu_arg, sizeof "mmx")) {
 644                                         printf("no sse or sse2\n");
 645                                         cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
 646                                 } else if (!strncmp("sse", fpu_arg, sizeof "sse")) {
 647                                         printf("no sse2\n");
 648                                         cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2);
 649                                 }
 650                         }
 651                         checked = 1;
 652         }
 653         return cpuid_cpu_info.cpuid_features;
 654 }
 655
 656 i386_cpu_info_t *
 657 cpuid_info(void)
 658 {
 659         return &cpuid_cpu_info;
 660 }
 661
 662 /* XXX for temporary compatibility */
 663 void
 664 set_cpu_model(void)
 665 {
 666         cpuid_get_info(&cpuid_cpu_info);
 667         cpuid_feature = cpuid_cpu_info.cpuid_features;  /* XXX compat */
 668 }
 669