osfmk/i386/cpuid.c

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31 #include <platforms.h>
  32 #include <mach_kdb.h>
  33 #include <pexpert/pexpert.h>
  34
  35 #include "cpuid.h"
  36 #if MACH_KDB
  37 #include <i386/db_machdep.h>
  38 #include <ddb/db_aout.h>
  39 #include <ddb/db_access.h>
  40 #include <ddb/db_sym.h>
  41 #include <ddb/db_variables.h>
  42 #include <ddb/db_command.h>
  43 #include <ddb/db_output.h>
  44 #include <ddb/db_expr.h>
  45 #endif
  46
  47 #define min(a,b) ((a) < (b) ? (a) : (b))
  48 #define quad(hi,lo)     (((uint64_t)(hi)) << 32 | (lo))
  49
  50 #define bit(n)          (1UL << (n))
  51 #define bitmask(h,l)    ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
  52 #define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l)
  53
  54 /*
  55  * CPU identification routines.
  56  *
  57  * Note that this code assumes a processor that supports the
  58  * 'cpuid' instruction.
  59  */
  60
  61 static unsigned int     cpuid_maxcpuid;
  62
  63 static i386_cpu_info_t  *cpuid_cpu_infop = NULL;
  64 static i386_cpu_info_t  cpuid_cpu_info;
  65
  66 uint32_t                cpuid_feature;          /* XXX obsolescent for compat */
  67
  68 /*
  69  * We only identify Intel CPUs here.  Adding support
  70  * for others would be straightforward.
  71  */
  72 static void     set_cpu_generic(i386_cpu_info_t *);
  73 static void     set_cpu_intel(i386_cpu_info_t *);
  74 static void     set_cpu_amd(i386_cpu_info_t *);
  75 static void     set_cpu_nsc(i386_cpu_info_t *);
  76 static void     set_cpu_unknown(i386_cpu_info_t *);
  77
  78 struct {
  79         const char      *vendor;
  80         void            (* func)(i386_cpu_info_t *);
  81 } cpu_vendors[] = {
  82         {CPUID_VID_INTEL,       set_cpu_intel},
  83         {CPUID_VID_AMD,         set_cpu_amd},
  84         {CPUID_VID_NSC,         set_cpu_nsc},
  85         {0,                     set_cpu_unknown}
  86 };
  87
  88 void
  89 cpuid_get_info(i386_cpu_info_t *info_p)
  90 {
  91         uint32_t        cpuid_result[4];
  92         int             i;
  93
  94         bzero((void *)info_p, sizeof(i386_cpu_info_t));
  95
  96         /* do cpuid 0 to get vendor */
  97         do_cpuid(0, cpuid_result);
  98         cpuid_maxcpuid = cpuid_result[eax];
  99         bcopy((char *)&cpuid_result[ebx], &info_p->cpuid_vendor[0], 4); /* ug */
 100         bcopy((char *)&cpuid_result[ecx], &info_p->cpuid_vendor[8], 4);
 101         bcopy((char *)&cpuid_result[edx], &info_p->cpuid_vendor[4], 4);
 102         info_p->cpuid_vendor[12] = 0;
 103
 104         /* look up vendor */
 105         for (i = 0; ; i++) {
 106                 if ((cpu_vendors[i].vendor == 0) ||
 107                     (!strcmp(cpu_vendors[i].vendor, info_p->cpuid_vendor))) {
 108                         cpu_vendors[i].func(info_p);
 109                         break;
 110                 }
 111         }
 112 }
 113
 114 /*
 115  * Cache descriptor table. Each row has the form:
 116  *         (descriptor_value,           cache,  size,           linesize,
 117  *                              description)
 118  * Note: the CACHE_DESC macro does not expand description text in the kernel.
 119  */
 120 static cpuid_cache_desc_t cpuid_cache_desc_tab[] = {
 121 CACHE_DESC(CPUID_CACHE_ITLB_4K,         Lnone,  0,              0, \
 122         "Instruction TLB, 4K, pages 4-way set associative, 64 entries"),
 123 CACHE_DESC(CPUID_CACHE_ITLB_4M,         Lnone,  0,              0, \
 124         "Instruction TLB, 4M, pages 4-way set associative, 2 entries"),
 125 CACHE_DESC(CPUID_CACHE_DTLB_4K,         Lnone,  0,              0, \
 126         "Data TLB, 4K pages, 4-way set associative, 64 entries"),
 127 CACHE_DESC(CPUID_CACHE_DTLB_4M,         Lnone,  0,              0, \
 128         "Data TLB, 4M pages, 4-way set associative, 8 entries"),
 129 CACHE_DESC(CPUID_CACHE_ITLB_64,         Lnone,  0,              0, \
 130         "Instruction TLB, 4K and 2M or 4M pages, 64 entries"),
 131 CACHE_DESC(CPUID_CACHE_ITLB_128,        Lnone,  0,              0, \
 132         "Instruction TLB, 4K and 2M or 4M pages, 128 entries"),
 133 CACHE_DESC(CPUID_CACHE_ITLB_256,        Lnone,  0,              0, \
 134         "Instruction TLB, 4K and 2M or 4M pages, 256 entries"),
 135 CACHE_DESC(CPUID_CACHE_DTLB_64,         Lnone,  0,              0, \
 136         "Data TLB, 4K and 4M pages, 64 entries"),
 137 CACHE_DESC(CPUID_CACHE_DTLB_128,        Lnone,  0,              0, \
 138         "Data TLB, 4K and 4M pages, 128 entries"),
 139 CACHE_DESC(CPUID_CACHE_DTLB_256,        Lnone,  0,              0, \
 140         "Data TLB, 4K and 4M pages, 256 entries"),
 141 CACHE_DESC(CPUID_CACHE_ITLB_128_4,      Lnone,  0,              0, \
 142         "Instruction TLB, 4K pages, 4-way set associative, 128 entries"),
 143 CACHE_DESC(CPUID_CACHE_DTLB_128_4,      Lnone,  0,              0, \
 144         "Data TLB, 4K pages, 4-way set associative, 128 entries"),
 145 CACHE_DESC(CPUID_CACHE_ICACHE_8K,       L1I,    8*1024,         32, \
 146         "Instruction L1 cache, 8K, 4-way set associative, 32byte line size"),
 147 CACHE_DESC(CPUID_CACHE_DCACHE_8K,       L1D,    8*1024,         32, \
 148         "Data L1 cache, 8K, 2-way set associative, 32byte line size"),
 149 CACHE_DESC(CPUID_CACHE_ICACHE_16K,      L1I,    16*1024,         32, \
 150         "Instruction L1 cache, 16K, 4-way set associative, 32byte line size"),
 151 CACHE_DESC(CPUID_CACHE_DCACHE_16K,      L1D,    16*1024,        32, \
 152         "Data L1 cache, 16K, 4-way set associative, 32byte line size"),
 153 CACHE_DESC(CPUID_CACHE_DCACHE_8K_64,    L1D,    8*1024,         64, \
 154         "Data L1 cache, 8K, 4-way set associative, 64byte line size"),
 155 CACHE_DESC(CPUID_CACHE_DCACHE_16K_64,   L1D,    16*1024,        64, \
 156         "Data L1 cache, 16K, 4-way set associative, 64byte line size"),
 157 CACHE_DESC(CPUID_CACHE_DCACHE_32K_64,   L1D,    32*1024,        64, \
 158         "Data L1 cache, 32K, 4-way set associative, 64byte line size"),
 159 CACHE_DESC(CPUID_CACHE_DCACHE_32K,      L1D,    32*1024,        64, \
 160         "Data L1 cache, 32K, 8-way set assocative, 64byte line size"),
 161 CACHE_DESC(CPUID_CACHE_ICACHE_32K,      L1I,    32*1024,        64, \
 162         "Instruction L1 cache, 32K, 8-way set associative, 64byte line size"),
 163 CACHE_DESC(CPUID_CACHE_DCACHE_16K_8,    L1D,    16*1024,        64, \
 164         "Data L1 cache, 16K, 8-way set associative, 64byte line size"),
 165 CACHE_DESC(CPUID_CACHE_TRACE_12K,       L1I,    12*1024,        64, \
 166         "Trace cache, 12K-uop, 8-way set associative"),
 167 CACHE_DESC(CPUID_CACHE_TRACE_16K,       L1I,    16*1024,        64, \
 168         "Trace cache, 16K-uop, 8-way set associative"),
 169 CACHE_DESC(CPUID_CACHE_TRACE_32K,       L1I,    32*1024,        64, \
 170         "Trace cache, 32K-uop, 8-way set associative"),
 171 CACHE_DESC(CPUID_CACHE_UCACHE_128K,     L2U,    128*1024,       32, \
 172         "Unified L2 cache, 128K, 4-way set associative, 32byte line size"),
 173 CACHE_DESC(CPUID_CACHE_UCACHE_256K,     L2U,    128*1024,       32, \
 174         "Unified L2 cache, 256K, 4-way set associative, 32byte line size"),
 175 CACHE_DESC(CPUID_CACHE_UCACHE_512K,     L2U,    512*1024,       32, \
 176         "Unified L2 cache, 512K, 4-way set associative, 32byte line size"),
 177 CACHE_DESC(CPUID_CACHE_UCACHE_1M,       L2U,    1*1024*1024,    32, \
 178         "Unified L2 cache, 1M, 4-way set associative, 32byte line size"),
 179 CACHE_DESC(CPUID_CACHE_UCACHE_2M,       L2U,    2*1024*1024,    32, \
 180         "Unified L2 cache, 2M, 4-way set associative, 32byte line size"),
 181 CACHE_DESC(CPUID_CACHE_UCACHE_4M,       L2U,    4*1024*1024,    64, \
 182         "Unified L2 cache, 4M, 16-way set associative, 64byte line size"),
 183 CACHE_DESC(CPUID_CACHE_UCACHE_128K_64,  L2U,    128*1024,       64, \
 184         "Unified L2 cache, 128K, 8-way set associative, 64byte line size"),
 185 CACHE_DESC(CPUID_CACHE_UCACHE_256K_64,  L2U,    256*1024,       64, \
 186         "Unified L2 cache, 256K, 8-way set associative, 64byte line size"),
 187 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64,  L2U,    512*1024,       64, \
 188         "Unified L2 cache, 512K, 8-way set associative, 64byte line size"),
 189 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64,    L2U,    1*1024*1024,    64, \
 190         "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
 191 CACHE_DESC(CPUID_CACHE_UCACHE_256K_32,  L2U,    256*1024,       32, \
 192         "Unified L2 cache, 256K, 8-way set associative, 32byte line size"),
 193 CACHE_DESC(CPUID_CACHE_UCACHE_512K_32,  L2U,    512*1024,       32, \
 194         "Unified L2 cache, 512K, 8-way set associative, 32byte line size"),
 195 CACHE_DESC(CPUID_CACHE_UCACHE_1M_32,    L2U,    1*1024*1024,    32, \
 196         "Unified L2 cache, 1M, 8-way set associative, 32byte line size"),
 197 CACHE_DESC(CPUID_CACHE_UCACHE_2M_32,    L2U,    2*1024*1024,    32, \
 198         "Unified L2 cache, 2M, 8-way set associative, 32byte line size"),
 199 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_4,  L2U,    1*1024*1024,    64, \
 200         "Unified L2 cache, 1M, 4-way set associative, 64byte line size"),
 201 CACHE_DESC(CPUID_CACHE_UCACHE_2M_64,    L2U,    2*1024*1024,    64, \
 202         "Unified L2 cache, 2M, 8-way set associative, 64byte line size"),
 203 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_2,L2U,    512*1024,       64, \
 204         "Unified L2 cache, 512K, 2-way set associative, 64byte line size"),
 205 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_4,L2U,    512*1024,       64, \
 206         "Unified L2 cache, 512K, 4-way set associative, 64byte line size"),
 207 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_8,  L2U,    1*1024*1024,    64, \
 208         "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
 209 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S4,  L2U,    128*1024,       64, \
 210         "Unified L2 sectored cache, 128K, 4-way set associative, 64byte line size"),
 211 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S2,  L2U,    128*1024,       64, \
 212         "Unified L2 sectored cache, 128K, 2-way set associative, 64byte line size"),
 213 CACHE_DESC(CPUID_CACHE_UCACHE_256K_S4,  L2U,    256*1024,       64, \
 214         "Unified L2 sectored cache, 256K, 4-way set associative, 64byte line size"),
 215 CACHE_DESC(CPUID_CACHE_L3CACHE_512K,    L3U,    512*1024,       64, \
 216         "Unified L3 cache, 512K, 4-way set associative, 64byte line size"),
 217 CACHE_DESC(CPUID_CACHE_L3CACHE_1M,      L3U,    1*1024*1024,    64, \
 218         "Unified L3 cache, 1M, 8-way set associative, 64byte line size"),
 219 CACHE_DESC(CPUID_CACHE_L3CACHE_2M,      L3U,    2*1024*1024,    64, \
 220         "Unified L3 cache, 2M, 8-way set associative, 64byte line size"),
 221 CACHE_DESC(CPUID_CACHE_L3CACHE_4M,      L3U,    4*1024*1024,    64, \
 222         "Unified L3 cache, 4M, 8-way set associative, 64byte line size"),
 223 CACHE_DESC(CPUID_CACHE_PREFETCH_64,     Lnone,  0,              0,  \
 224         "64-Byte Prefetching"),
 225 CACHE_DESC(CPUID_CACHE_PREFETCH_128,    Lnone,  0,              0,  \
 226         "128-Byte Prefetching"),
 227 CACHE_DESC(CPUID_CACHE_NOCACHE, Lnone, 0, 0, \
 228         "No L2 cache or, if valid L2 cache, no L3 cache"),
 229 CACHE_DESC(CPUID_CACHE_NULL, Lnone, 0, 0, \
 230         (char *)0),
 231 };
 232
 233 static const char * get_intel_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype)
 234 {
 235         *type = CPU_TYPE_X86;
 236         *subtype = CPU_SUBTYPE_X86_ARCH1;
 237
 238     /* check for brand id string */
 239     switch(info_p->cpuid_brand) {
 240         case CPUID_BRAND_UNSUPPORTED:
 241             /* brand ID not supported; use alternate method. */
 242             switch(info_p->cpuid_family) {
 243                 case CPUID_FAMILY_486:
 244                     return "Intel 486";
 245                 case CPUID_FAMILY_586:
 246                     return "Intel Pentium";
 247                 case CPUID_FAMILY_686:
 248                     switch(info_p->cpuid_model) {
 249                         case CPUID_MODEL_P6:
 250                             return "Intel Pentium Pro";
 251                         case CPUID_MODEL_PII:
 252                             return "Intel Pentium II";
 253                         case CPUID_MODEL_P65:
 254                         case CPUID_MODEL_P66:
 255                             return "Intel Celeron";
 256                         case CPUID_MODEL_P67:
 257                         case CPUID_MODEL_P68:
 258                         case CPUID_MODEL_P6A:
 259                         case CPUID_MODEL_P6B:
 260                             return "Intel Pentium III";
 261                         case CPUID_MODEL_PM9:
 262                         case CPUID_MODEL_PMD:
 263                             return "Intel Pentium M";
 264                         default:
 265                             return "Unknown Intel P6 Family";
 266                     }
 267                 case CPUID_FAMILY_EXTENDED:
 268                     switch (info_p->cpuid_extfamily) {
 269                         case CPUID_EXTFAMILY_PENTIUM4:
 270                             *subtype = CPU_SUBTYPE_PENTIUM_4;
 271                             return "Intel Pentium 4";
 272                                                 default:
 273                                     return "Unknown Intel Extended Family";
 274                     }
 275                 default:
 276                     return "Unknown Intel Family";
 277             }
 278             break;
 279         case CPUID_BRAND_CELERON_1:
 280         case CPUID_BRAND_CELERON_A:
 281         case CPUID_BRAND_CELERON_14:
 282             return "Intel Celeron";
 283         case CPUID_BRAND_PENTIUM_III_2:
 284         case CPUID_BRAND_PENTIUM_III_4:
 285             return "Pentium III";
 286         case CPUID_BRAND_PIII_XEON:
 287                         if (info_p->cpuid_signature == 0x6B1) {
 288                                 return "Intel Celeron";
 289                         } else {
 290                                 return "Intel Pentium III Xeon";
 291                         }
 292         case CPUID_BRAND_PENTIUM_III_M:
 293             return "Mobile Intel Pentium III-M";
 294         case CPUID_BRAND_M_CELERON_7:
 295         case CPUID_BRAND_M_CELERON_F:
 296         case CPUID_BRAND_M_CELERON_13:
 297         case CPUID_BRAND_M_CELERON_17:
 298             return "Mobile Intel Celeron";
 299         case CPUID_BRAND_PENTIUM4_8:
 300         case CPUID_BRAND_PENTIUM4_9:
 301             *subtype = CPU_SUBTYPE_PENTIUM_4;
 302             return "Intel Pentium 4";
 303         case CPUID_BRAND_XEON:
 304             return "Intel Xeon";
 305         case CPUID_BRAND_XEON_MP:
 306             return "Intel Xeon MP";
 307         case CPUID_BRAND_PENTIUM4_M:
 308                         if (info_p->cpuid_signature == 0xF13) {
 309                                 return "Intel Xeon";
 310                         } else {
 311                                 *subtype = CPU_SUBTYPE_PENTIUM_4;
 312                                 return "Mobile Intel Pentium 4";
 313                         }
 314         case CPUID_BRAND_CELERON_M:
 315             return "Intel Celeron M";
 316         case CPUID_BRAND_PENTIUM_M:
 317             return "Intel Pentium M";
 318         case CPUID_BRAND_MOBILE_15:
 319         case CPUID_BRAND_MOBILE_17:
 320             return "Mobile Intel";
 321     }
 322     return "Unknown Intel";
 323 }
 324
 325 static void set_intel_cache_info( i386_cpu_info_t * info_p )
 326 {
 327         uint32_t        cpuid_result[4];
 328         uint32_t        l1d_cache_linesize = 0;
 329         unsigned int    i;
 330         unsigned int    j;
 331
 332         /* get processor cache descriptor info */
 333         do_cpuid(2, cpuid_result);
 334         for (j = 0; j < 4; j++) {
 335                 if ((cpuid_result[j] >> 31) == 1)       /* bit31 is validity */
 336                         continue;
 337                 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j];
 338         }
 339         /* first byte gives number of cpuid calls to get all descriptors */
 340         for (i = 1; i < info_p->cache_info[0]; i++) {
 341                 if (i*16 > sizeof(info_p->cache_info))
 342                         break;
 343                 do_cpuid(2, cpuid_result);
 344                 for (j = 0; j < 4; j++) {
 345                         if ((cpuid_result[j] >> 31) == 1)
 346                                 continue;
 347                         ((uint32_t *) info_p->cache_info)[4*i+j] =
 348                                 cpuid_result[j];
 349                 }
 350         }
 351
 352         /* decode the descriptors looking for L1/L2/L3 size info */
 353         for (i = 1; i < sizeof(info_p->cache_info); i++) {
 354                 cpuid_cache_desc_t      *descp;
 355                 uint8_t                 desc = info_p->cache_info[i];
 356
 357                 if (desc == CPUID_CACHE_NULL)
 358                         continue;
 359                 for (descp = cpuid_cache_desc_tab;
 360                         descp->value != CPUID_CACHE_NULL; descp++) {
 361                         if (descp->value != desc)
 362                                 continue;
 363                         info_p->cache_size[descp->type] = descp->size;
 364                         if (descp->type == L2U)
 365                                 info_p->cache_linesize = descp->linesize;
 366                         if (descp->type == L1D)
 367                                 l1d_cache_linesize = descp->linesize;
 368                         break;
 369                 }
 370         }
 371         /* For P-IIIs, L2 could be 256k or 512k but we can't tell */
 372         if (info_p->cache_size[L2U] == 0 &&
 373             info_p->cpuid_family == 0x6 && info_p->cpuid_model == 0xb) {
 374                 info_p->cache_size[L2U] = 256*1024;
 375                 info_p->cache_linesize = 32;
 376         }
 377         /* If we have no L2 cache, use the L1 data cache line size */
 378         if (info_p->cache_size[L2U] == 0)
 379             info_p->cache_linesize = l1d_cache_linesize;
 380
 381         /*
 382          * Get cache sharing info if available.
 383          */
 384         do_cpuid(0, cpuid_result);
 385         if (cpuid_result[eax] >= 4) {
 386                 uint32_t        reg[4];
 387                 uint32_t        index;
 388                 for (index = 0;; index++) {
 389                         /*
 390                          * Scan making calls for cpuid with %eax = 4
 391                          * to get info about successive cache levels
 392                          * until a null type is returned.
 393                          */
 394                         cache_type_t    type = Lnone;
 395                         uint32_t        cache_type;
 396                         uint32_t        cache_level;
 397                         uint32_t        cache_sharing;
 398
 399                         reg[eax] = 4;           /* cpuid request 4 */
 400                         reg[ecx] = index;       /* index starting at 0 */
 401                         cpuid(reg);
 402 //kprintf("cpuid(4) index=%d eax=%p\n", index, reg[eax]);
 403                         cache_type = bitfield(reg[eax], 4, 0);
 404                         if (cache_type == 0)
 405                                 break;          /* done with cache info */
 406                         cache_level   = bitfield(reg[eax],  7,  5);
 407                         cache_sharing = bitfield(reg[eax], 25, 14);
 408                         info_p->cpuid_cores_per_package =
 409                                         bitfield(reg[eax], 31, 26) + 1;
 410                         switch (cache_level) {
 411                         case 1:
 412                                 type = cache_type == 1 ? L1D :
 413                                        cache_type == 2 ? L1I :
 414                                                          Lnone;
 415                                 break;
 416                         case 2:
 417                                 type = cache_type == 3 ? L2U :
 418                                                          Lnone;
 419                                 break;
 420                         case 3:
 421                                 type = cache_type == 3 ? L3U :
 422                                                          Lnone;
 423                         }
 424                         if (type != Lnone)
 425                                 info_p->cache_sharing[type] = cache_sharing + 1;
 426                 }
 427         }
 428 }
 429
 430 static void set_cpu_intel( i386_cpu_info_t * info_p )
 431 {
 432     set_cpu_generic(info_p);
 433     set_intel_cache_info(info_p);
 434     info_p->cpuid_model_string = get_intel_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype);
 435 }
 436
 437 static const char * get_amd_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype )
 438 {
 439         *type = CPU_TYPE_X86;
 440         *subtype = CPU_SUBTYPE_X86_ARCH1;
 441
 442     /* check for brand id string */
 443     switch (info_p->cpuid_family)
 444     {
 445         case CPUID_FAMILY_486:
 446             switch (info_p->cpuid_model) {
 447                 case CPUID_MODEL_AM486_DX:
 448                 case CPUID_MODEL_AM486_DX2:
 449                 case CPUID_MODEL_AM486_DX2WB:
 450                 case CPUID_MODEL_AM486_DX4:
 451                 case CPUID_MODEL_AM486_DX4WB:
 452                     return "Am486";
 453                 case CPUID_MODEL_AM486_5X86:
 454                 case CPUID_MODEL_AM486_5X86WB:
 455                     return "Am5x86";
 456             }
 457             break;
 458         case CPUID_FAMILY_586:
 459             switch (info_p->cpuid_model) {
 460                 case CPUID_MODEL_K5M0:
 461                 case CPUID_MODEL_K5M1:
 462                 case CPUID_MODEL_K5M2:
 463                 case CPUID_MODEL_K5M3:
 464                     return "AMD-K5";
 465                 case CPUID_MODEL_K6M6:
 466                 case CPUID_MODEL_K6M7:
 467                     return "AMD-K6";
 468                 case CPUID_MODEL_K6_2:
 469                     return "AMD-K6-2";
 470                 case CPUID_MODEL_K6_III:
 471                     return "AMD-K6-III";
 472             }
 473             break;
 474         case CPUID_FAMILY_686:
 475             switch (info_p->cpuid_model) {
 476                 case CPUID_MODEL_ATHLON_M1:
 477                 case CPUID_MODEL_ATHLON_M2:
 478                 case CPUID_MODEL_ATHLON_M4:
 479                 case CPUID_MODEL_ATHLON_M6:
 480                 case CPUID_MODEL_ATHLON_M8:
 481                 case CPUID_MODEL_ATHLON_M10:
 482                     return "AMD Athlon";
 483                 case CPUID_MODEL_DURON_M3:
 484                 case CPUID_MODEL_DURON_M7:
 485                     return "AMD Duron";
 486                 default:
 487                     return "Unknown AMD Athlon";
 488             }
 489         case CPUID_FAMILY_EXTENDED:
 490             switch (info_p->cpuid_model) {
 491                 case CPUID_MODEL_ATHLON64:
 492                     return "AMD Athlon 64";
 493                 case CPUID_MODEL_OPTERON:
 494                     return "AMD Opteron";
 495                 default:
 496                     return "Unknown AMD-64";
 497             }
 498     }
 499     return "Unknown AMD";
 500 }
 501
 502 static void set_amd_cache_info( i386_cpu_info_t * info_p )
 503 {
 504     uint32_t    cpuid_result[4];
 505
 506     /* It would make sense to fill in info_p->cache_info with complete information
 507      * on the TLBs and data cache associativity, lines, etc, either by mapping
 508      * to the Intel tags (if possible), or replacing cache_info with a generic
 509      * mechanism.  But right now, nothing makes use of that information (that I know
 510      * of).
 511      */
 512
 513     /* L1 Cache and TLB Information */
 514     do_cpuid(0x80000005, cpuid_result);
 515
 516     /* EAX: TLB Information for 2-Mbyte and 4-MByte Pages */
 517     /* (ignore) */
 518
 519     /* EBX: TLB Information for 4-Kbyte Pages */
 520     /* (ignore) */
 521
 522     /* ECX: L1 Data Cache Information */
 523     info_p->cache_size[L1D] = ((cpuid_result[ecx] >> 24) & 0xFF) * 1024;
 524     info_p->cache_linesize = (cpuid_result[ecx] & 0xFF);
 525
 526     /* EDX: L1 Instruction Cache Information */
 527     info_p->cache_size[L1I] = ((cpuid_result[edx] >> 24) & 0xFF) * 1024;
 528
 529     /* L2 Cache Information */
 530     do_cpuid(0x80000006, cpuid_result);
 531
 532     /* EAX: L2 TLB Information for 2-Mbyte and 4-Mbyte Pages */
 533     /* (ignore) */
 534
 535     /* EBX: L2 TLB Information for 4-Kbyte Pages */
 536     /* (ignore) */
 537
 538     /* ECX: L2 Cache Information */
 539     info_p->cache_size[L2U] = ((cpuid_result[ecx] >> 16) & 0xFFFF) * 1024;
 540     if (info_p->cache_size[L2U] > 0)
 541         info_p->cache_linesize = cpuid_result[ecx] & 0xFF;
 542 }
 543
 544 static void set_cpu_amd( i386_cpu_info_t * info_p )
 545 {
 546     set_cpu_generic(info_p);
 547     set_amd_cache_info(info_p);
 548     info_p->cpuid_model_string = get_amd_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype);
 549 }
 550
 551 static void set_cpu_nsc( i386_cpu_info_t * info_p )
 552 {
 553     set_cpu_generic(info_p);
 554     set_amd_cache_info(info_p);
 555
 556     /* check for brand id string */
 557     if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX1) {
 558         info_p->cpuid_model_string = "AMD Geode GX1";
 559     } else if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX2) {
 560         info_p->cpuid_model_string = "AMD Geode GX";
 561     } else {
 562         info_p->cpuid_model_string = "Unknown National Semiconductor";
 563     }
 564     info_p->cpuid_cpu_type = CPU_TYPE_X86;
 565     info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
 566 }
 567
 568 static void
 569 set_cpu_generic(i386_cpu_info_t *info_p)
 570 {
 571         uint32_t        cpuid_result[4];
 572         uint32_t        max_extid;
 573         char            str[128], *p;
 574
 575         /* get extended cpuid results */
 576         do_cpuid(0x80000000, cpuid_result);
 577         max_extid = cpuid_result[eax];
 578
 579         /* check to see if we can get brand string */
 580         if (max_extid >= 0x80000004) {
 581                 /*
 582                  * The brand string 48 bytes (max), guaranteed to
 583                  * be NUL terminated.
 584                  */
 585                 do_cpuid(0x80000002, cpuid_result);
 586                 bcopy((char *)cpuid_result, &str[0], 16);
 587                 do_cpuid(0x80000003, cpuid_result);
 588                 bcopy((char *)cpuid_result, &str[16], 16);
 589                 do_cpuid(0x80000004, cpuid_result);
 590                 bcopy((char *)cpuid_result, &str[32], 16);
 591                 for (p = str; *p != '\0'; p++) {
 592                         if (*p != ' ') break;
 593                 }
 594                 strncpy(info_p->cpuid_brand_string,
 595                         p, sizeof(info_p->cpuid_brand_string)-1);
 596                 info_p->cpuid_brand_string[sizeof(info_p->cpuid_brand_string)-1] = '\0';
 597
 598                 if (!strcmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN)) {
 599                     /*
 600                      * This string means we have a BIOS-programmable brand string,
 601                      * and the BIOS couldn't figure out what sort of CPU we have.
 602                      */
 603                     info_p->cpuid_brand_string[0] = '\0';
 604                 }
 605         }
 606
 607         /* get processor signature and decode */
 608         do_cpuid(1, cpuid_result);
 609         info_p->cpuid_signature = cpuid_result[eax];
 610         info_p->cpuid_stepping  = bitfield(cpuid_result[eax],  3,  0);
 611         info_p->cpuid_model     = bitfield(cpuid_result[eax],  7,  4);
 612         info_p->cpuid_family    = bitfield(cpuid_result[eax], 11,  8);
 613         info_p->cpuid_type      = bitfield(cpuid_result[eax], 13, 12);
 614         info_p->cpuid_extmodel  = bitfield(cpuid_result[eax], 19, 16);
 615         info_p->cpuid_extfamily = bitfield(cpuid_result[eax], 27, 20);
 616         info_p->cpuid_brand     = bitfield(cpuid_result[ebx],  7,  0);
 617         info_p->cpuid_logical_per_package =
 618                                   bitfield(cpuid_result[ebx], 23, 16);
 619         info_p->cpuid_features  = quad(cpuid_result[ecx], cpuid_result[edx]);
 620
 621         if (max_extid >= 0x80000001) {
 622                 do_cpuid(0x80000001, cpuid_result);
 623                 info_p->cpuid_extfeatures =
 624                                 quad(cpuid_result[ecx], cpuid_result[edx]);
 625         }
 626
 627         return;
 628 }
 629
 630 static void
 631 set_cpu_unknown(__unused i386_cpu_info_t *info_p)
 632 {
 633     info_p->cpuid_model_string = "Unknown";
 634 }
 635
 636
 637 static struct {
 638         uint64_t        mask;
 639         const char      *name;
 640 } feature_map[] = {
 641         {CPUID_FEATURE_FPU,   "FPU",},
 642         {CPUID_FEATURE_VME,   "VME",},
 643         {CPUID_FEATURE_DE,    "DE",},
 644         {CPUID_FEATURE_PSE,   "PSE",},
 645         {CPUID_FEATURE_TSC,   "TSC",},
 646         {CPUID_FEATURE_MSR,   "MSR",},
 647         {CPUID_FEATURE_PAE,   "PAE",},
 648         {CPUID_FEATURE_MCE,   "MCE",},
 649         {CPUID_FEATURE_CX8,   "CX8",},
 650         {CPUID_FEATURE_APIC,  "APIC",},
 651         {CPUID_FEATURE_SEP,   "SEP",},
 652         {CPUID_FEATURE_MTRR,  "MTRR",},
 653         {CPUID_FEATURE_PGE,   "PGE",},
 654         {CPUID_FEATURE_MCA,   "MCA",},
 655         {CPUID_FEATURE_CMOV,  "CMOV",},
 656         {CPUID_FEATURE_PAT,   "PAT",},
 657         {CPUID_FEATURE_PSE36, "PSE36",},
 658         {CPUID_FEATURE_PSN,   "PSN",},
 659         {CPUID_FEATURE_CLFSH, "CLFSH",},
 660         {CPUID_FEATURE_DS,    "DS",},
 661         {CPUID_FEATURE_ACPI,  "ACPI",},
 662         {CPUID_FEATURE_MMX,   "MMX",},
 663         {CPUID_FEATURE_FXSR,  "FXSR",},
 664         {CPUID_FEATURE_SSE,   "SSE",},
 665         {CPUID_FEATURE_SSE2,  "SSE2",},
 666         {CPUID_FEATURE_SS,    "SS",},
 667         {CPUID_FEATURE_HTT,   "HTT",},
 668         {CPUID_FEATURE_TM,    "TM",},
 669         {CPUID_FEATURE_SSE3,    "SSE3"},
 670         {CPUID_FEATURE_MONITOR, "MON"},
 671         {CPUID_FEATURE_DSCPL,   "DSCPL"},
 672         {CPUID_FEATURE_VMX,     "VMX"},
 673         {CPUID_FEATURE_SMX,     "SMX"},
 674         {CPUID_FEATURE_EST,     "EST"},
 675         {CPUID_FEATURE_TM2,     "TM2"},
 676         {CPUID_FEATURE_MNI,     "MNI"},
 677         {CPUID_FEATURE_CID,     "CID"},
 678         {CPUID_FEATURE_CX16,    "CX16"},
 679         {CPUID_FEATURE_xTPR,    "TPR"},
 680         {0, 0}
 681 },
 682 extfeature_map[] = {
 683         {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"},
 684         {CPUID_EXTFEATURE_XD,      "XD"},
 685         {CPUID_EXTFEATURE_EM64T,   "EM64T"},
 686         {CPUID_EXTFEATURE_LAHF,    "LAHF"},
 687         {0, 0}
 688 };
 689
 690 i386_cpu_info_t *
 691 cpuid_info(void)
 692 {
 693         /* Set-up the cpuid_indo stucture lazily */
 694         if (cpuid_cpu_infop == NULL) {
 695                 cpuid_get_info(&cpuid_cpu_info);
 696                 cpuid_cpu_infop = &cpuid_cpu_info;
 697         }
 698         return cpuid_cpu_infop;
 699 }
 700
 701 char *
 702 cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len)
 703 {
 704         int     len = -1;
 705         char    *p = buf;
 706         int     i;
 707
 708         for (i = 0; feature_map[i].mask != 0; i++) {
 709                 if ((features & feature_map[i].mask) == 0)
 710                         continue;
 711                 if (len > 0)
 712                         *p++ = ' ';
 713                 len = min(strlen(feature_map[i].name), (buf_len-1) - (p-buf));
 714                 if (len == 0)
 715                         break;
 716                 bcopy(feature_map[i].name, p, len);
 717                 p += len;
 718         }
 719         *p = '\0';
 720         return buf;
 721 }
 722
 723 char *
 724 cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len)
 725 {
 726         int     len = -1;
 727         char    *p = buf;
 728         int     i;
 729
 730         for (i = 0; extfeature_map[i].mask != 0; i++) {
 731                 if ((extfeatures & extfeature_map[i].mask) == 0)
 732                         continue;
 733                 if (len > 0)
 734                         *p++ = ' ';
 735                 len = min(strlen(extfeature_map[i].name), (buf_len-1)-(p-buf));
 736                 if (len == 0)
 737                         break;
 738                 bcopy(extfeature_map[i].name, p, len);
 739                 p += len;
 740         }
 741         *p = '\0';
 742         return buf;
 743 }
 744
 745 void
 746 cpuid_feature_display(
 747         const char      *header)
 748 {
 749         char    buf[256];
 750
 751         kprintf("%s: %s\n", header,
 752                   cpuid_get_feature_names(cpuid_features(),
 753                                                 buf, sizeof(buf)));
 754         if (cpuid_features() & CPUID_FEATURE_HTT) {
 755 #define s_if_plural(n)  ((n > 1) ? "s" : "")
 756                 kprintf("  HTT: %d core%s per package;"
 757                              " %d logical cpu%s per package\n",
 758                         cpuid_cpu_info.cpuid_cores_per_package,
 759                         s_if_plural(cpuid_cpu_info.cpuid_cores_per_package),
 760                         cpuid_cpu_info.cpuid_logical_per_package,
 761                         s_if_plural(cpuid_cpu_info.cpuid_logical_per_package));
 762         }
 763 }
 764
 765 void
 766 cpuid_extfeature_display(
 767         const char      *header)
 768 {
 769         char    buf[256];
 770
 771         kprintf("%s: %s\n", header,
 772                   cpuid_get_extfeature_names(cpuid_extfeatures(),
 773                                                 buf, sizeof(buf)));
 774 }
 775
 776 void
 777 cpuid_cpu_display(
 778         const char      *header)
 779 {
 780     if (cpuid_info()->cpuid_brand_string[0] != '\0') {
 781         kprintf("%s: %s\n", header, cpuid_cpu_info.cpuid_brand_string);
 782     }
 783 }
 784
 785 unsigned int
 786 cpuid_family(void)
 787 {
 788         return cpuid_info()->cpuid_family;
 789 }
 790
 791 cpu_type_t
 792 cpuid_cputype(void)
 793 {
 794         return cpuid_info()->cpuid_cpu_type;
 795 }
 796
 797 cpu_subtype_t
 798 cpuid_cpusubtype(void)
 799 {
 800         return cpuid_info()->cpuid_cpu_subtype;
 801 }
 802
 803 uint64_t
 804 cpuid_features(void)
 805 {
 806         static int checked = 0;
 807         char    fpu_arg[16] = { 0 };
 808
 809         (void) cpuid_info();
 810         if (!checked) {
 811                     /* check for boot-time fpu limitations */
 812                         if (PE_parse_boot_arg("_fpu", &fpu_arg[0])) {
 813                                 printf("limiting fpu features to: %s\n", fpu_arg);
 814                                 if (!strncmp("387", fpu_arg, sizeof "387") || !strncmp("mmx", fpu_arg, sizeof "mmx")) {
 815                                         printf("no sse or sse2\n");
 816                                         cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
 817                                 } else if (!strncmp("sse", fpu_arg, sizeof "sse")) {
 818                                         printf("no sse2\n");
 819                                         cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2);
 820                                 }
 821                         }
 822                         checked = 1;
 823         }
 824         return cpuid_cpu_info.cpuid_features;
 825 }
 826
 827 uint64_t
 828 cpuid_extfeatures(void)
 829 {
 830         return cpuid_info()->cpuid_extfeatures;
 831 }
 832
 833 void
 834 cpuid_set_info(void)
 835 {
 836         cpuid_get_info(&cpuid_cpu_info);
 837 }
 838
 839 #if MACH_KDB
 840
 841 /*
 842  *      Display the cpuid
 843  * *
 844  *      cp
 845  */
 846 void
 847 db_cpuid(__unused db_expr_t addr,
 848          __unused int have_addr,
 849          __unused db_expr_t count,
 850          __unused char *modif)
 851 {
 852
 853         uint32_t        i, mid;
 854         uint32_t        cpid[4];
 855
 856         do_cpuid(0, cpid);      /* Get the first cpuid which is the number of
 857                                  * basic ids */
 858         db_printf("%08X - %08X %08X %08X %08X\n",
 859                 0, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
 860
 861         mid = cpid[eax];        /* Set the number */
 862         for (i = 1; i <= mid; i++) {    /* Dump 'em out */
 863                 do_cpuid(i, cpid);      /* Get the next */
 864                 db_printf("%08X - %08X %08X %08X %08X\n",
 865                         i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
 866         }
 867         db_printf("\n");
 868
 869         do_cpuid(0x80000000, cpid);     /* Get the first extended cpuid which
 870                                          * is the number of extended ids */
 871         db_printf("%08X - %08X %08X %08X %08X\n",
 872                 0x80000000, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
 873
 874         mid = cpid[eax];        /* Set the number */
 875         for (i = 0x80000001; i <= mid; i++) {   /* Dump 'em out */
 876                 do_cpuid(i, cpid);      /* Get the next */
 877                 db_printf("%08X - %08X %08X %08X %08X\n",
 878                         i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
 879         }
 880 }
 881
 882 #endif