osfmk/ppc/machine_routines.c

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
   7  *
   8  * This file contains Original Code and/or Modifications of Original Code
   9  * as defined in and that are subject to the Apple Public Source License
  10  * Version 2.0 (the 'License'). You may not use this file except in
  11  * compliance with the License. Please obtain a copy of the License at
  12  * http://www.opensource.apple.com/apsl/ and read it before using this
  13  * file.
  14  *
  15  * The Original Code and all software distributed under the License are
  16  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  17  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  18  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  20  * Please see the License for the specific language governing rights and
  21  * limitations under the License.
  22  *
  23  * @APPLE_LICENSE_HEADER_END@
  24  */
  25 #include <ppc/machine_routines.h>
  26 #include <ppc/machine_cpu.h>
  27 #include <ppc/exception.h>
  28 #include <ppc/misc_protos.h>
  29 #include <ppc/Firmware.h>
  30 #include <vm/vm_page.h>
  31 #include <ppc/pmap.h>
  32 #include <ppc/proc_reg.h>
  33 #include <kern/processor.h>
  34
  35 unsigned int max_cpus_initialized = 0;
  36
  37 #define MAX_CPUS_SET    0x1
  38 #define MAX_CPUS_WAIT   0x2
  39
  40 boolean_t get_interrupts_enabled(void);
  41
  42 /* Map memory map IO space */
  43 vm_offset_t
  44 ml_io_map(
  45         vm_offset_t phys_addr,
  46         vm_size_t size)
  47 {
  48         return(io_map(phys_addr,size));
  49 }
  50
  51 /* static memory allocation */
  52 vm_offset_t
  53 ml_static_malloc(
  54         vm_size_t size)
  55 {
  56         extern vm_offset_t static_memory_end;
  57         extern boolean_t pmap_initialized;
  58         vm_offset_t vaddr;
  59
  60         if (pmap_initialized)
  61                 return((vm_offset_t)NULL);
  62         else {
  63                 vaddr = static_memory_end;
  64                 static_memory_end = round_page(vaddr+size);
  65                 return(vaddr);
  66         }
  67 }
  68
  69 vm_offset_t
  70 ml_static_ptovirt(
  71         vm_offset_t paddr)
  72 {
  73         extern vm_offset_t static_memory_end;
  74         vm_offset_t vaddr;
  75
  76         /* Static memory is map V=R */
  77         vaddr = paddr;
  78         if ( (vaddr < static_memory_end) && (pmap_extract(kernel_pmap, vaddr)==paddr) )
  79                 return(vaddr);
  80         else
  81                 return((vm_offset_t)NULL);
  82 }
  83
  84 void
  85 ml_static_mfree(
  86         vm_offset_t vaddr,
  87         vm_size_t size)
  88 {
  89         vm_offset_t paddr_cur, vaddr_cur;
  90
  91         for (vaddr_cur = round_page(vaddr);
  92              vaddr_cur < trunc_page(vaddr+size);
  93              vaddr_cur += PAGE_SIZE) {
  94                 paddr_cur = pmap_extract(kernel_pmap, vaddr_cur);
  95                 if (paddr_cur != (vm_offset_t)NULL) {
  96                         vm_page_wire_count--;
  97                         pmap_remove(kernel_pmap, vaddr_cur, vaddr_cur+PAGE_SIZE);
  98                         vm_page_create(paddr_cur,paddr_cur+PAGE_SIZE);
  99                 }
 100         }
 101 }
 102
 103 /* virtual to physical on wired pages */
 104 vm_offset_t ml_vtophys(
 105         vm_offset_t vaddr)
 106 {
 107         return(pmap_extract(kernel_pmap, vaddr));
 108 }
 109
 110 /* Initialize Interrupt Handler */
 111 void ml_install_interrupt_handler(
 112         void *nub,
 113         int source,
 114         void *target,
 115         IOInterruptHandler handler,
 116         void *refCon)
 117 {
 118         int     current_cpu;
 119         boolean_t current_state;
 120
 121         current_cpu = cpu_number();
 122         current_state = ml_get_interrupts_enabled();
 123
 124         per_proc_info[current_cpu].interrupt_nub     = nub;
 125         per_proc_info[current_cpu].interrupt_source  = source;
 126         per_proc_info[current_cpu].interrupt_target  = target;
 127         per_proc_info[current_cpu].interrupt_handler = handler;
 128         per_proc_info[current_cpu].interrupt_refCon  = refCon;
 129
 130         per_proc_info[current_cpu].interrupts_enabled = TRUE;
 131         (void) ml_set_interrupts_enabled(current_state);
 132
 133         initialize_screen(0, kPEAcquireScreen);
 134 }
 135
 136 /* Initialize Interrupts */
 137 void ml_init_interrupt(void)
 138 {
 139         int     current_cpu;
 140         boolean_t current_state;
 141
 142         current_state = ml_get_interrupts_enabled();
 143
 144         current_cpu = cpu_number();
 145         per_proc_info[current_cpu].interrupts_enabled = TRUE;
 146         (void) ml_set_interrupts_enabled(current_state);
 147 }
 148
 149 boolean_t fake_get_interrupts_enabled(void)
 150 {
 151         /*
 152          * The scheduler is not active on this cpu. There is no need to disable
 153          * preemption. The current thread wont be dispatched on anhother cpu.
 154          */
 155         return((per_proc_info[cpu_number()].cpu_flags & turnEEon) != 0);
 156 }
 157
 158 boolean_t fake_set_interrupts_enabled(boolean_t enable)
 159 {
 160         boolean_t interrupt_state_prev;
 161
 162         /*
 163          * The scheduler is not active on this cpu. There is no need to disable
 164          * preemption. The current thread wont be dispatched on anhother cpu.
 165          */
 166         interrupt_state_prev =
 167                 (per_proc_info[cpu_number()].cpu_flags & turnEEon) != 0;
 168         if (interrupt_state_prev != enable)
 169                 per_proc_info[cpu_number()].cpu_flags ^= turnEEon;
 170         return(interrupt_state_prev);
 171 }
 172
 173 /* Get Interrupts Enabled */
 174 boolean_t ml_get_interrupts_enabled(void)
 175 {
 176         if (per_proc_info[cpu_number()].interrupts_enabled == TRUE)
 177                 return(get_interrupts_enabled());
 178         else
 179                 return(fake_get_interrupts_enabled());
 180 }
 181
 182 boolean_t get_interrupts_enabled(void)
 183 {
 184         return((mfmsr() & MASK(MSR_EE)) != 0);
 185 }
 186
 187 /* Check if running at interrupt context */
 188 boolean_t ml_at_interrupt_context(void)
 189 {
 190         boolean_t       ret;
 191         boolean_t       current_state;
 192
 193         current_state = ml_set_interrupts_enabled(FALSE);
 194         ret = (per_proc_info[cpu_number()].istackptr == 0);
 195         ml_set_interrupts_enabled(current_state);
 196         return(ret);
 197 }
 198
 199 /* Generate a fake interrupt */
 200 void ml_cause_interrupt(void)
 201 {
 202         CreateFakeIO();
 203 }
 204
 205 void ml_thread_policy(
 206         thread_t thread,
 207         unsigned policy_id,
 208         unsigned policy_info)
 209 {
 210         if ((policy_id == MACHINE_GROUP) &&
 211                 ((per_proc_info[0].pf.Available) & pfSMPcap))
 212                         thread_bind(thread, master_processor);
 213
 214         if (policy_info & MACHINE_NETWORK_WORKLOOP) {
 215                 spl_t           s = splsched();
 216
 217                 thread_lock(thread);
 218
 219                 thread->sched_mode |= TH_MODE_FORCEDPREEMPT;
 220                 set_priority(thread, thread->priority + 1);
 221
 222                 thread_unlock(thread);
 223                 splx(s);
 224         }
 225 }
 226
 227 void machine_idle(void)
 228 {
 229         if (per_proc_info[cpu_number()].interrupts_enabled == TRUE) {
 230                 int cur_decr;
 231
 232                 machine_idle_ppc();
 233
 234                 /*
 235                  * protect against a lost decrementer trap
 236                  * if the current decrementer value is negative
 237                  * by more than 10 ticks, re-arm it since it's
 238                  * unlikely to fire at this point... a hardware
 239                  * interrupt got us out of machine_idle and may
 240                  * also be contributing to this state
 241                  */
 242                 cur_decr = isync_mfdec();
 243
 244                 if (cur_decr < -10) {
 245                         mtdec(1);
 246                 }
 247         }
 248 }
 249
 250 void
 251 machine_signal_idle(
 252         processor_t processor)
 253 {
 254         (void)cpu_signal(processor->slot_num, SIGPwake, 0, 0);
 255 }
 256
 257 kern_return_t
 258 ml_processor_register(
 259         ml_processor_info_t *processor_info,
 260         processor_t         *processor,
 261         ipi_handler_t       *ipi_handler)
 262 {
 263         kern_return_t ret;
 264         int target_cpu;
 265
 266         if (processor_info->boot_cpu == FALSE) {
 267                  if (cpu_register(&target_cpu) != KERN_SUCCESS)
 268                         return KERN_FAILURE;
 269         } else {
 270                 /* boot_cpu is always 0 */
 271                 target_cpu= 0;
 272         }
 273
 274         per_proc_info[target_cpu].cpu_id = processor_info->cpu_id;
 275         per_proc_info[target_cpu].start_paddr = processor_info->start_paddr;
 276
 277         if(per_proc_info[target_cpu].pf.Available & pfCanNap)
 278           if(processor_info->supports_nap)
 279                 per_proc_info[target_cpu].pf.Available |= pfWillNap;
 280
 281         if(processor_info->time_base_enable !=  (void(*)(cpu_id_t, boolean_t ))NULL)
 282                 per_proc_info[target_cpu].time_base_enable = processor_info->time_base_enable;
 283         else
 284                 per_proc_info[target_cpu].time_base_enable = (void(*)(cpu_id_t, boolean_t ))NULL;
 285
 286         if(target_cpu == cpu_number())
 287                 __asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available));       /* Set live value */
 288
 289         *processor = cpu_to_processor(target_cpu);
 290         *ipi_handler = cpu_signal_handler;
 291
 292         return KERN_SUCCESS;
 293 }
 294
 295 boolean_t
 296 ml_enable_nap(int target_cpu, boolean_t nap_enabled)
 297 {
 298     boolean_t prev_value = (per_proc_info[target_cpu].pf.Available & pfCanNap) && (per_proc_info[target_cpu].pf.Available & pfWillNap);
 299
 300         if(per_proc_info[target_cpu].pf.Available & pfCanNap) {                         /* Can the processor nap? */
 301                 if (nap_enabled) per_proc_info[target_cpu].pf.Available |= pfWillNap;   /* Is nap supported on this machine? */
 302                 else per_proc_info[target_cpu].pf.Available &= ~pfWillNap;              /* Clear if not */
 303         }
 304
 305         if(target_cpu == cpu_number())
 306                 __asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available));       /* Set live value */
 307
 308     return (prev_value);
 309 }
 310
 311 void
 312 ml_init_max_cpus(unsigned long max_cpus)
 313 {
 314         boolean_t current_state;
 315
 316         current_state = ml_set_interrupts_enabled(FALSE);
 317         if (max_cpus_initialized != MAX_CPUS_SET) {
 318                 if (max_cpus > 0 && max_cpus < NCPUS)
 319                         machine_info.max_cpus = max_cpus;
 320                 if (max_cpus_initialized == MAX_CPUS_WAIT)
 321                         wakeup((event_t)&max_cpus_initialized);
 322                 max_cpus_initialized = MAX_CPUS_SET;
 323         }
 324         (void) ml_set_interrupts_enabled(current_state);
 325 }
 326
 327 int
 328 ml_get_max_cpus(void)
 329 {
 330         boolean_t current_state;
 331
 332         current_state = ml_set_interrupts_enabled(FALSE);
 333         if (max_cpus_initialized != MAX_CPUS_SET) {
 334                 max_cpus_initialized = MAX_CPUS_WAIT;
 335                 assert_wait((event_t)&max_cpus_initialized, THREAD_UNINT);
 336                 (void)thread_block(THREAD_CONTINUE_NULL);
 337         }
 338         (void) ml_set_interrupts_enabled(current_state);
 339         return(machine_info.max_cpus);
 340 }
 341
 342 int
 343 ml_get_current_cpus(void)
 344 {
 345         return machine_info.avail_cpus;
 346 }
 347
 348 void
 349 ml_cpu_get_info(ml_cpu_info_t *cpu_info)
 350 {
 351   if (cpu_info == 0) return;
 352
 353   cpu_info->vector_unit = (per_proc_info[0].pf.Available & pfAltivec) != 0;
 354   cpu_info->cache_line_size = per_proc_info[0].pf.lineSize;
 355   cpu_info->l1_icache_size = per_proc_info[0].pf.l1iSize;
 356   cpu_info->l1_dcache_size = per_proc_info[0].pf.l1dSize;
 357
 358   if (per_proc_info[0].pf.Available & pfL2) {
 359     cpu_info->l2_settings = per_proc_info[0].pf.l2cr;
 360     cpu_info->l2_cache_size = per_proc_info[0].pf.l2Size;
 361   } else {
 362     cpu_info->l2_settings = 0;
 363     cpu_info->l2_cache_size = 0xFFFFFFFF;
 364   }
 365   if (per_proc_info[0].pf.Available & pfL3) {
 366     cpu_info->l3_settings = per_proc_info[0].pf.l3cr;
 367     cpu_info->l3_cache_size = per_proc_info[0].pf.l3Size;
 368   } else {
 369     cpu_info->l3_settings = 0;
 370     cpu_info->l3_cache_size = 0xFFFFFFFF;
 371   }
 372 }
 373
 374 #define l2em 0x80000000
 375 #define l3em 0x80000000
 376
 377 extern int real_ncpus;
 378
 379 int
 380 ml_enable_cache_level(int cache_level, int enable)
 381 {
 382   int old_mode;
 383   unsigned long available, ccr;
 384
 385   if (real_ncpus != 1) return -1;
 386
 387   available = per_proc_info[0].pf.Available;
 388
 389   if ((cache_level == 2) && (available & pfL2)) {
 390     ccr = per_proc_info[0].pf.l2cr;
 391     old_mode = (ccr & l2em) ? TRUE : FALSE;
 392     if (old_mode != enable) {
 393       if (enable) ccr = per_proc_info[0].pf.l2crOriginal;
 394       else ccr = 0;
 395       per_proc_info[0].pf.l2cr = ccr;
 396       cacheInit();
 397     }
 398
 399     return old_mode;
 400   }
 401
 402   if ((cache_level == 3) && (available & pfL3)) {
 403     ccr = per_proc_info[0].pf.l3cr;
 404     old_mode = (ccr & l3em) ? TRUE : FALSE;
 405     if (old_mode != enable) {
 406       if (enable) ccr = per_proc_info[0].pf.l3crOriginal;
 407       else ccr = 0;
 408       per_proc_info[0].pf.l3cr = ccr;
 409       cacheInit();
 410     }
 411
 412     return old_mode;
 413   }
 414
 415   return -1;
 416 }
 417
 418 void
 419 init_ast_check(processor_t processor)
 420 {}
 421
 422 void
 423 cause_ast_check(
 424         processor_t             processor)
 425 {
 426         if (    processor != current_processor()                                                                &&
 427                 per_proc_info[processor->slot_num].interrupts_enabled == TRUE   )
 428                 cpu_signal(processor->slot_num, SIGPast, NULL, NULL);
 429 }
 430
 431 thread_t
 432 switch_to_shutdown_context(
 433         thread_t        thread,
 434         void            (*doshutdown)(processor_t),
 435         processor_t     processor)
 436 {
 437         CreateShutdownCTX();
 438         return((thread_t)(per_proc_info[cpu_number()].old_thread));
 439 }
 440
 441 int
 442 set_be_bit()
 443 {
 444
 445         int mycpu;
 446         boolean_t current_state;
 447
 448         current_state = ml_set_interrupts_enabled(FALSE);       /* Can't allow interruptions when mucking with per_proc flags */
 449         mycpu = cpu_number();
 450         per_proc_info[mycpu].cpu_flags |= traceBE;
 451         (void) ml_set_interrupts_enabled(current_state);
 452         return(1);
 453 }
 454
 455 int
 456 clr_be_bit()
 457 {
 458         int mycpu;
 459         boolean_t current_state;
 460
 461         current_state = ml_set_interrupts_enabled(FALSE);       /* Can't allow interruptions when mucking with per_proc flags */
 462         mycpu = cpu_number();
 463         per_proc_info[mycpu].cpu_flags &= ~traceBE;
 464         (void) ml_set_interrupts_enabled(current_state);
 465         return(1);
 466 }
 467
 468 int
 469 be_tracing()
 470 {
 471   int mycpu = cpu_number();
 472   return(per_proc_info[mycpu].cpu_flags & traceBE);
 473 }
 474