[apple/xnu.git] / osfmk / ppc / machine_routines.c

/*
 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this
 * file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
#include <ppc/machine_routines.h>
#include <ppc/machine_cpu.h>
#include <ppc/exception.h>
#include <ppc/misc_protos.h>
#include <ppc/Firmware.h>
#include <vm/vm_page.h>
#include <ppc/pmap.h>
#include <ppc/proc_reg.h>
#include <kern/processor.h>

unsigned int max_cpus_initialized = 0;

#define	MAX_CPUS_SET	0x1
#define	MAX_CPUS_WAIT	0x2

boolean_t get_interrupts_enabled(void);

/* Map memory map IO space */
vm_offset_t 
ml_io_map(
	vm_offset_t phys_addr, 
	vm_size_t size)
{
	return(io_map(phys_addr,size));
}

/* static memory allocation */
vm_offset_t 
ml_static_malloc(
	vm_size_t size)
{
	extern vm_offset_t static_memory_end;
	extern boolean_t pmap_initialized;
	vm_offset_t vaddr;

	if (pmap_initialized)
		return((vm_offset_t)NULL);
	else {
		vaddr = static_memory_end;
		static_memory_end = round_page(vaddr+size);
		return(vaddr);
	}
}

vm_offset_t
ml_static_ptovirt(
	vm_offset_t paddr)
{
	extern vm_offset_t static_memory_end;
	vm_offset_t vaddr;

	/* Static memory is map V=R */
	vaddr = paddr;
	if ( (vaddr < static_memory_end) && (pmap_extract(kernel_pmap, vaddr)==paddr) )
		return(vaddr);
	else
		return((vm_offset_t)NULL);
}

void
ml_static_mfree(
	vm_offset_t vaddr,
	vm_size_t size)
{
	vm_offset_t paddr_cur, vaddr_cur;

	for (vaddr_cur = round_page(vaddr);
	     vaddr_cur < trunc_page(vaddr+size);
	     vaddr_cur += PAGE_SIZE) {
		paddr_cur = pmap_extract(kernel_pmap, vaddr_cur);
		if (paddr_cur != (vm_offset_t)NULL) {
			vm_page_wire_count--;
			pmap_remove(kernel_pmap, vaddr_cur, vaddr_cur+PAGE_SIZE);
			vm_page_create(paddr_cur,paddr_cur+PAGE_SIZE);
		}
	}
}

/* virtual to physical on wired pages */
vm_offset_t ml_vtophys(
	vm_offset_t vaddr)
{
	return(pmap_extract(kernel_pmap, vaddr));
}

/* Initialize Interrupt Handler */
void ml_install_interrupt_handler(
	void *nub,
	int source,
	void *target,
	IOInterruptHandler handler,
	void *refCon)
{
	int	current_cpu;
	boolean_t current_state;

	current_cpu = cpu_number();
	current_state = ml_get_interrupts_enabled();

	per_proc_info[current_cpu].interrupt_nub     = nub;
	per_proc_info[current_cpu].interrupt_source  = source;
	per_proc_info[current_cpu].interrupt_target  = target;
	per_proc_info[current_cpu].interrupt_handler = handler;
	per_proc_info[current_cpu].interrupt_refCon  = refCon;

	per_proc_info[current_cpu].interrupts_enabled = TRUE;  
	(void) ml_set_interrupts_enabled(current_state);

	initialize_screen(0, kPEAcquireScreen);
}

/* Initialize Interrupts */
void ml_init_interrupt(void)
{
	int	current_cpu;
	boolean_t current_state;

	current_state = ml_get_interrupts_enabled();

	current_cpu = cpu_number();
	per_proc_info[current_cpu].interrupts_enabled = TRUE;  
	(void) ml_set_interrupts_enabled(current_state);
}

boolean_t fake_get_interrupts_enabled(void)
{
	/*
	 * The scheduler is not active on this cpu. There is no need to disable 
	 * preemption. The current thread wont be dispatched on anhother cpu.
	 */
	return((per_proc_info[cpu_number()].cpu_flags & turnEEon) != 0);
}

boolean_t fake_set_interrupts_enabled(boolean_t enable)
{
	boolean_t interrupt_state_prev;

	/*
	 * The scheduler is not active on this cpu. There is no need to disable 
	 * preemption. The current thread wont be dispatched on anhother cpu.
	 */
	interrupt_state_prev = 
		(per_proc_info[cpu_number()].cpu_flags & turnEEon) != 0;
	if (interrupt_state_prev != enable)
		per_proc_info[cpu_number()].cpu_flags ^= turnEEon;
	return(interrupt_state_prev);
}

/* Get Interrupts Enabled */
boolean_t ml_get_interrupts_enabled(void)
{
	if (per_proc_info[cpu_number()].interrupts_enabled == TRUE)
		return(get_interrupts_enabled());
	else
		return(fake_get_interrupts_enabled());
}

boolean_t get_interrupts_enabled(void)
{
	return((mfmsr() & MASK(MSR_EE)) != 0);
}

/* Check if running at interrupt context */
boolean_t ml_at_interrupt_context(void)
{
	boolean_t	ret;
	boolean_t	current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
 	ret = (per_proc_info[cpu_number()].istackptr == 0);	
	ml_set_interrupts_enabled(current_state);
	return(ret);
}

/* Generate a fake interrupt */
void ml_cause_interrupt(void)
{
	CreateFakeIO();
}

void ml_thread_policy(
	thread_t thread,
	unsigned policy_id,
	unsigned policy_info)
{
	if ((policy_id == MACHINE_GROUP) &&
		((per_proc_info[0].pf.Available) & pfSMPcap))
			thread_bind(thread, master_processor);

	if (policy_info & MACHINE_NETWORK_WORKLOOP) {
		spl_t		s = splsched();

		thread_lock(thread);

		thread->sched_mode |= TH_MODE_FORCEDPREEMPT;
		set_priority(thread, thread->priority + 1);

		thread_unlock(thread);
		splx(s);
	}
}

void machine_idle(void)
{
        if (per_proc_info[cpu_number()].interrupts_enabled == TRUE) {
	        int cur_decr;

	        machine_idle_ppc();

		/*
		 * protect against a lost decrementer trap
		 * if the current decrementer value is negative
		 * by more than 10 ticks, re-arm it since it's 
		 * unlikely to fire at this point... a hardware
		 * interrupt got us out of machine_idle and may
		 * also be contributing to this state
		 */
		cur_decr = isync_mfdec();

		if (cur_decr < -10) {
		        mtdec(1);
		}
	}
}

void
machine_signal_idle(
	processor_t processor)
{
	(void)cpu_signal(processor->slot_num, SIGPwake, 0, 0);
}

kern_return_t
ml_processor_register(
	ml_processor_info_t *processor_info,
	processor_t	    *processor,
	ipi_handler_t       *ipi_handler)
{
	kern_return_t ret;
	int target_cpu;

	if (processor_info->boot_cpu == FALSE) {
		 if (cpu_register(&target_cpu) != KERN_SUCCESS)
			return KERN_FAILURE;
	} else {
		/* boot_cpu is always 0 */
		target_cpu= 0;
	}

	per_proc_info[target_cpu].cpu_id = processor_info->cpu_id;
	per_proc_info[target_cpu].start_paddr = processor_info->start_paddr;

	if(per_proc_info[target_cpu].pf.Available & pfCanNap)
	  if(processor_info->supports_nap) 
		per_proc_info[target_cpu].pf.Available |= pfWillNap;

	if(processor_info->time_base_enable !=  (void(*)(cpu_id_t, boolean_t ))NULL)
		per_proc_info[target_cpu].time_base_enable = processor_info->time_base_enable;
	else
		per_proc_info[target_cpu].time_base_enable = (void(*)(cpu_id_t, boolean_t ))NULL;
	
	if(target_cpu == cpu_number()) 
		__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available));	/* Set live value */

	*processor = cpu_to_processor(target_cpu);
	*ipi_handler = cpu_signal_handler;

	return KERN_SUCCESS;
}

boolean_t
ml_enable_nap(int target_cpu, boolean_t nap_enabled)
{
    boolean_t prev_value = (per_proc_info[target_cpu].pf.Available & pfCanNap) && (per_proc_info[target_cpu].pf.Available & pfWillNap);
    
 	if(per_proc_info[target_cpu].pf.Available & pfCanNap) {				/* Can the processor nap? */
		if (nap_enabled) per_proc_info[target_cpu].pf.Available |= pfWillNap;	/* Is nap supported on this machine? */
		else per_proc_info[target_cpu].pf.Available &= ~pfWillNap;		/* Clear if not */
	}

	if(target_cpu == cpu_number()) 
		__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available));	/* Set live value */

    return (prev_value);
}

void
ml_init_max_cpus(unsigned long max_cpus)
{
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
	if (max_cpus_initialized != MAX_CPUS_SET) {
		if (max_cpus > 0 && max_cpus < NCPUS)
			machine_info.max_cpus = max_cpus;
		if (max_cpus_initialized == MAX_CPUS_WAIT)
			wakeup((event_t)&max_cpus_initialized);
		max_cpus_initialized = MAX_CPUS_SET;
	}
	(void) ml_set_interrupts_enabled(current_state);
}

int
ml_get_max_cpus(void)
{
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
	if (max_cpus_initialized != MAX_CPUS_SET) {
		max_cpus_initialized = MAX_CPUS_WAIT;
		assert_wait((event_t)&max_cpus_initialized, THREAD_UNINT);
		(void)thread_block(THREAD_CONTINUE_NULL);
	}
	(void) ml_set_interrupts_enabled(current_state);
	return(machine_info.max_cpus);
}

int
ml_get_current_cpus(void)
{
	return machine_info.avail_cpus;
}

void
ml_cpu_get_info(ml_cpu_info_t *cpu_info)
{
  if (cpu_info == 0) return;
  
  cpu_info->vector_unit = (per_proc_info[0].pf.Available & pfAltivec) != 0;
  cpu_info->cache_line_size = per_proc_info[0].pf.lineSize;
  cpu_info->l1_icache_size = per_proc_info[0].pf.l1iSize;
  cpu_info->l1_dcache_size = per_proc_info[0].pf.l1dSize;
  
  if (per_proc_info[0].pf.Available & pfL2) {
    cpu_info->l2_settings = per_proc_info[0].pf.l2cr;
    cpu_info->l2_cache_size = per_proc_info[0].pf.l2Size;
  } else {
    cpu_info->l2_settings = 0;
    cpu_info->l2_cache_size = 0xFFFFFFFF;
  }
  if (per_proc_info[0].pf.Available & pfL3) {
    cpu_info->l3_settings = per_proc_info[0].pf.l3cr;
    cpu_info->l3_cache_size = per_proc_info[0].pf.l3Size;
  } else {
    cpu_info->l3_settings = 0;
    cpu_info->l3_cache_size = 0xFFFFFFFF;
  }
}

#define l2em 0x80000000
#define l3em 0x80000000

extern int real_ncpus;

int
ml_enable_cache_level(int cache_level, int enable)
{
  int old_mode;
  unsigned long available, ccr;
  
  if (real_ncpus != 1) return -1;
  
  available = per_proc_info[0].pf.Available;
  
  if ((cache_level == 2) && (available & pfL2)) {
    ccr = per_proc_info[0].pf.l2cr;
    old_mode = (ccr & l2em) ? TRUE : FALSE;
    if (old_mode != enable) {
      if (enable) ccr = per_proc_info[0].pf.l2crOriginal;
      else ccr = 0;
      per_proc_info[0].pf.l2cr = ccr;
      cacheInit();
    }
    
    return old_mode;
  }
  
  if ((cache_level == 3) && (available & pfL3)) {
    ccr = per_proc_info[0].pf.l3cr;
    old_mode = (ccr & l3em) ? TRUE : FALSE;
    if (old_mode != enable) {
      if (enable) ccr = per_proc_info[0].pf.l3crOriginal;
      else ccr = 0;
      per_proc_info[0].pf.l3cr = ccr;
      cacheInit();
    }
    
    return old_mode;
  }
  
  return -1;
}

void
init_ast_check(processor_t processor)
{}
                
void
cause_ast_check(
	processor_t		processor)
{
	if (	processor != current_processor()								&&
	    	per_proc_info[processor->slot_num].interrupts_enabled == TRUE	)
		cpu_signal(processor->slot_num, SIGPast, NULL, NULL);
}
              
thread_t        
switch_to_shutdown_context(
	thread_t	thread,
	void		(*doshutdown)(processor_t),
	processor_t	processor)
{
	CreateShutdownCTX();   
	return((thread_t)(per_proc_info[cpu_number()].old_thread));
}

int
set_be_bit()
{
	
	int mycpu;
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);	/* Can't allow interruptions when mucking with per_proc flags */
	mycpu = cpu_number();
	per_proc_info[mycpu].cpu_flags |= traceBE;
	(void) ml_set_interrupts_enabled(current_state);
	return(1);
}

int
clr_be_bit()
{
	int mycpu;
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);	/* Can't allow interruptions when mucking with per_proc flags */
	mycpu = cpu_number();
	per_proc_info[mycpu].cpu_flags &= ~traceBE;
	(void) ml_set_interrupts_enabled(current_state);
	return(1);
}

int
be_tracing()
{
  int mycpu = cpu_number();
  return(per_proc_info[mycpu].cpu_flags & traceBE);
}
Commit	Line	Data
1c79356b A	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
43866e37	6	* Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
1c79356b	7	*
43866e37 A	8	* This file contains Original Code and/or Modifications of Original Code
	9	* as defined in and that are subject to the Apple Public Source License
	10	* Version 2.0 (the 'License'). You may not use this file except in
	11	* compliance with the License. Please obtain a copy of the License at
	12	* http://www.opensource.apple.com/apsl/ and read it before using this
	13	* file.
	14	*
	15	* The Original Code and all software distributed under the License are
	16	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
1c79356b A	17	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
1c79356b A	18	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
43866e37 A	19	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	20	* Please see the License for the specific language governing rights and
	21	* limitations under the License.
1c79356b A	22	*
	23	* @APPLE_LICENSE_HEADER_END@
	24	*/
	25	#include <ppc/machine_routines.h>
	26	#include <ppc/machine_cpu.h>
	27	#include <ppc/exception.h>
	28	#include <ppc/misc_protos.h>
	29	#include <ppc/Firmware.h>
	30	#include <vm/vm_page.h>
	31	#include <ppc/pmap.h>
	32	#include <ppc/proc_reg.h>
	33	#include <kern/processor.h>
	34
43866e37 A	35	unsigned int max_cpus_initialized = 0;
	36
	37	#define MAX_CPUS_SET 0x1
	38	#define MAX_CPUS_WAIT 0x2
	39
1c79356b	40	boolean_t get_interrupts_enabled(void);
1c79356b A	41
	42	/* Map memory map IO space */
	43	vm_offset_t
	44	ml_io_map(
	45	vm_offset_t phys_addr,
	46	vm_size_t size)
	47	{
	48	return(io_map(phys_addr,size));
	49	}
	50
	51	/* static memory allocation */
	52	vm_offset_t
	53	ml_static_malloc(
	54	vm_size_t size)
	55	{
	56	extern vm_offset_t static_memory_end;
	57	extern boolean_t pmap_initialized;
	58	vm_offset_t vaddr;
	59
	60	if (pmap_initialized)
	61	return((vm_offset_t)NULL);
	62	else {
	63	vaddr = static_memory_end;
de355530	64	static_memory_end = round_page(vaddr+size);
1c79356b A	65	return(vaddr);
	66	}
	67	}
	68
	69	vm_offset_t
	70	ml_static_ptovirt(
	71	vm_offset_t paddr)
	72	{
	73	extern vm_offset_t static_memory_end;
	74	vm_offset_t vaddr;
	75
	76	/* Static memory is map V=R */
	77	vaddr = paddr;
	78	if ( (vaddr < static_memory_end) && (pmap_extract(kernel_pmap, vaddr)==paddr) )
	79	return(vaddr);
	80	else
	81	return((vm_offset_t)NULL);
	82	}
	83
	84	void
	85	ml_static_mfree(
	86	vm_offset_t vaddr,
	87	vm_size_t size)
	88	{
	89	vm_offset_t paddr_cur, vaddr_cur;
	90
de355530 A	91	for (vaddr_cur = round_page(vaddr);
de355530 A	92	vaddr_cur < trunc_page(vaddr+size);
1c79356b A	93	vaddr_cur += PAGE_SIZE) {
	94	paddr_cur = pmap_extract(kernel_pmap, vaddr_cur);
	95	if (paddr_cur != (vm_offset_t)NULL) {
	96	vm_page_wire_count--;
de355530 A	97	pmap_remove(kernel_pmap, vaddr_cur, vaddr_cur+PAGE_SIZE);
de355530 A	98	vm_page_create(paddr_cur,paddr_cur+PAGE_SIZE);
1c79356b A	99	}
	100	}
	101	}
	102
	103	/* virtual to physical on wired pages */
	104	vm_offset_t ml_vtophys(
	105	vm_offset_t vaddr)
	106	{
	107	return(pmap_extract(kernel_pmap, vaddr));
	108	}
	109
	110	/* Initialize Interrupt Handler */
	111	void ml_install_interrupt_handler(
	112	void *nub,
	113	int source,
	114	void *target,
	115	IOInterruptHandler handler,
	116	void *refCon)
	117	{
	118	int current_cpu;
	119	boolean_t current_state;
	120
	121	current_cpu = cpu_number();
	122	current_state = ml_get_interrupts_enabled();
	123
	124	per_proc_info[current_cpu].interrupt_nub = nub;
	125	per_proc_info[current_cpu].interrupt_source = source;
	126	per_proc_info[current_cpu].interrupt_target = target;
	127	per_proc_info[current_cpu].interrupt_handler = handler;
	128	per_proc_info[current_cpu].interrupt_refCon = refCon;
	129
0b4e3aa0	130	per_proc_info[current_cpu].interrupts_enabled = TRUE;
1c79356b	131	(void) ml_set_interrupts_enabled(current_state);
9bccf70c A	132
9bccf70c A	133	initialize_screen(0, kPEAcquireScreen);
1c79356b A	134	}
	135
	136	/* Initialize Interrupts */
	137	void ml_init_interrupt(void)
	138	{
	139	int current_cpu;
	140	boolean_t current_state;
	141
	142	current_state = ml_get_interrupts_enabled();
	143
	144	current_cpu = cpu_number();
0b4e3aa0	145	per_proc_info[current_cpu].interrupts_enabled = TRUE;
1c79356b A	146	(void) ml_set_interrupts_enabled(current_state);
	147	}
	148
de355530 A	149	boolean_t fake_get_interrupts_enabled(void)
	150	{
	151	/*
	152	* The scheduler is not active on this cpu. There is no need to disable
	153	* preemption. The current thread wont be dispatched on anhother cpu.
	154	*/
	155	return((per_proc_info[cpu_number()].cpu_flags & turnEEon) != 0);
	156	}
	157
	158	boolean_t fake_set_interrupts_enabled(boolean_t enable)
	159	{
	160	boolean_t interrupt_state_prev;
	161
	162	/*
	163	* The scheduler is not active on this cpu. There is no need to disable
	164	* preemption. The current thread wont be dispatched on anhother cpu.
	165	*/
	166	interrupt_state_prev =
	167	(per_proc_info[cpu_number()].cpu_flags & turnEEon) != 0;
	168	if (interrupt_state_prev != enable)
	169	per_proc_info[cpu_number()].cpu_flags ^= turnEEon;
	170	return(interrupt_state_prev);
	171	}
	172
1c79356b A	173	/* Get Interrupts Enabled */
1c79356b A	174	boolean_t ml_get_interrupts_enabled(void)
de355530 A	175	{
	176	if (per_proc_info[cpu_number()].interrupts_enabled == TRUE)
	177	return(get_interrupts_enabled());
	178	else
	179	return(fake_get_interrupts_enabled());
	180	}
	181
	182	boolean_t get_interrupts_enabled(void)
1c79356b A	183	{
	184	return((mfmsr() & MASK(MSR_EE)) != 0);
	185	}
	186
1c79356b A	187	/* Check if running at interrupt context */
	188	boolean_t ml_at_interrupt_context(void)
	189	{
0b4e3aa0 A	190	boolean_t ret;
	191	boolean_t current_state;
	192
	193	current_state = ml_set_interrupts_enabled(FALSE);
	194	ret = (per_proc_info[cpu_number()].istackptr == 0);
	195	ml_set_interrupts_enabled(current_state);
	196	return(ret);
1c79356b A	197	}
	198
	199	/* Generate a fake interrupt */
	200	void ml_cause_interrupt(void)
	201	{
	202	CreateFakeIO();
	203	}
	204
9bccf70c	205	void ml_thread_policy(
d52fe63f A	206	thread_t thread,
	207	unsigned policy_id,
	208	unsigned policy_info)
	209	{
	210	if ((policy_id == MACHINE_GROUP) &&
9bccf70c A	211	((per_proc_info[0].pf.Available) & pfSMPcap))
	212	thread_bind(thread, master_processor);
	213
	214	if (policy_info & MACHINE_NETWORK_WORKLOOP) {
	215	spl_t s = splsched();
	216
	217	thread_lock(thread);
	218
	219	thread->sched_mode \|= TH_MODE_FORCEDPREEMPT;
	220	set_priority(thread, thread->priority + 1);
	221
	222	thread_unlock(thread);
	223	splx(s);
	224	}
d52fe63f A	225	}
d52fe63f A	226
1c79356b A	227	void machine_idle(void)
1c79356b A	228	{
0b4e3aa0	229	if (per_proc_info[cpu_number()].interrupts_enabled == TRUE) {
1c79356b A	230	int cur_decr;
	231
	232	machine_idle_ppc();
	233
	234	/*
	235	* protect against a lost decrementer trap
	236	* if the current decrementer value is negative
	237	* by more than 10 ticks, re-arm it since it's
	238	* unlikely to fire at this point... a hardware
	239	* interrupt got us out of machine_idle and may
	240	* also be contributing to this state
	241	*/
	242	cur_decr = isync_mfdec();
	243
	244	if (cur_decr < -10) {
	245	mtdec(1);
	246	}
	247	}
	248	}
	249
	250	void
	251	machine_signal_idle(
	252	processor_t processor)
	253	{
	254	(void)cpu_signal(processor->slot_num, SIGPwake, 0, 0);
	255	}
	256
	257	kern_return_t
	258	ml_processor_register(
	259	ml_processor_info_t *processor_info,
	260	processor_t *processor,
	261	ipi_handler_t *ipi_handler)
	262	{
	263	kern_return_t ret;
de355530	264	int target_cpu;
1c79356b A	265
	266	if (processor_info->boot_cpu == FALSE) {
	267	if (cpu_register(&target_cpu) != KERN_SUCCESS)
	268	return KERN_FAILURE;
	269	} else {
	270	/* boot_cpu is always 0 */
de355530	271	target_cpu= 0;
1c79356b A	272	}
	273
	274	per_proc_info[target_cpu].cpu_id = processor_info->cpu_id;
	275	per_proc_info[target_cpu].start_paddr = processor_info->start_paddr;
	276
	277	if(per_proc_info[target_cpu].pf.Available & pfCanNap)
de355530	278	if(processor_info->supports_nap)
1c79356b A	279	per_proc_info[target_cpu].pf.Available \|= pfWillNap;
	280
	281	if(processor_info->time_base_enable != (void(*)(cpu_id_t, boolean_t ))NULL)
	282	per_proc_info[target_cpu].time_base_enable = processor_info->time_base_enable;
	283	else
	284	per_proc_info[target_cpu].time_base_enable = (void(*)(cpu_id_t, boolean_t ))NULL;
	285
	286	if(target_cpu == cpu_number())
	287	__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available)); /* Set live value */
	288
	289	*processor = cpu_to_processor(target_cpu);
	290	*ipi_handler = cpu_signal_handler;
	291
	292	return KERN_SUCCESS;
	293	}
	294
	295	boolean_t
	296	ml_enable_nap(int target_cpu, boolean_t nap_enabled)
	297	{
	298	boolean_t prev_value = (per_proc_info[target_cpu].pf.Available & pfCanNap) && (per_proc_info[target_cpu].pf.Available & pfWillNap);
	299
	300	if(per_proc_info[target_cpu].pf.Available & pfCanNap) { /* Can the processor nap? */
	301	if (nap_enabled) per_proc_info[target_cpu].pf.Available \|= pfWillNap; /* Is nap supported on this machine? */
	302	else per_proc_info[target_cpu].pf.Available &= ~pfWillNap; /* Clear if not */
	303	}
	304
	305	if(target_cpu == cpu_number())
	306	__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available)); /* Set live value */
1c79356b	307
de355530	308	return (prev_value);
d7e50217 A	309	}
	310
	311	void
43866e37 A	312	ml_init_max_cpus(unsigned long max_cpus)
	313	{
	314	boolean_t current_state;
	315
	316	current_state = ml_set_interrupts_enabled(FALSE);
	317	if (max_cpus_initialized != MAX_CPUS_SET) {
	318	if (max_cpus > 0 && max_cpus < NCPUS)
	319	machine_info.max_cpus = max_cpus;
	320	if (max_cpus_initialized == MAX_CPUS_WAIT)
	321	wakeup((event_t)&max_cpus_initialized);
	322	max_cpus_initialized = MAX_CPUS_SET;
	323	}
	324	(void) ml_set_interrupts_enabled(current_state);
	325	}
	326
	327	int
	328	ml_get_max_cpus(void)
	329	{
	330	boolean_t current_state;
	331
	332	current_state = ml_set_interrupts_enabled(FALSE);
	333	if (max_cpus_initialized != MAX_CPUS_SET) {
	334	max_cpus_initialized = MAX_CPUS_WAIT;
	335	assert_wait((event_t)&max_cpus_initialized, THREAD_UNINT);
	336	(void)thread_block(THREAD_CONTINUE_NULL);
	337	}
	338	(void) ml_set_interrupts_enabled(current_state);
	339	return(machine_info.max_cpus);
	340	}
	341
	342	int
	343	ml_get_current_cpus(void)
	344	{
	345	return machine_info.avail_cpus;
	346	}
	347
	348	void
	349	ml_cpu_get_info(ml_cpu_info_t *cpu_info)
1c79356b A	350	{
	351	if (cpu_info == 0) return;
	352
	353	cpu_info->vector_unit = (per_proc_info[0].pf.Available & pfAltivec) != 0;
	354	cpu_info->cache_line_size = per_proc_info[0].pf.lineSize;
	355	cpu_info->l1_icache_size = per_proc_info[0].pf.l1iSize;
	356	cpu_info->l1_dcache_size = per_proc_info[0].pf.l1dSize;
	357
	358	if (per_proc_info[0].pf.Available & pfL2) {
	359	cpu_info->l2_settings = per_proc_info[0].pf.l2cr;
	360	cpu_info->l2_cache_size = per_proc_info[0].pf.l2Size;
	361	} else {
	362	cpu_info->l2_settings = 0;
	363	cpu_info->l2_cache_size = 0xFFFFFFFF;
	364	}
	365	if (per_proc_info[0].pf.Available & pfL3) {
	366	cpu_info->l3_settings = per_proc_info[0].pf.l3cr;
	367	cpu_info->l3_cache_size = per_proc_info[0].pf.l3Size;
	368	} else {
	369	cpu_info->l3_settings = 0;
	370	cpu_info->l3_cache_size = 0xFFFFFFFF;
	371	}
	372	}
	373
d52fe63f A	374	#define l2em 0x80000000
	375	#define l3em 0x80000000
	376
	377	extern int real_ncpus;
	378
	379	int
	380	ml_enable_cache_level(int cache_level, int enable)
	381	{
	382	int old_mode;
	383	unsigned long available, ccr;
	384
	385	if (real_ncpus != 1) return -1;
	386
	387	available = per_proc_info[0].pf.Available;
	388
	389	if ((cache_level == 2) && (available & pfL2)) {
	390	ccr = per_proc_info[0].pf.l2cr;
	391	old_mode = (ccr & l2em) ? TRUE : FALSE;
	392	if (old_mode != enable) {
	393	if (enable) ccr = per_proc_info[0].pf.l2crOriginal;
	394	else ccr = 0;
	395	per_proc_info[0].pf.l2cr = ccr;
	396	cacheInit();
	397	}
	398
	399	return old_mode;
	400	}
	401
	402	if ((cache_level == 3) && (available & pfL3)) {
	403	ccr = per_proc_info[0].pf.l3cr;
	404	old_mode = (ccr & l3em) ? TRUE : FALSE;
	405	if (old_mode != enable) {
	406	if (enable) ccr = per_proc_info[0].pf.l3crOriginal;
	407	else ccr = 0;
	408	per_proc_info[0].pf.l3cr = ccr;
	409	cacheInit();
	410	}
	411
	412	return old_mode;
	413	}
	414
	415	return -1;
	416	}
	417
1c79356b A	418	void
	419	init_ast_check(processor_t processor)
	420	{}
	421
	422	void
9bccf70c A	423	cause_ast_check(
9bccf70c A	424	processor_t processor)
1c79356b	425	{
9bccf70c A	426	if ( processor != current_processor() &&
9bccf70c A	427	per_proc_info[processor->slot_num].interrupts_enabled == TRUE )
1c79356b A	428	cpu_signal(processor->slot_num, SIGPast, NULL, NULL);
	429	}
	430
	431	thread_t
	432	switch_to_shutdown_context(
	433	thread_t thread,
	434	void (*doshutdown)(processor_t),
	435	processor_t processor)
	436	{
1c79356b	437	CreateShutdownCTX();
1c79356b A	438	return((thread_t)(per_proc_info[cpu_number()].old_thread));
	439	}
	440
	441	int
	442	set_be_bit()
	443	{
	444
	445	int mycpu;
	446	boolean_t current_state;
	447
	448	current_state = ml_set_interrupts_enabled(FALSE); /* Can't allow interruptions when mucking with per_proc flags */
	449	mycpu = cpu_number();
	450	per_proc_info[mycpu].cpu_flags \|= traceBE;
	451	(void) ml_set_interrupts_enabled(current_state);
	452	return(1);
	453	}
	454
	455	int
	456	clr_be_bit()
	457	{
	458	int mycpu;
	459	boolean_t current_state;
	460
	461	current_state = ml_set_interrupts_enabled(FALSE); /* Can't allow interruptions when mucking with per_proc flags */
	462	mycpu = cpu_number();
	463	per_proc_info[mycpu].cpu_flags &= ~traceBE;
	464	(void) ml_set_interrupts_enabled(current_state);
	465	return(1);
	466	}
	467
	468	int
	469	be_tracing()
	470	{
	471	int mycpu = cpu_number();
	472	return(per_proc_info[mycpu].cpu_flags & traceBE);
	473	}
0b4e3aa0	474