osfmk/i386/cpuid.c

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 /*
  23  * @OSF_COPYRIGHT@
  24  */
  25
  26 #include <pexpert/pexpert.h>
  27
  28 #include "cpuid.h"
  29
  30 #define min(a,b) ((a) < (b) ? (a) : (b))
  31
  32 /*
  33  * CPU identification routines.
  34  *
  35  * Note that this code assumes a processor that supports the
  36  * 'cpuid' instruction.
  37  */
  38
  39 static unsigned int     cpuid_maxcpuid;
  40
  41 static i386_cpu_info_t  cpuid_cpu_info;
  42
  43 uint32_t                cpuid_feature;          /* XXX obsolescent for compat */
  44
  45 /*
  46  * We only identify Intel CPUs here.  Adding support
  47  * for others would be straightforward.
  48  */
  49 static void     set_cpu_generic(i386_cpu_info_t *);
  50 static void     set_cpu_intel(i386_cpu_info_t *);
  51 static void     set_cpu_amd(i386_cpu_info_t *);
  52 static void     set_cpu_nsc(i386_cpu_info_t *);
  53 static void     set_cpu_unknown(i386_cpu_info_t *);
  54
  55 struct {
  56         const char      *vendor;
  57         void            (* func)(i386_cpu_info_t *);
  58 } cpu_vendors[] = {
  59         {CPUID_VID_INTEL,       set_cpu_intel},
  60         {CPUID_VID_AMD,         set_cpu_amd},
  61         {CPUID_VID_NSC,         set_cpu_nsc},
  62         {0,                     set_cpu_unknown}
  63 };
  64
  65 void
  66 cpuid_get_info(i386_cpu_info_t *info_p)
  67 {
  68         uint32_t        cpuid_result[4];
  69         int             i;
  70
  71         bzero((void *)info_p, sizeof(i386_cpu_info_t));
  72
  73         /* do cpuid 0 to get vendor */
  74         do_cpuid(0, cpuid_result);
  75         cpuid_maxcpuid = cpuid_result[0];
  76         bcopy((char *)&cpuid_result[1], &info_p->cpuid_vendor[0], 4); /* ugh */
  77         bcopy((char *)&cpuid_result[2], &info_p->cpuid_vendor[8], 4);
  78         bcopy((char *)&cpuid_result[3], &info_p->cpuid_vendor[4], 4);
  79         info_p->cpuid_vendor[12] = 0;
  80
  81         /* look up vendor */
  82         for (i = 0; ; i++) {
  83                 if ((cpu_vendors[i].vendor == 0) ||
  84                     (!strcmp(cpu_vendors[i].vendor, info_p->cpuid_vendor))) {
  85                         cpu_vendors[i].func(info_p);
  86                         break;
  87                 }
  88         }
  89 }
  90
  91 /*
  92  * Cache descriptor table. Each row has the form:
  93  *         (descriptor_value,           cache,  size,           linesize,
  94  *                              description)
  95  * Note: the CACHE_DESC macro does not expand description text in the kernel.
  96  */
  97 static cpuid_cache_desc_t cpuid_cache_desc_tab[] = {
  98 CACHE_DESC(CPUID_CACHE_ITLB_4K,         Lnone,  0,              0, \
  99         "Instruction TLB, 4K, pages 4-way set associative, 64 entries"),
 100 CACHE_DESC(CPUID_CACHE_ITLB_4M,         Lnone,  0,              0, \
 101         "Instruction TLB, 4M, pages 4-way set associative, 2 entries"),
 102 CACHE_DESC(CPUID_CACHE_DTLB_4K,         Lnone,  0,              0, \
 103         "Data TLB, 4K pages, 4-way set associative, 64 entries"),
 104 CACHE_DESC(CPUID_CACHE_DTLB_4M,         Lnone,  0,              0, \
 105         "Data TLB, 4M pages, 4-way set associative, 8 entries"),
 106 CACHE_DESC(CPUID_CACHE_ITLB_64,         Lnone,  0,              0, \
 107         "Instruction TLB, 4K and 2M or 4M pages, 64 entries"),
 108 CACHE_DESC(CPUID_CACHE_ITLB_128,        Lnone,  0,              0, \
 109         "Instruction TLB, 4K and 2M or 4M pages, 128 entries"),
 110 CACHE_DESC(CPUID_CACHE_ITLB_256,        Lnone,  0,              0, \
 111         "Instruction TLB, 4K and 2M or 4M pages, 256 entries"),
 112 CACHE_DESC(CPUID_CACHE_DTLB_64,         Lnone,  0,              0, \
 113         "Data TLB, 4K and 4M pages, 64 entries"),
 114 CACHE_DESC(CPUID_CACHE_DTLB_128,        Lnone,  0,              0, \
 115         "Data TLB, 4K and 4M pages, 128 entries"),
 116 CACHE_DESC(CPUID_CACHE_DTLB_256,        Lnone,  0,              0, \
 117         "Data TLB, 4K and 4M pages, 256 entries"),
 118 CACHE_DESC(CPUID_CACHE_ITLB_128_4,      Lnone,  0,              0, \
 119         "Instruction TLB, 4K pages, 4-way set associative, 128 entries"),
 120 CACHE_DESC(CPUID_CACHE_DTLB_128_4,      Lnone,  0,              0, \
 121         "Data TLB, 4K pages, 4-way set associative, 128 entries"),
 122 CACHE_DESC(CPUID_CACHE_ICACHE_8K,       L1I,    8*1024,         32, \
 123         "Instruction L1 cache, 8K, 4-way set associative, 32byte line size"),
 124 CACHE_DESC(CPUID_CACHE_DCACHE_8K,       L1D,    8*1024,         32, \
 125         "Data L1 cache, 8K, 2-way set associative, 32byte line size"),
 126 CACHE_DESC(CPUID_CACHE_ICACHE_16K,      L1I,    16*1024,         32, \
 127         "Instruction L1 cache, 16K, 4-way set associative, 32byte line size"),
 128 CACHE_DESC(CPUID_CACHE_DCACHE_16K,      L1D,    16*1024,        32, \
 129         "Data L1 cache, 16K, 4-way set associative, 32byte line size"),
 130 CACHE_DESC(CPUID_CACHE_DCACHE_8K_64,    L1D,    8*1024,         64, \
 131         "Data L1 cache, 8K, 4-way set associative, 64byte line size"),
 132 CACHE_DESC(CPUID_CACHE_DCACHE_16K_64,   L1D,    16*1024,        64, \
 133         "Data L1 cache, 16K, 4-way set associative, 64byte line size"),
 134 CACHE_DESC(CPUID_CACHE_DCACHE_32K_64,   L1D,    32*1024,        64, \
 135         "Data L1 cache, 32K, 4-way set associative, 64byte line size"),
 136 CACHE_DESC(CPUID_CACHE_DCACHE_32K,      L1D,    32*1024,        64, \
 137         "Data L1 cache, 32K, 8-way set assocative, 64byte line size"),
 138 CACHE_DESC(CPUID_CACHE_ICACHE_32K,      L1I,    32*1024,        64, \
 139         "Instruction L1 cache, 32K, 8-way set associative, 64byte line size"),
 140 CACHE_DESC(CPUID_CACHE_DCACHE_16K_8,    L1D,    16*1024,        64, \
 141         "Data L1 cache, 16K, 8-way set associative, 64byte line size"),
 142 CACHE_DESC(CPUID_CACHE_TRACE_12K,       L1I,    12*1024,        64, \
 143         "Trace cache, 12K-uop, 8-way set associative"),
 144 CACHE_DESC(CPUID_CACHE_TRACE_16K,       L1I,    16*1024,        64, \
 145         "Trace cache, 16K-uop, 8-way set associative"),
 146 CACHE_DESC(CPUID_CACHE_TRACE_32K,       L1I,    32*1024,        64, \
 147         "Trace cache, 32K-uop, 8-way set associative"),
 148 CACHE_DESC(CPUID_CACHE_UCACHE_128K,     L2U,    128*1024,       32, \
 149         "Unified L2 cache, 128K, 4-way set associative, 32byte line size"),
 150 CACHE_DESC(CPUID_CACHE_UCACHE_256K,     L2U,    128*1024,       32, \
 151         "Unified L2 cache, 256K, 4-way set associative, 32byte line size"),
 152 CACHE_DESC(CPUID_CACHE_UCACHE_512K,     L2U,    512*1024,       32, \
 153         "Unified L2 cache, 512K, 4-way set associative, 32byte line size"),
 154 CACHE_DESC(CPUID_CACHE_UCACHE_1M,       L2U,    1*1024*1024,    32, \
 155         "Unified L2 cache, 1M, 4-way set associative, 32byte line size"),
 156 CACHE_DESC(CPUID_CACHE_UCACHE_2M,       L2U,    2*1024*1024,    32, \
 157         "Unified L2 cache, 2M, 4-way set associative, 32byte line size"),
 158 CACHE_DESC(CPUID_CACHE_UCACHE_128K_64,  L2U,    128*1024,       64, \
 159         "Unified L2 cache, 128K, 8-way set associative, 64byte line size"),
 160 CACHE_DESC(CPUID_CACHE_UCACHE_256K_64,  L2U,    256*1024,       64, \
 161         "Unified L2 cache, 256K, 8-way set associative, 64byte line size"),
 162 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64,  L2U,    512*1024,       64, \
 163         "Unified L2 cache, 512K, 8-way set associative, 64byte line size"),
 164 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64,    L2U,    1*1024*1024,    64, \
 165         "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
 166 CACHE_DESC(CPUID_CACHE_UCACHE_256K_32,  L2U,    256*1024,       32, \
 167         "Unified L2 cache, 256K, 8-way set associative, 32byte line size"),
 168 CACHE_DESC(CPUID_CACHE_UCACHE_512K_32,  L2U,    512*1024,       32, \
 169         "Unified L2 cache, 512K, 8-way set associative, 32byte line size"),
 170 CACHE_DESC(CPUID_CACHE_UCACHE_1M_32,    L2U,    1*1024*1024,    32, \
 171         "Unified L2 cache, 1M, 8-way set associative, 32byte line size"),
 172 CACHE_DESC(CPUID_CACHE_UCACHE_2M_32,    L2U,    2*1024*1024,    32, \
 173         "Unified L2 cache, 2M, 8-way set associative, 32byte line size"),
 174 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_4,  L2U,    1*1024*1024,    64, \
 175         "Unified L2 cache, 1M, 4-way set associative, 64byte line size"),
 176 CACHE_DESC(CPUID_CACHE_UCACHE_2M_64,    L2U,    2*1024*1024,    64, \
 177         "Unified L2 cache, 2M, 8-way set associative, 64byte line size"),
 178 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_2,L2U,    512*1024,       64, \
 179         "Unified L2 cache, 512K, 2-way set associative, 64byte line size"),
 180 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_4,L2U,    512*1024,       64, \
 181         "Unified L2 cache, 512K, 4-way set associative, 64byte line size"),
 182 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_8,  L2U,    1*1024*1024,    64, \
 183         "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
 184 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S4,  L2U,    128*1024,       64, \
 185         "Unified L2 sectored cache, 128K, 4-way set associative, 64byte line size"),
 186 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S2,  L2U,    128*1024,       64, \
 187         "Unified L2 sectored cache, 128K, 2-way set associative, 64byte line size"),
 188 CACHE_DESC(CPUID_CACHE_UCACHE_256K_S4,  L2U,    256*1024,       64, \
 189         "Unified L2 sectored cache, 256K, 4-way set associative, 64byte line size"),
 190 CACHE_DESC(CPUID_CACHE_L3CACHE_512K,    L3U,    512*1024,       64, \
 191         "Unified L3 cache, 512K, 4-way set associative, 64byte line size"),
 192 CACHE_DESC(CPUID_CACHE_L3CACHE_1M,      L3U,    1*1024*1024,    64, \
 193         "Unified L3 cache, 1M, 8-way set associative, 64byte line size"),
 194 CACHE_DESC(CPUID_CACHE_L3CACHE_2M,      L3U,    2*1024*1024,    64, \
 195         "Unified L3 cache, 2M, 8-way set associative, 64byte line size"),
 196 CACHE_DESC(CPUID_CACHE_L3CACHE_4M,      L3U,    4*1024*1024,    64, \
 197         "Unified L3 cache, 4M, 8-way set associative, 64byte line size"),
 198 CACHE_DESC(CPUID_CACHE_PREFETCH_64,     Lnone,  0,              0,  \
 199         "64-Byte Prefetching"),
 200 CACHE_DESC(CPUID_CACHE_PREFETCH_128,    Lnone,  0,              0,  \
 201         "128-Byte Prefetching"),
 202 CACHE_DESC(CPUID_CACHE_NOCACHE, Lnone, 0, 0, \
 203         "No L2 cache or, if valid L2 cache, no L3 cache"),
 204 CACHE_DESC(CPUID_CACHE_NULL, Lnone, 0, 0, \
 205         (char *)0),
 206 };
 207
 208 static const char * get_intel_model_string( i386_cpu_info_t * info_p )
 209 {
 210     /* check for brand id */
 211     switch(info_p->cpuid_brand) {
 212         case CPUID_BRAND_UNSUPPORTED:
 213             /* brand ID not supported; use alternate method. */
 214             switch(info_p->cpuid_family) {
 215                 case CPUID_FAMILY_486:
 216                     return "Intel 486";
 217                 case CPUID_FAMILY_586:
 218                     return "Intel Pentium";
 219                 case CPUID_FAMILY_686:
 220                     switch(info_p->cpuid_model) {
 221                         case CPUID_MODEL_P6:
 222                             return "Intel Pentium Pro";
 223                         case CPUID_MODEL_PII:
 224                             return "Intel Pentium II";
 225                         case CPUID_MODEL_P65:
 226                         case CPUID_MODEL_P66:
 227                             return "Intel Celeron";
 228                         case CPUID_MODEL_P67:
 229                         case CPUID_MODEL_P68:
 230                         case CPUID_MODEL_P6A:
 231                         case CPUID_MODEL_P6B:
 232                             return "Intel Pentium III";
 233                         case CPUID_MODEL_PM9:
 234                         case CPUID_MODEL_PMD:
 235                             return "Intel Pentium M";
 236                         default:
 237                             return "Unknown Intel P6 Family";
 238                     }
 239                 case CPUID_FAMILY_ITANIUM:
 240                     return "Intel Itanium";
 241                 case CPUID_FAMILY_EXTENDED:
 242                     switch (info_p->cpuid_extfamily) {
 243                         case CPUID_EXTFAMILY_PENTIUM4:
 244                             return "Intel Pentium 4";
 245                         case CPUID_EXTFAMILY_ITANIUM2:
 246                             return "Intel Itanium 2";
 247                     }
 248                 default:
 249                     return "Unknown Intel Family";
 250             }
 251             break;
 252         case CPUID_BRAND_CELERON_1:
 253         case CPUID_BRAND_CELERON_A:
 254         case CPUID_BRAND_CELERON_14:
 255             return "Intel Celeron";
 256         case CPUID_BRAND_PENTIUM_III_2:
 257         case CPUID_BRAND_PENTIUM_III_4:
 258             return "Pentium III";
 259         case CPUID_BRAND_PIII_XEON:
 260             if (info_p->cpuid_signature == 0x6B1)
 261                 return "Intel Celeron";
 262             else
 263                 return "Intel Pentium III Xeon";
 264         case CPUID_BRAND_PENTIUM_III_M:
 265             return "Mobile Intel Pentium III-M";
 266         case CPUID_BRAND_M_CELERON_7:
 267         case CPUID_BRAND_M_CELERON_F:
 268         case CPUID_BRAND_M_CELERON_13:
 269         case CPUID_BRAND_M_CELERON_17:
 270             return "Mobile Intel Celeron";
 271         case CPUID_BRAND_PENTIUM4_8:
 272         case CPUID_BRAND_PENTIUM4_9:
 273             return "Intel Pentium 4";
 274         case CPUID_BRAND_XEON:
 275             return "Intel Xeon";
 276         case CPUID_BRAND_XEON_MP:
 277             return "Intel Xeon MP";
 278         case CPUID_BRAND_PENTIUM4_M:
 279             if (info_p->cpuid_signature == 0xF13)
 280                 return "Intel Xeon";
 281             else
 282                 return "Mobile Intel Pentium 4";
 283         case CPUID_BRAND_CELERON_M:
 284             return "Intel Celeron M";
 285         case CPUID_BRAND_PENTIUM_M:
 286             return "Intel Pentium M";
 287         case CPUID_BRAND_MOBILE_15:
 288         case CPUID_BRAND_MOBILE_17:
 289             return "Mobile Intel";
 290     }
 291
 292     return "Unknown Intel";
 293 }
 294
 295 static void set_intel_cache_info( i386_cpu_info_t * info_p )
 296 {
 297         uint32_t        cpuid_result[4];
 298         uint32_t        l1d_cache_linesize = 0;
 299         unsigned int    i;
 300         unsigned int    j;
 301
 302         /* get processor cache descriptor info */
 303         do_cpuid(2, cpuid_result);
 304         for (j = 0; j < 4; j++) {
 305                 if ((cpuid_result[j] >> 31) == 1)       /* bit31 is validity */
 306                         continue;
 307                 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j];
 308         }
 309         /* first byte gives number of cpuid calls to get all descriptors */
 310         for (i = 1; i < info_p->cache_info[0]; i++) {
 311                 if (i*16 > sizeof(info_p->cache_info))
 312                         break;
 313                 do_cpuid(2, cpuid_result);
 314                 for (j = 0; j < 4; j++) {
 315                         if ((cpuid_result[j] >> 31) == 1)
 316                                 continue;
 317                         ((uint32_t *) info_p->cache_info)[4*i+j] =
 318                                 cpuid_result[j];
 319                 }
 320         }
 321
 322         /* decode the descriptors looking for L1/L2/L3 size info */
 323         for (i = 1; i < sizeof(info_p->cache_info); i++) {
 324                 cpuid_cache_desc_t      *descp;
 325                 uint8_t                 desc = info_p->cache_info[i];
 326
 327                 if (desc == CPUID_CACHE_NULL)
 328                         continue;
 329                 for (descp = cpuid_cache_desc_tab;
 330                         descp->value != CPUID_CACHE_NULL; descp++) {
 331                         if (descp->value != desc)
 332                                 continue;
 333                         info_p->cache_size[descp->type] = descp->size;
 334                         if (descp->type == L2U)
 335                                 info_p->cache_linesize = descp->linesize;
 336                         if (descp->type == L1D)
 337                                 l1d_cache_linesize = descp->linesize;
 338                         break;
 339                 }
 340         }
 341         /* For P-IIIs, L2 could be 256k or 512k but we can't tell */
 342         if (info_p->cache_size[L2U] == 0 &&
 343             info_p->cpuid_family == 0x6 && info_p->cpuid_model == 0xb) {
 344                 info_p->cache_size[L2U] = 256*1024;
 345                 info_p->cache_linesize = 32;
 346         }
 347         /* If we have no L2 cache, use the L1 data cache line size */
 348         if (info_p->cache_size[L2U] == 0)
 349             info_p->cache_linesize = l1d_cache_linesize;
 350 }
 351
 352 static void set_cpu_intel( i386_cpu_info_t * info_p )
 353 {
 354     set_cpu_generic(info_p);
 355     set_intel_cache_info(info_p);
 356     info_p->cpuid_model_string = get_intel_model_string(info_p);
 357 }
 358
 359 static const char * get_amd_model_string( i386_cpu_info_t * info_p )
 360 {
 361     switch (info_p->cpuid_family)
 362     {
 363         case CPUID_FAMILY_486:
 364             switch (info_p->cpuid_model) {
 365                 case CPUID_MODEL_AM486_DX:
 366                 case CPUID_MODEL_AM486_DX2:
 367                 case CPUID_MODEL_AM486_DX2WB:
 368                 case CPUID_MODEL_AM486_DX4:
 369                 case CPUID_MODEL_AM486_DX4WB:
 370                     return "Am486";
 371                 case CPUID_MODEL_AM486_5X86:
 372                 case CPUID_MODEL_AM486_5X86WB:
 373                     return "Am5x86";
 374             }
 375             break;
 376         case CPUID_FAMILY_586:
 377             switch (info_p->cpuid_model) {
 378                 case CPUID_MODEL_K5M0:
 379                 case CPUID_MODEL_K5M1:
 380                 case CPUID_MODEL_K5M2:
 381                 case CPUID_MODEL_K5M3:
 382                     return "AMD-K5";
 383                 case CPUID_MODEL_K6M6:
 384                 case CPUID_MODEL_K6M7:
 385                     return "AMD-K6";
 386                 case CPUID_MODEL_K6_2:
 387                     return "AMD-K6-2";
 388                 case CPUID_MODEL_K6_III:
 389                     return "AMD-K6-III";
 390             }
 391             break;
 392         case CPUID_FAMILY_686:
 393             switch (info_p->cpuid_model) {
 394                 case CPUID_MODEL_ATHLON_M1:
 395                 case CPUID_MODEL_ATHLON_M2:
 396                 case CPUID_MODEL_ATHLON_M4:
 397                 case CPUID_MODEL_ATHLON_M6:
 398                 case CPUID_MODEL_ATHLON_M8:
 399                 case CPUID_MODEL_ATHLON_M10:
 400                     return "AMD Athlon";
 401                 case CPUID_MODEL_DURON_M3:
 402                 case CPUID_MODEL_DURON_M7:
 403                     return "AMD Duron";
 404                 default:
 405                     return "Unknown AMD Athlon";
 406             }
 407         case CPUID_FAMILY_EXTENDED:
 408             switch (info_p->cpuid_model) {
 409                 case CPUID_MODEL_ATHLON64:
 410                     return "AMD Athlon 64";
 411                 case CPUID_MODEL_OPTERON:
 412                     return "AMD Opteron";
 413                 default:
 414                     return "Unknown AMD-64";
 415             }
 416     }
 417     return "Unknown AMD";
 418 }
 419
 420 static void set_amd_cache_info( i386_cpu_info_t * info_p )
 421 {
 422     uint32_t    cpuid_result[4];
 423
 424     /* It would make sense to fill in info_p->cache_info with complete information
 425      * on the TLBs and data cache associativity, lines, etc, either by mapping
 426      * to the Intel tags (if possible), or replacing cache_info with a generic
 427      * mechanism.  But right now, nothing makes use of that information (that I know
 428      * of).
 429      */
 430
 431     /* L1 Cache and TLB Information */
 432     do_cpuid(0x80000005, cpuid_result);
 433
 434     /* EAX: TLB Information for 2-Mbyte and 4-MByte Pages */
 435     /* (ignore) */
 436
 437     /* EBX: TLB Information for 4-Kbyte Pages */
 438     /* (ignore) */
 439
 440     /* ECX: L1 Data Cache Information */
 441     info_p->cache_size[L1D] = ((cpuid_result[2] >> 24) & 0xFF) * 1024;
 442     info_p->cache_linesize = (cpuid_result[2] & 0xFF);
 443
 444     /* EDX: L1 Instruction Cache Information */
 445     info_p->cache_size[L1I] = ((cpuid_result[3] >> 24) & 0xFF) * 1024;
 446
 447     /* L2 Cache Information */
 448     do_cpuid(0x80000006, cpuid_result);
 449
 450     /* EAX: L2 TLB Information for 2-Mbyte and 4-Mbyte Pages */
 451     /* (ignore) */
 452
 453     /* EBX: L2 TLB Information for 4-Kbyte Pages */
 454     /* (ignore) */
 455
 456     /* ECX: L2 Cache Information */
 457     info_p->cache_size[L2U] = ((cpuid_result[2] >> 16) & 0xFFFF) * 1024;
 458     if (info_p->cache_size[L2U] > 0)
 459         info_p->cache_linesize = cpuid_result[2] & 0xFF;
 460 }
 461
 462 static void set_cpu_amd( i386_cpu_info_t * info_p )
 463 {
 464     set_cpu_generic(info_p);
 465     set_amd_cache_info(info_p);
 466     info_p->cpuid_model_string = get_amd_model_string(info_p);
 467 }
 468
 469 static void set_cpu_nsc( i386_cpu_info_t * info_p )
 470 {
 471     set_cpu_generic(info_p);
 472     set_amd_cache_info(info_p);
 473
 474     if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX1)
 475         info_p->cpuid_model_string = "AMD Geode GX1";
 476     else if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX2)
 477         info_p->cpuid_model_string = "AMD Geode GX";
 478     else
 479         info_p->cpuid_model_string = "Unknown National Semiconductor";
 480 }
 481
 482 static void
 483 set_cpu_generic(i386_cpu_info_t *info_p)
 484 {
 485         uint32_t        cpuid_result[4];
 486         uint32_t        max_extid;
 487         char            str[128], *p;
 488
 489         /* get extended cpuid results */
 490         do_cpuid(0x80000000, cpuid_result);
 491         max_extid = cpuid_result[0];
 492
 493         /* check to see if we can get brand string */
 494         if (max_extid >= 0x80000004) {
 495                 /*
 496                  * The brand string 48 bytes (max), guaranteed to
 497                  * be NUL terminated.
 498                  */
 499                 do_cpuid(0x80000002, cpuid_result);
 500                 bcopy((char *)cpuid_result, &str[0], 16);
 501                 do_cpuid(0x80000003, cpuid_result);
 502                 bcopy((char *)cpuid_result, &str[16], 16);
 503                 do_cpuid(0x80000004, cpuid_result);
 504                 bcopy((char *)cpuid_result, &str[32], 16);
 505                 for (p = str; *p != '\0'; p++) {
 506                         if (*p != ' ') break;
 507                 }
 508                 strncpy(info_p->cpuid_brand_string,
 509                         p, sizeof(info_p->cpuid_brand_string)-1);
 510                 info_p->cpuid_brand_string[sizeof(info_p->cpuid_brand_string)-1] = '\0';
 511
 512                 if (!strcmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN)) {
 513                     /*
 514                      * This string means we have a BIOS-programmable brand string,
 515                      * and the BIOS couldn't figure out what sort of CPU we have.
 516                      */
 517                     info_p->cpuid_brand_string[0] = '\0';
 518                 }
 519         }
 520
 521         /* get processor signature and decode */
 522         do_cpuid(1, cpuid_result);
 523         info_p->cpuid_signature =  cpuid_result[0];
 524         info_p->cpuid_stepping  =  cpuid_result[0]        & 0x0f;
 525         info_p->cpuid_model     = (cpuid_result[0] >> 4)  & 0x0f;
 526         info_p->cpuid_family    = (cpuid_result[0] >> 8)  & 0x0f;
 527         info_p->cpuid_type      = (cpuid_result[0] >> 12) & 0x03;
 528         info_p->cpuid_extmodel  = (cpuid_result[0] >> 16) & 0x0f;
 529         info_p->cpuid_extfamily = (cpuid_result[0] >> 20) & 0xff;
 530         info_p->cpuid_brand     =  cpuid_result[1]        & 0xff;
 531         info_p->cpuid_features  =  cpuid_result[3];
 532
 533         return;
 534 }
 535
 536 static void
 537 set_cpu_unknown(__unused i386_cpu_info_t *info_p)
 538 {
 539     info_p->cpuid_model_string = "Unknown";
 540 }
 541
 542
 543 static struct {
 544         uint32_t        mask;
 545         const char      *name;
 546 } feature_names[] = {
 547         {CPUID_FEATURE_FPU,   "FPU",},
 548         {CPUID_FEATURE_VME,   "VME",},
 549         {CPUID_FEATURE_DE,    "DE",},
 550         {CPUID_FEATURE_PSE,   "PSE",},
 551         {CPUID_FEATURE_TSC,   "TSC",},
 552         {CPUID_FEATURE_MSR,   "MSR",},
 553         {CPUID_FEATURE_PAE,   "PAE",},
 554         {CPUID_FEATURE_MCE,   "MCE",},
 555         {CPUID_FEATURE_CX8,   "CX8",},
 556         {CPUID_FEATURE_APIC,  "APIC",},
 557         {CPUID_FEATURE_SEP,   "SEP",},
 558         {CPUID_FEATURE_MTRR,  "MTRR",},
 559         {CPUID_FEATURE_PGE,   "PGE",},
 560         {CPUID_FEATURE_MCA,   "MCA",},
 561         {CPUID_FEATURE_CMOV,  "CMOV",},
 562         {CPUID_FEATURE_PAT,   "PAT",},
 563         {CPUID_FEATURE_PSE36, "PSE36",},
 564         {CPUID_FEATURE_PSN,   "PSN",},
 565         {CPUID_FEATURE_CLFSH, "CLFSH",},
 566         {CPUID_FEATURE_DS,    "DS",},
 567         {CPUID_FEATURE_ACPI,  "ACPI",},
 568         {CPUID_FEATURE_MMX,   "MMX",},
 569         {CPUID_FEATURE_FXSR,  "FXSR",},
 570         {CPUID_FEATURE_SSE,   "SSE",},
 571         {CPUID_FEATURE_SSE2,  "SSE2",},
 572         {CPUID_FEATURE_SS,    "SS",},
 573         {CPUID_FEATURE_HTT,   "HTT",},
 574         {CPUID_FEATURE_TM,    "TM",},
 575         {0, 0}
 576 };
 577
 578 char *
 579 cpuid_get_feature_names(uint32_t feature, char *buf, unsigned buf_len)
 580 {
 581         int     i;
 582         int     len;
 583         char    *p = buf;
 584
 585         for (i = 0; feature_names[i].mask != 0; i++) {
 586                 if ((feature & feature_names[i].mask) == 0)
 587                         continue;
 588                 if (i > 0)
 589                         *p++ = ' ';
 590                 len = min(strlen(feature_names[i].name), (buf_len-1) - (p-buf));
 591                 if (len == 0)
 592                         break;
 593                 bcopy(feature_names[i].name, p, len);
 594                 p += len;
 595         }
 596         *p = '\0';
 597         return buf;
 598 }
 599
 600 void
 601 cpuid_feature_display(
 602         const char      *header,
 603         __unused int    my_cpu)
 604 {
 605         char    buf[256];
 606
 607         printf("%s: %s\n", header,
 608                   cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf)));
 609 }
 610
 611 void
 612 cpuid_cpu_display(
 613         const char      *header,
 614         __unused int    my_cpu)
 615 {
 616     if (cpuid_cpu_info.cpuid_brand_string[0] != '\0') {
 617         printf("%s: %s\n", header,
 618                cpuid_cpu_info.cpuid_brand_string);
 619     }
 620 }
 621
 622 unsigned int
 623 cpuid_family(void)
 624 {
 625         return cpuid_cpu_info.cpuid_family;
 626 }
 627
 628 unsigned int
 629 cpuid_features(void)
 630 {
 631         static int checked = 0;
 632         char    fpu_arg[16] = { 0 };
 633         if (!checked) {
 634                     /* check for boot-time fpu limitations */
 635                         if (PE_parse_boot_arg("_fpu", &fpu_arg[0])) {
 636                                 printf("limiting fpu features to: %s\n", fpu_arg);
 637                                 if (!strncmp("387", fpu_arg, sizeof "387") || !strncmp("mmx", fpu_arg, sizeof "mmx")) {
 638                                         printf("no sse or sse2\n");
 639                                         cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
 640                                 } else if (!strncmp("sse", fpu_arg, sizeof "sse")) {
 641                                         printf("no sse2\n");
 642                                         cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2);
 643                                 }
 644                         }
 645                         checked = 1;
 646         }
 647         return cpuid_cpu_info.cpuid_features;
 648 }
 649
 650 i386_cpu_info_t *
 651 cpuid_info(void)
 652 {
 653         return &cpuid_cpu_info;
 654 }
 655
 656 /* XXX for temporary compatibility */
 657 void
 658 set_cpu_model(void)
 659 {
 660         cpuid_get_info(&cpuid_cpu_info);
 661         cpuid_feature = cpuid_cpu_info.cpuid_features;  /* XXX compat */
 662 }
 663