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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_COPYRIGHT@
24 */
25 #include <platforms.h>
26 #include <mach_kdb.h>
27 #include <pexpert/pexpert.h>
28
29 #include "cpuid.h"
30 #if MACH_KDB
31 #include <i386/db_machdep.h>
32 #include <ddb/db_aout.h>
33 #include <ddb/db_access.h>
34 #include <ddb/db_sym.h>
35 #include <ddb/db_variables.h>
36 #include <ddb/db_command.h>
37 #include <ddb/db_output.h>
38 #include <ddb/db_expr.h>
39 #endif
40
41 #define min(a,b) ((a) < (b) ? (a) : (b))
42 #define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo))
43
44 #define bit(n) (1UL << (n))
45 #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
46 #define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l)
47
48 /*
49 * CPU identification routines.
50 *
51 * Note that this code assumes a processor that supports the
52 * 'cpuid' instruction.
53 */
54
55 static unsigned int cpuid_maxcpuid;
56
57 static i386_cpu_info_t *cpuid_cpu_infop = NULL;
58 static i386_cpu_info_t cpuid_cpu_info;
59
60 uint32_t cpuid_feature; /* XXX obsolescent for compat */
61
62 /*
63 * We only identify Intel CPUs here. Adding support
64 * for others would be straightforward.
65 */
66 static void set_cpu_generic(i386_cpu_info_t *);
67 static void set_cpu_intel(i386_cpu_info_t *);
68 static void set_cpu_amd(i386_cpu_info_t *);
69 static void set_cpu_nsc(i386_cpu_info_t *);
70 static void set_cpu_unknown(i386_cpu_info_t *);
71
72 struct {
73 const char *vendor;
74 void (* func)(i386_cpu_info_t *);
75 } cpu_vendors[] = {
76 {CPUID_VID_INTEL, set_cpu_intel},
77 {CPUID_VID_AMD, set_cpu_amd},
78 {CPUID_VID_NSC, set_cpu_nsc},
79 {0, set_cpu_unknown}
80 };
81
82 void
83 cpuid_get_info(i386_cpu_info_t *info_p)
84 {
85 uint32_t cpuid_result[4];
86 int i;
87
88 bzero((void *)info_p, sizeof(i386_cpu_info_t));
89
90 /* do cpuid 0 to get vendor */
91 do_cpuid(0, cpuid_result);
92 cpuid_maxcpuid = cpuid_result[eax];
93 bcopy((char *)&cpuid_result[ebx], &info_p->cpuid_vendor[0], 4); /* ug */
94 bcopy((char *)&cpuid_result[ecx], &info_p->cpuid_vendor[8], 4);
95 bcopy((char *)&cpuid_result[edx], &info_p->cpuid_vendor[4], 4);
96 info_p->cpuid_vendor[12] = 0;
97
98 /* look up vendor */
99 for (i = 0; ; i++) {
100 if ((cpu_vendors[i].vendor == 0) ||
101 (!strcmp(cpu_vendors[i].vendor, info_p->cpuid_vendor))) {
102 cpu_vendors[i].func(info_p);
103 break;
104 }
105 }
106 }
107
108 /*
109 * Cache descriptor table. Each row has the form:
110 * (descriptor_value, cache, size, linesize,
111 * description)
112 * Note: the CACHE_DESC macro does not expand description text in the kernel.
113 */
114 static cpuid_cache_desc_t cpuid_cache_desc_tab[] = {
115 CACHE_DESC(CPUID_CACHE_ITLB_4K, Lnone, 0, 0, \
116 "Instruction TLB, 4K, pages 4-way set associative, 64 entries"),
117 CACHE_DESC(CPUID_CACHE_ITLB_4M, Lnone, 0, 0, \
118 "Instruction TLB, 4M, pages 4-way set associative, 2 entries"),
119 CACHE_DESC(CPUID_CACHE_DTLB_4K, Lnone, 0, 0, \
120 "Data TLB, 4K pages, 4-way set associative, 64 entries"),
121 CACHE_DESC(CPUID_CACHE_DTLB_4M, Lnone, 0, 0, \
122 "Data TLB, 4M pages, 4-way set associative, 8 entries"),
123 CACHE_DESC(CPUID_CACHE_ITLB_64, Lnone, 0, 0, \
124 "Instruction TLB, 4K and 2M or 4M pages, 64 entries"),
125 CACHE_DESC(CPUID_CACHE_ITLB_128, Lnone, 0, 0, \
126 "Instruction TLB, 4K and 2M or 4M pages, 128 entries"),
127 CACHE_DESC(CPUID_CACHE_ITLB_256, Lnone, 0, 0, \
128 "Instruction TLB, 4K and 2M or 4M pages, 256 entries"),
129 CACHE_DESC(CPUID_CACHE_DTLB_64, Lnone, 0, 0, \
130 "Data TLB, 4K and 4M pages, 64 entries"),
131 CACHE_DESC(CPUID_CACHE_DTLB_128, Lnone, 0, 0, \
132 "Data TLB, 4K and 4M pages, 128 entries"),
133 CACHE_DESC(CPUID_CACHE_DTLB_256, Lnone, 0, 0, \
134 "Data TLB, 4K and 4M pages, 256 entries"),
135 CACHE_DESC(CPUID_CACHE_ITLB_4K_128_4, Lnone, 0, 0, \
136 "Instruction TLB, 4K pages, 4-way set associative, 128 entries"),
137 CACHE_DESC(CPUID_CACHE_DTLB_4K_128_4, Lnone, 0, 0, \
138 "Data TLB, 4K pages, 4-way set associative, 128 entries"),
139 CACHE_DESC(CPUID_CACHE_ICACHE_8K, L1I, 8*1024, 32, \
140 "Instruction L1 cache, 8K, 4-way set associative, 32byte line size"),
141 CACHE_DESC(CPUID_CACHE_DCACHE_8K, L1D, 8*1024, 32, \
142 "Data L1 cache, 8K, 2-way set associative, 32byte line size"),
143 CACHE_DESC(CPUID_CACHE_ICACHE_16K, L1I, 16*1024, 32, \
144 "Instruction L1 cache, 16K, 4-way set associative, 32byte line size"),
145 CACHE_DESC(CPUID_CACHE_DCACHE_16K, L1D, 16*1024, 32, \
146 "Data L1 cache, 16K, 4-way set associative, 32byte line size"),
147 CACHE_DESC(CPUID_CACHE_DCACHE_8K_4_64, L1D, 8*1024, 64, \
148 "Data L1 cache, 8K, 4-way set associative, 64byte line size"),
149 CACHE_DESC(CPUID_CACHE_DCACHE_16K_4_64, L1D, 16*1024, 64, \
150 "Data L1 cache, 16K, 4-way set associative, 64byte line size"),
151 CACHE_DESC(CPUID_CACHE_DCACHE_32K_4_64, L1D, 32*1024, 64, \
152 "Data L1 cache, 32K, 4-way set associative, 64byte line size"),
153 CACHE_DESC(CPUID_CACHE_DCACHE_32K, L1D, 32*1024, 64, \
154 "Data L1 cache, 32K, 8-way set assocative, 64byte line size"),
155 CACHE_DESC(CPUID_CACHE_ICACHE_32K, L1I, 32*1024, 64, \
156 "Instruction L1 cache, 32K, 8-way set associative, 64byte line size"),
157 CACHE_DESC(CPUID_CACHE_DCACHE_16K_8_64, L1D, 16*1024, 64, \
158 "Data L1 cache, 16K, 8-way set associative, 64byte line size"),
159 CACHE_DESC(CPUID_CACHE_TRACE_12K_8, L1I, 12*1024, 64, \
160 "Trace cache, 12K-uop, 8-way set associative"),
161 CACHE_DESC(CPUID_CACHE_TRACE_16K_8, L1I, 16*1024, 64, \
162 "Trace cache, 16K-uop, 8-way set associative"),
163 CACHE_DESC(CPUID_CACHE_TRACE_32K_8, L1I, 32*1024, 64, \
164 "Trace cache, 32K-uop, 8-way set associative"),
165 CACHE_DESC(CPUID_CACHE_L2_128K, L2U, 128*1024, 32, \
166 "Unified L2 cache, 128K, 4-way set associative, 32byte line size"),
167 CACHE_DESC(CPUID_CACHE_L2_256K, L2U, 128*1024, 32, \
168 "Unified L2 cache, 256K, 4-way set associative, 32byte line size"),
169 CACHE_DESC(CPUID_CACHE_L2_512K, L2U, 512*1024, 32, \
170 "Unified L2 cache, 512K, 4-way set associative, 32byte line size"),
171 CACHE_DESC(CPUID_CACHE_L2_1M_4, L2U, 1*1024*1024, 32, \
172 "Unified L2 cache, 1M, 4-way set associative, 32byte line size"),
173 CACHE_DESC(CPUID_CACHE_L2_2M_4, L2U, 2*1024*1024, 32, \
174 "Unified L2 cache, 2M, 4-way set associative, 32byte line size"),
175 CACHE_DESC(CPUID_CACHE_L2_4M_16_64, L2U, 4*1024*1024, 64, \
176 "Unified L2 cache, 4M, 16-way set associative, 64byte line size"),
177 CACHE_DESC(CPUID_CACHE_L2_128K_8_64_2, L2U, 128*1024, 64, \
178 "Unified L2 cache, 128K, 8-way set associative, 64byte line size"),
179 CACHE_DESC(CPUID_CACHE_L2_256K_8_64_2, L2U, 256*1024, 64, \
180 "Unified L2 cache, 256K, 8-way set associative, 64byte line size"),
181 CACHE_DESC(CPUID_CACHE_L2_512K_8_64_2, L2U, 512*1024, 64, \
182 "Unified L2 cache, 512K, 8-way set associative, 64byte line size"),
183 CACHE_DESC(CPUID_CACHE_L2_1M_8_64_2, L2U, 1*1024*1024, 64, \
184 "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
185 CACHE_DESC(CPUID_CACHE_L2_256K_8_32, L2U, 256*1024, 32, \
186 "Unified L2 cache, 256K, 8-way set associative, 32byte line size"),
187 CACHE_DESC(CPUID_CACHE_L2_512K_8_32, L2U, 512*1024, 32, \
188 "Unified L2 cache, 512K, 8-way set associative, 32byte line size"),
189 CACHE_DESC(CPUID_CACHE_L2_1M_8_32, L2U, 1*1024*1024, 32, \
190 "Unified L2 cache, 1M, 8-way set associative, 32byte line size"),
191 CACHE_DESC(CPUID_CACHE_L2_2M_8_32, L2U, 2*1024*1024, 32, \
192 "Unified L2 cache, 2M, 8-way set associative, 32byte line size"),
193 CACHE_DESC(CPUID_CACHE_L2_1M_4_64, L2U, 1*1024*1024, 64, \
194 "Unified L2 cache, 1M, 4-way set associative, 64byte line size"),
195 CACHE_DESC(CPUID_CACHE_L2_2M_8_64, L2U, 2*1024*1024, 64, \
196 "Unified L2 cache, 2M, 8-way set associative, 64byte line size"),
197 CACHE_DESC(CPUID_CACHE_L2_512K_2_64,L2U, 512*1024, 64, \
198 "Unified L2 cache, 512K, 2-way set associative, 64byte line size"),
199 CACHE_DESC(CPUID_CACHE_L2_512K_4_64,L2U, 512*1024, 64, \
200 "Unified L2 cache, 512K, 4-way set associative, 64byte line size"),
201 CACHE_DESC(CPUID_CACHE_L2_1M_8_64, L2U, 1*1024*1024, 64, \
202 "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
203 CACHE_DESC(CPUID_CACHE_L2_128K_S4, L2U, 128*1024, 64, \
204 "Unified L2 sectored cache, 128K, 4-way set associative, 64byte line size"),
205 CACHE_DESC(CPUID_CACHE_L2_128K_S2, L2U, 128*1024, 64, \
206 "Unified L2 sectored cache, 128K, 2-way set associative, 64byte line size"),
207 CACHE_DESC(CPUID_CACHE_L2_256K_S4, L2U, 256*1024, 64, \
208 "Unified L2 sectored cache, 256K, 4-way set associative, 64byte line size"),
209 CACHE_DESC(CPUID_CACHE_L3_512K, L3U, 512*1024, 64, \
210 "Unified L3 cache, 512K, 4-way set associative, 64byte line size"),
211 CACHE_DESC(CPUID_CACHE_L3_1M, L3U, 1*1024*1024, 64, \
212 "Unified L3 cache, 1M, 8-way set associative, 64byte line size"),
213 CACHE_DESC(CPUID_CACHE_L3_2M, L3U, 2*1024*1024, 64, \
214 "Unified L3 cache, 2M, 8-way set associative, 64byte line size"),
215 CACHE_DESC(CPUID_CACHE_L3_4M, L3U, 4*1024*1024, 64, \
216 "Unified L3 cache, 4M, 8-way set associative, 64byte line size"),
217 CACHE_DESC(CPUID_CACHE_PREFETCH_64, Lnone, 0, 0, \
218 "64-Byte Prefetching"),
219 CACHE_DESC(CPUID_CACHE_PREFETCH_128, Lnone, 0, 0, \
220 "128-Byte Prefetching"),
221 CACHE_DESC(CPUID_CACHE_NOCACHE, Lnone, 0, 0, \
222 "No L2 cache or, if valid L2 cache, no L3 cache"),
223 CACHE_DESC(CPUID_CACHE_NULL, Lnone, 0, 0, \
224 (char *)0),
225 };
226
227 static const char * get_intel_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype)
228 {
229 *type = CPU_TYPE_X86;
230 *subtype = CPU_SUBTYPE_X86_ARCH1;
231
232 /* check for brand id string */
233 switch(info_p->cpuid_brand) {
234 case CPUID_BRAND_UNSUPPORTED:
235 /* brand ID not supported; use alternate method. */
236 switch(info_p->cpuid_family) {
237 case CPUID_FAMILY_486:
238 return "Intel 486";
239 case CPUID_FAMILY_586:
240 return "Intel Pentium";
241 case CPUID_FAMILY_686:
242 switch(info_p->cpuid_model) {
243 case CPUID_MODEL_P6:
244 return "Intel Pentium Pro";
245 case CPUID_MODEL_PII:
246 return "Intel Pentium II";
247 case CPUID_MODEL_P65:
248 case CPUID_MODEL_P66:
249 return "Intel Celeron";
250 case CPUID_MODEL_P67:
251 case CPUID_MODEL_P68:
252 case CPUID_MODEL_P6A:
253 case CPUID_MODEL_P6B:
254 return "Intel Pentium III";
255 case CPUID_MODEL_PM9:
256 case CPUID_MODEL_PMD:
257 return "Intel Pentium M";
258 default:
259 return "Unknown Intel P6 Family";
260 }
261 case CPUID_FAMILY_EXTENDED:
262 switch (info_p->cpuid_extfamily) {
263 case CPUID_EXTFAMILY_PENTIUM4:
264 *subtype = CPU_SUBTYPE_PENTIUM_4;
265 return "Intel Pentium 4";
266 default:
267 return "Unknown Intel Extended Family";
268 }
269 default:
270 return "Unknown Intel Family";
271 }
272 break;
273 case CPUID_BRAND_CELERON_1:
274 case CPUID_BRAND_CELERON_A:
275 case CPUID_BRAND_CELERON_14:
276 return "Intel Celeron";
277 case CPUID_BRAND_PENTIUM_III_2:
278 case CPUID_BRAND_PENTIUM_III_4:
279 return "Pentium III";
280 case CPUID_BRAND_PIII_XEON:
281 if (info_p->cpuid_signature == 0x6B1) {
282 return "Intel Celeron";
283 } else {
284 return "Intel Pentium III Xeon";
285 }
286 case CPUID_BRAND_PENTIUM_III_M:
287 return "Mobile Intel Pentium III-M";
288 case CPUID_BRAND_M_CELERON_7:
289 case CPUID_BRAND_M_CELERON_F:
290 case CPUID_BRAND_M_CELERON_13:
291 case CPUID_BRAND_M_CELERON_17:
292 return "Mobile Intel Celeron";
293 case CPUID_BRAND_PENTIUM4_8:
294 case CPUID_BRAND_PENTIUM4_9:
295 *subtype = CPU_SUBTYPE_PENTIUM_4;
296 return "Intel Pentium 4";
297 case CPUID_BRAND_XEON:
298 return "Intel Xeon";
299 case CPUID_BRAND_XEON_MP:
300 return "Intel Xeon MP";
301 case CPUID_BRAND_PENTIUM4_M:
302 if (info_p->cpuid_signature == 0xF13) {
303 return "Intel Xeon";
304 } else {
305 *subtype = CPU_SUBTYPE_PENTIUM_4;
306 return "Mobile Intel Pentium 4";
307 }
308 case CPUID_BRAND_CELERON_M:
309 return "Intel Celeron M";
310 case CPUID_BRAND_PENTIUM_M:
311 return "Intel Pentium M";
312 case CPUID_BRAND_MOBILE_15:
313 case CPUID_BRAND_MOBILE_17:
314 return "Mobile Intel";
315 }
316 return "Unknown Intel";
317 }
318
319 static void set_intel_cache_info( i386_cpu_info_t * info_p )
320 {
321 uint32_t cpuid_result[4];
322 uint32_t l1d_cache_linesize = 0;
323 unsigned int i;
324 unsigned int j;
325
326 /* get processor cache descriptor info */
327 do_cpuid(2, cpuid_result);
328 for (j = 0; j < 4; j++) {
329 if ((cpuid_result[j] >> 31) == 1) /* bit31 is validity */
330 continue;
331 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j];
332 }
333 /* first byte gives number of cpuid calls to get all descriptors */
334 for (i = 1; i < info_p->cache_info[0]; i++) {
335 if (i*16 > sizeof(info_p->cache_info))
336 break;
337 do_cpuid(2, cpuid_result);
338 for (j = 0; j < 4; j++) {
339 if ((cpuid_result[j] >> 31) == 1)
340 continue;
341 ((uint32_t *) info_p->cache_info)[4*i+j] =
342 cpuid_result[j];
343 }
344 }
345
346 /* decode the descriptors looking for L1/L2/L3 size info */
347 for (i = 1; i < sizeof(info_p->cache_info); i++) {
348 cpuid_cache_desc_t *descp;
349 uint8_t desc = info_p->cache_info[i];
350
351 if (desc == CPUID_CACHE_NULL)
352 continue;
353 for (descp = cpuid_cache_desc_tab;
354 descp->value != CPUID_CACHE_NULL; descp++) {
355 if (descp->value != desc)
356 continue;
357 info_p->cache_size[descp->type] = descp->size;
358 if (descp->type == L2U)
359 info_p->cache_linesize = descp->linesize;
360 if (descp->type == L1D)
361 l1d_cache_linesize = descp->linesize;
362 break;
363 }
364 }
365 /* For P-IIIs, L2 could be 256k or 512k but we can't tell */
366 if (info_p->cache_size[L2U] == 0 &&
367 info_p->cpuid_family == 0x6 && info_p->cpuid_model == 0xb) {
368 info_p->cache_size[L2U] = 256*1024;
369 info_p->cache_linesize = 32;
370 }
371 /* If we have no L2 cache, use the L1 data cache line size */
372 if (info_p->cache_size[L2U] == 0)
373 info_p->cache_linesize = l1d_cache_linesize;
374
375 /*
376 * Get cache sharing info if available.
377 */
378 do_cpuid(0, cpuid_result);
379 if (cpuid_result[eax] >= 4) {
380 uint32_t reg[4];
381 uint32_t index;
382 for (index = 0;; index++) {
383 /*
384 * Scan making calls for cpuid with %eax = 4
385 * to get info about successive cache levels
386 * until a null type is returned.
387 */
388 cache_type_t type = Lnone;
389 uint32_t cache_type;
390 uint32_t cache_level;
391 uint32_t cache_sharing;
392
393 reg[eax] = 4; /* cpuid request 4 */
394 reg[ecx] = index; /* index starting at 0 */
395 cpuid(reg);
396 //kprintf("cpuid(4) index=%d eax=%p\n", index, reg[eax]);
397 cache_type = bitfield(reg[eax], 4, 0);
398 if (cache_type == 0)
399 break; /* done with cache info */
400 cache_level = bitfield(reg[eax], 7, 5);
401 cache_sharing = bitfield(reg[eax], 25, 14);
402 info_p->cpuid_cores_per_package =
403 bitfield(reg[eax], 31, 26) + 1;
404 switch (cache_level) {
405 case 1:
406 type = cache_type == 1 ? L1D :
407 cache_type == 2 ? L1I :
408 Lnone;
409 break;
410 case 2:
411 type = cache_type == 3 ? L2U :
412 Lnone;
413 break;
414 case 3:
415 type = cache_type == 3 ? L3U :
416 Lnone;
417 }
418 if (type != Lnone)
419 info_p->cache_sharing[type] = cache_sharing + 1;
420 }
421 }
422 }
423
424 static void set_cpu_intel( i386_cpu_info_t * info_p )
425 {
426 set_cpu_generic(info_p);
427 set_intel_cache_info(info_p);
428 info_p->cpuid_model_string = get_intel_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype);
429 }
430
431 static const char * get_amd_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype )
432 {
433 *type = CPU_TYPE_X86;
434 *subtype = CPU_SUBTYPE_X86_ARCH1;
435
436 /* check for brand id string */
437 switch (info_p->cpuid_family)
438 {
439 case CPUID_FAMILY_486:
440 switch (info_p->cpuid_model) {
441 case CPUID_MODEL_AM486_DX:
442 case CPUID_MODEL_AM486_DX2:
443 case CPUID_MODEL_AM486_DX2WB:
444 case CPUID_MODEL_AM486_DX4:
445 case CPUID_MODEL_AM486_DX4WB:
446 return "Am486";
447 case CPUID_MODEL_AM486_5X86:
448 case CPUID_MODEL_AM486_5X86WB:
449 return "Am5x86";
450 }
451 break;
452 case CPUID_FAMILY_586:
453 switch (info_p->cpuid_model) {
454 case CPUID_MODEL_K5M0:
455 case CPUID_MODEL_K5M1:
456 case CPUID_MODEL_K5M2:
457 case CPUID_MODEL_K5M3:
458 return "AMD-K5";
459 case CPUID_MODEL_K6M6:
460 case CPUID_MODEL_K6M7:
461 return "AMD-K6";
462 case CPUID_MODEL_K6_2:
463 return "AMD-K6-2";
464 case CPUID_MODEL_K6_III:
465 return "AMD-K6-III";
466 }
467 break;
468 case CPUID_FAMILY_686:
469 switch (info_p->cpuid_model) {
470 case CPUID_MODEL_ATHLON_M1:
471 case CPUID_MODEL_ATHLON_M2:
472 case CPUID_MODEL_ATHLON_M4:
473 case CPUID_MODEL_ATHLON_M6:
474 case CPUID_MODEL_ATHLON_M8:
475 case CPUID_MODEL_ATHLON_M10:
476 return "AMD Athlon";
477 case CPUID_MODEL_DURON_M3:
478 case CPUID_MODEL_DURON_M7:
479 return "AMD Duron";
480 default:
481 return "Unknown AMD Athlon";
482 }
483 case CPUID_FAMILY_EXTENDED:
484 switch (info_p->cpuid_model) {
485 case CPUID_MODEL_ATHLON64:
486 return "AMD Athlon 64";
487 case CPUID_MODEL_OPTERON:
488 return "AMD Opteron";
489 default:
490 return "Unknown AMD-64";
491 }
492 }
493 return "Unknown AMD";
494 }
495
496 static void set_amd_cache_info( i386_cpu_info_t * info_p )
497 {
498 uint32_t cpuid_result[4];
499
500 /* It would make sense to fill in info_p->cache_info with complete information
501 * on the TLBs and data cache associativity, lines, etc, either by mapping
502 * to the Intel tags (if possible), or replacing cache_info with a generic
503 * mechanism. But right now, nothing makes use of that information (that I know
504 * of).
505 */
506
507 /* L1 Cache and TLB Information */
508 do_cpuid(0x80000005, cpuid_result);
509
510 /* EAX: TLB Information for 2-Mbyte and 4-MByte Pages */
511 /* (ignore) */
512
513 /* EBX: TLB Information for 4-Kbyte Pages */
514 /* (ignore) */
515
516 /* ECX: L1 Data Cache Information */
517 info_p->cache_size[L1D] = ((cpuid_result[ecx] >> 24) & 0xFF) * 1024;
518 info_p->cache_linesize = (cpuid_result[ecx] & 0xFF);
519
520 /* EDX: L1 Instruction Cache Information */
521 info_p->cache_size[L1I] = ((cpuid_result[edx] >> 24) & 0xFF) * 1024;
522
523 /* L2 Cache Information */
524 do_cpuid(0x80000006, cpuid_result);
525
526 /* EAX: L2 TLB Information for 2-Mbyte and 4-Mbyte Pages */
527 /* (ignore) */
528
529 /* EBX: L2 TLB Information for 4-Kbyte Pages */
530 /* (ignore) */
531
532 /* ECX: L2 Cache Information */
533 info_p->cache_size[L2U] = ((cpuid_result[ecx] >> 16) & 0xFFFF) * 1024;
534 if (info_p->cache_size[L2U] > 0)
535 info_p->cache_linesize = cpuid_result[ecx] & 0xFF;
536 }
537
538 static void set_cpu_amd( i386_cpu_info_t * info_p )
539 {
540 set_cpu_generic(info_p);
541 set_amd_cache_info(info_p);
542 info_p->cpuid_model_string = get_amd_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype);
543 }
544
545 static void set_cpu_nsc( i386_cpu_info_t * info_p )
546 {
547 set_cpu_generic(info_p);
548 set_amd_cache_info(info_p);
549
550 /* check for brand id string */
551 if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX1) {
552 info_p->cpuid_model_string = "AMD Geode GX1";
553 } else if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX2) {
554 info_p->cpuid_model_string = "AMD Geode GX";
555 } else {
556 info_p->cpuid_model_string = "Unknown National Semiconductor";
557 }
558 info_p->cpuid_cpu_type = CPU_TYPE_X86;
559 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
560 }
561
562 static void
563 set_cpu_generic(i386_cpu_info_t *info_p)
564 {
565 uint32_t cpuid_result[4];
566 uint32_t max_extid;
567 char str[128], *p;
568
569 /* get extended cpuid results */
570 do_cpuid(0x80000000, cpuid_result);
571 max_extid = cpuid_result[eax];
572
573 /* check to see if we can get brand string */
574 if (max_extid >= 0x80000004) {
575 /*
576 * The brand string 48 bytes (max), guaranteed to
577 * be NUL terminated.
578 */
579 do_cpuid(0x80000002, cpuid_result);
580 bcopy((char *)cpuid_result, &str[0], 16);
581 do_cpuid(0x80000003, cpuid_result);
582 bcopy((char *)cpuid_result, &str[16], 16);
583 do_cpuid(0x80000004, cpuid_result);
584 bcopy((char *)cpuid_result, &str[32], 16);
585 for (p = str; *p != '\0'; p++) {
586 if (*p != ' ') break;
587 }
588 strncpy(info_p->cpuid_brand_string,
589 p, sizeof(info_p->cpuid_brand_string)-1);
590 info_p->cpuid_brand_string[sizeof(info_p->cpuid_brand_string)-1] = '\0';
591
592 if (!strcmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN)) {
593 /*
594 * This string means we have a BIOS-programmable brand string,
595 * and the BIOS couldn't figure out what sort of CPU we have.
596 */
597 info_p->cpuid_brand_string[0] = '\0';
598 }
599 }
600
601 /* get processor signature and decode */
602 do_cpuid(1, cpuid_result);
603 info_p->cpuid_signature = cpuid_result[eax];
604 info_p->cpuid_stepping = bitfield(cpuid_result[eax], 3, 0);
605 info_p->cpuid_model = bitfield(cpuid_result[eax], 7, 4);
606 info_p->cpuid_family = bitfield(cpuid_result[eax], 11, 8);
607 info_p->cpuid_type = bitfield(cpuid_result[eax], 13, 12);
608 info_p->cpuid_extmodel = bitfield(cpuid_result[eax], 19, 16);
609 info_p->cpuid_extfamily = bitfield(cpuid_result[eax], 27, 20);
610 info_p->cpuid_brand = bitfield(cpuid_result[ebx], 7, 0);
611 info_p->cpuid_logical_per_package =
612 bitfield(cpuid_result[ebx], 23, 16);
613 info_p->cpuid_features = quad(cpuid_result[ecx], cpuid_result[edx]);
614
615 if (max_extid >= 0x80000001) {
616 do_cpuid(0x80000001, cpuid_result);
617 info_p->cpuid_extfeatures =
618 quad(cpuid_result[ecx], cpuid_result[edx]);
619 }
620
621 return;
622 }
623
624 static void
625 set_cpu_unknown(__unused i386_cpu_info_t *info_p)
626 {
627 info_p->cpuid_model_string = "Unknown";
628 }
629
630
631 static struct {
632 uint64_t mask;
633 const char *name;
634 } feature_map[] = {
635 {CPUID_FEATURE_FPU, "FPU",},
636 {CPUID_FEATURE_VME, "VME",},
637 {CPUID_FEATURE_DE, "DE",},
638 {CPUID_FEATURE_PSE, "PSE",},
639 {CPUID_FEATURE_TSC, "TSC",},
640 {CPUID_FEATURE_MSR, "MSR",},
641 {CPUID_FEATURE_PAE, "PAE",},
642 {CPUID_FEATURE_MCE, "MCE",},
643 {CPUID_FEATURE_CX8, "CX8",},
644 {CPUID_FEATURE_APIC, "APIC",},
645 {CPUID_FEATURE_SEP, "SEP",},
646 {CPUID_FEATURE_MTRR, "MTRR",},
647 {CPUID_FEATURE_PGE, "PGE",},
648 {CPUID_FEATURE_MCA, "MCA",},
649 {CPUID_FEATURE_CMOV, "CMOV",},
650 {CPUID_FEATURE_PAT, "PAT",},
651 {CPUID_FEATURE_PSE36, "PSE36",},
652 {CPUID_FEATURE_PSN, "PSN",},
653 {CPUID_FEATURE_CLFSH, "CLFSH",},
654 {CPUID_FEATURE_DS, "DS",},
655 {CPUID_FEATURE_ACPI, "ACPI",},
656 {CPUID_FEATURE_MMX, "MMX",},
657 {CPUID_FEATURE_FXSR, "FXSR",},
658 {CPUID_FEATURE_SSE, "SSE",},
659 {CPUID_FEATURE_SSE2, "SSE2",},
660 {CPUID_FEATURE_SS, "SS",},
661 {CPUID_FEATURE_HTT, "HTT",},
662 {CPUID_FEATURE_TM, "TM",},
663 {CPUID_FEATURE_SSE3, "SSE3"},
664 {CPUID_FEATURE_MONITOR, "MON"},
665 {CPUID_FEATURE_DSCPL, "DSCPL"},
666 {CPUID_FEATURE_VMX, "VMX"},
667 {CPUID_FEATURE_SMX, "SMX"},
668 {CPUID_FEATURE_EST, "EST"},
669 {CPUID_FEATURE_TM2, "TM2"},
670 {CPUID_FEATURE_MNI, "MNI"},
671 {CPUID_FEATURE_CID, "CID"},
672 {CPUID_FEATURE_CX16, "CX16"},
673 {CPUID_FEATURE_xTPR, "TPR"},
674 {CPUID_FEATURE_PDCM, "PDCM"},
675 {CPUID_FEATURE_DCA, "DCA"},
676 {CPUID_FEATURE_SSE4_1, "SSE4.1"},
677 {CPUID_FEATURE_SSE4_2, "SSE4.2"},
678 {CPUID_FEATURE_POPCNT, "POPCNT"},
679 {0, 0}
680 },
681 extfeature_map[] = {
682 {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"},
683 {CPUID_EXTFEATURE_XD, "XD"},
684 {CPUID_EXTFEATURE_EM64T, "EM64T"},
685 {CPUID_EXTFEATURE_LAHF, "LAHF"},
686 {0, 0}
687 };
688
689 i386_cpu_info_t *
690 cpuid_info(void)
691 {
692 /* Set-up the cpuid_indo stucture lazily */
693 if (cpuid_cpu_infop == NULL) {
694 cpuid_get_info(&cpuid_cpu_info);
695 cpuid_cpu_infop = &cpuid_cpu_info;
696 }
697 return cpuid_cpu_infop;
698 }
699
700 char *
701 cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len)
702 {
703 int len = -1;
704 char *p = buf;
705 int i;
706
707 for (i = 0; feature_map[i].mask != 0; i++) {
708 if ((features & feature_map[i].mask) == 0)
709 continue;
710 if (len > 0)
711 *p++ = ' ';
712 len = min(strlen(feature_map[i].name), (buf_len-1) - (p-buf));
713 if (len == 0)
714 break;
715 bcopy(feature_map[i].name, p, len);
716 p += len;
717 }
718 *p = '\0';
719 return buf;
720 }
721
722 char *
723 cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len)
724 {
725 int len = -1;
726 char *p = buf;
727 int i;
728
729 for (i = 0; extfeature_map[i].mask != 0; i++) {
730 if ((extfeatures & extfeature_map[i].mask) == 0)
731 continue;
732 if (len > 0)
733 *p++ = ' ';
734 len = min(strlen(extfeature_map[i].name), (buf_len-1)-(p-buf));
735 if (len == 0)
736 break;
737 bcopy(extfeature_map[i].name, p, len);
738 p += len;
739 }
740 *p = '\0';
741 return buf;
742 }
743
744 void
745 cpuid_feature_display(
746 const char *header)
747 {
748 char buf[256];
749
750 kprintf("%s: %s\n", header,
751 cpuid_get_feature_names(cpuid_features(),
752 buf, sizeof(buf)));
753 if (cpuid_features() & CPUID_FEATURE_HTT) {
754 #define s_if_plural(n) ((n > 1) ? "s" : "")
755 kprintf(" HTT: %d core%s per package;"
756 " %d logical cpu%s per package\n",
757 cpuid_cpu_info.cpuid_cores_per_package,
758 s_if_plural(cpuid_cpu_info.cpuid_cores_per_package),
759 cpuid_cpu_info.cpuid_logical_per_package,
760 s_if_plural(cpuid_cpu_info.cpuid_logical_per_package));
761 }
762 }
763
764 void
765 cpuid_extfeature_display(
766 const char *header)
767 {
768 char buf[256];
769
770 kprintf("%s: %s\n", header,
771 cpuid_get_extfeature_names(cpuid_extfeatures(),
772 buf, sizeof(buf)));
773 }
774
775 void
776 cpuid_cpu_display(
777 const char *header)
778 {
779 if (cpuid_info()->cpuid_brand_string[0] != '\0') {
780 kprintf("%s: %s\n", header, cpuid_cpu_info.cpuid_brand_string);
781 }
782 }
783
784 unsigned int
785 cpuid_family(void)
786 {
787 return cpuid_info()->cpuid_family;
788 }
789
790 cpu_type_t
791 cpuid_cputype(void)
792 {
793 return cpuid_info()->cpuid_cpu_type;
794 }
795
796 cpu_subtype_t
797 cpuid_cpusubtype(void)
798 {
799 return cpuid_info()->cpuid_cpu_subtype;
800 }
801
802 uint64_t
803 cpuid_features(void)
804 {
805 static int checked = 0;
806 char fpu_arg[16] = { 0 };
807
808 (void) cpuid_info();
809 if (!checked) {
810 /* check for boot-time fpu limitations */
811 if (PE_parse_boot_arg("_fpu", &fpu_arg[0])) {
812 printf("limiting fpu features to: %s\n", fpu_arg);
813 if (!strncmp("387", fpu_arg, sizeof "387") || !strncmp("mmx", fpu_arg, sizeof "mmx")) {
814 printf("no sse or sse2\n");
815 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
816 } else if (!strncmp("sse", fpu_arg, sizeof "sse")) {
817 printf("no sse2\n");
818 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2);
819 }
820 }
821 checked = 1;
822 }
823 return cpuid_cpu_info.cpuid_features;
824 }
825
826 uint64_t
827 cpuid_extfeatures(void)
828 {
829 return cpuid_info()->cpuid_extfeatures;
830 }
831
832 void
833 cpuid_set_info(void)
834 {
835 cpuid_get_info(&cpuid_cpu_info);
836 }
837
838 #if MACH_KDB
839
840 /*
841 * Display the cpuid
842 * *
843 * cp
844 */
845 void
846 db_cpuid(__unused db_expr_t addr,
847 __unused int have_addr,
848 __unused db_expr_t count,
849 __unused char *modif)
850 {
851
852 uint32_t i, mid;
853 uint32_t cpid[4];
854
855 do_cpuid(0, cpid); /* Get the first cpuid which is the number of
856 * basic ids */
857 db_printf("%08X - %08X %08X %08X %08X\n",
858 0, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
859
860 mid = cpid[eax]; /* Set the number */
861 for (i = 1; i <= mid; i++) { /* Dump 'em out */
862 do_cpuid(i, cpid); /* Get the next */
863 db_printf("%08X - %08X %08X %08X %08X\n",
864 i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
865 }
866 db_printf("\n");
867
868 do_cpuid(0x80000000, cpid); /* Get the first extended cpuid which
869 * is the number of extended ids */
870 db_printf("%08X - %08X %08X %08X %08X\n",
871 0x80000000, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
872
873 mid = cpid[eax]; /* Set the number */
874 for (i = 0x80000001; i <= mid; i++) { /* Dump 'em out */
875 do_cpuid(i, cpid); /* Get the next */
876 db_printf("%08X - %08X %08X %08X %08X\n",
877 i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
878 }
879 }
880
881 #endif
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