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0c530ab8 1/*
593a1d5f 2 * Copyright (c) 2005-2008 Apple Inc. All rights reserved.
0c530ab8 3 *
2d21ac55 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
0a7de745 5 *
2d21ac55
A
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
0a7de745 14 *
2d21ac55
A
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
0a7de745 17 *
2d21ac55
A
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
0c530ab8
A
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55
A
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
0a7de745 25 *
2d21ac55 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
0c530ab8
A
27 */
28/*
29 * @OSF_FREE_COPYRIGHT@
30 */
31/*
32 * @APPLE_FREE_COPYRIGHT@
33 */
34
35/*
36 * Author: Bill Angell, Apple
37 * Date: 10/auht-five
38 *
316670eb 39 * Random diagnostics, augmented Derek Kumar 2011
0c530ab8 40 *
0c530ab8
A
41 *
42 */
43
44
45#include <kern/machine.h>
46#include <kern/processor.h>
47#include <mach/machine.h>
48#include <mach/processor_info.h>
49#include <mach/mach_types.h>
50#include <mach/boolean.h>
51#include <kern/thread.h>
52#include <kern/task.h>
53#include <kern/ipc_kobject.h>
54#include <mach/vm_param.h>
55#include <ipc/port.h>
56#include <ipc/ipc_entry.h>
57#include <ipc/ipc_space.h>
58#include <ipc/ipc_object.h>
59#include <ipc/ipc_port.h>
60#include <vm/vm_kern.h>
61#include <vm/vm_map.h>
62#include <vm/vm_page.h>
63#include <vm/pmap.h>
64#include <pexpert/pexpert.h>
65#include <console/video_console.h>
66#include <i386/cpu_data.h>
67#include <i386/Diagnostics.h>
68#include <i386/mp.h>
69#include <i386/pmCPU.h>
70#include <i386/tsc.h>
0c530ab8 71#include <mach/i386/syscall_sw.h>
316670eb 72#include <kern/kalloc.h>
db609669 73#include <sys/kdebug.h>
bd504ef0
A
74#include <i386/machine_cpu.h>
75#include <i386/misc_protos.h>
76#include <i386/cpuid.h>
77
5ba3f43e
A
78#if MONOTONIC
79#include <kern/monotonic.h>
80#endif /* MONOTONIC */
81
bd504ef0
A
82#define PERMIT_PERMCHECK (0)
83
0c530ab8 84diagWork dgWork;
0c530ab8 85uint64_t lastRuptClear = 0ULL;
0a7de745 86boolean_t diag_pmc_enabled = FALSE;
4b17d6b6
A
87void cpu_powerstats(void *);
88
89typedef struct {
90 uint64_t caperf;
91 uint64_t cmperf;
bd504ef0
A
92 uint64_t ccres[6];
93 uint64_t crtimes[CPU_RTIME_BINS];
94 uint64_t citimes[CPU_ITIME_BINS];
4b17d6b6
A
95 uint64_t crtime_total;
96 uint64_t citime_total;
bd504ef0
A
97 uint64_t cpu_idle_exits;
98 uint64_t cpu_insns;
99 uint64_t cpu_ucc;
100 uint64_t cpu_urc;
0a7de745 101#if DIAG_ALL_PMCS
a1c7dba1
A
102 uint64_t gpmcs[4];
103#endif /* DIAG_ALL_PMCS */
4b17d6b6
A
104} core_energy_stat_t;
105
106typedef struct {
39236c6e 107 uint64_t pkes_version;
bd504ef0 108 uint64_t pkg_cres[2][7];
4b17d6b6
A
109 uint64_t pkg_power_unit;
110 uint64_t pkg_energy;
bd504ef0
A
111 uint64_t pp0_energy;
112 uint64_t pp1_energy;
113 uint64_t ddr_energy;
114 uint64_t llc_flushed_cycles;
115 uint64_t ring_ratio_instantaneous;
116 uint64_t IA_frequency_clipping_cause;
117 uint64_t GT_frequency_clipping_cause;
118 uint64_t pkg_idle_exits;
119 uint64_t pkg_rtimes[CPU_RTIME_BINS];
120 uint64_t pkg_itimes[CPU_ITIME_BINS];
121 uint64_t mbus_delay_time;
122 uint64_t mint_delay_time;
4b17d6b6
A
123 uint32_t ncpus;
124 core_energy_stat_t cest[];
125} pkg_energy_statistics_t;
126
db609669 127
0a7de745 128int
2d21ac55 129diagCall64(x86_saved_state_t * state)
0c530ab8 130{
0a7de745
A
131 uint64_t curpos, i, j;
132 uint64_t selector, data;
133 uint64_t currNap, durNap;
134 x86_saved_state64_t *regs;
135 boolean_t diagflag;
136 uint32_t rval = 0;
2d21ac55
A
137
138 assert(is_saved_state64(state));
139 regs = saved_state64(state);
39236c6e 140
db609669 141 diagflag = ((dgWork.dgFlags & enaDiagSCs) != 0);
2d21ac55
A
142 selector = regs->rdi;
143
0a7de745
A
144 switch (selector) { /* Select the routine */
145 case dgRuptStat: /* Suck Interruption statistics */
316670eb 146 (void) ml_set_interrupts_enabled(TRUE);
2d21ac55
A
147 data = regs->rsi; /* Get the number of processors */
148
149 if (data == 0) { /* If no location is specified for data, clear all
0a7de745
A
150 * counts
151 */
152 for (i = 0; i < real_ncpus; i++) { /* Cycle through
153 * processors */
154 for (j = 0; j < 256; j++) {
2d21ac55 155 cpu_data_ptr[i]->cpu_hwIntCnt[j] = 0;
0a7de745 156 }
2d21ac55
A
157 }
158
0a7de745
A
159 lastRuptClear = mach_absolute_time(); /* Get the time of clear */
160 rval = 1; /* Normal return */
3e170ce0 161 (void) ml_set_interrupts_enabled(FALSE);
4b17d6b6 162 break;
2d21ac55
A
163 }
164
0a7de745
A
165 (void) copyout((char *) &real_ncpus, data, sizeof(real_ncpus)); /* Copy out number of
166 * processors */
167 currNap = mach_absolute_time(); /* Get the time now */
168 durNap = currNap - lastRuptClear; /* Get the last interval
169 * duration */
170 if (durNap == 0) {
171 durNap = 1; /* This is a very short time, make it
172 * bigger */
173 }
174 curpos = data + sizeof(real_ncpus); /* Point to the next
175 * available spot */
176
177 for (i = 0; i < real_ncpus; i++) { /* Move 'em all out */
178 (void) copyout((char *) &durNap, curpos, 8); /* Copy out the time
179 * since last clear */
180 (void) copyout((char *) &cpu_data_ptr[i]->cpu_hwIntCnt, curpos + 8, 256 * sizeof(uint32_t)); /* Copy out interrupt
181 * data for this
182 * processor */
183 curpos = curpos + (256 * sizeof(uint32_t) + 8); /* Point to next out put
184 * slot */
2d21ac55 185 }
4b17d6b6 186 rval = 1;
3e170ce0 187 (void) ml_set_interrupts_enabled(FALSE);
2d21ac55 188 break;
39236c6e 189
4b17d6b6
A
190 case dgPowerStat:
191 {
192 uint32_t c2l = 0, c2h = 0, c3l = 0, c3h = 0, c6l = 0, c6h = 0, c7l = 0, c7h = 0;
193 uint32_t pkg_unit_l = 0, pkg_unit_h = 0, pkg_ecl = 0, pkg_ech = 0;
194
195 pkg_energy_statistics_t pkes;
196 core_energy_stat_t cest;
197
198 bzero(&pkes, sizeof(pkes));
199 bzero(&cest, sizeof(cest));
200
39236c6e 201 pkes.pkes_version = 1ULL;
4b17d6b6
A
202 rdmsr_carefully(MSR_IA32_PKG_C2_RESIDENCY, &c2l, &c2h);
203 rdmsr_carefully(MSR_IA32_PKG_C3_RESIDENCY, &c3l, &c3h);
204 rdmsr_carefully(MSR_IA32_PKG_C6_RESIDENCY, &c6l, &c6h);
205 rdmsr_carefully(MSR_IA32_PKG_C7_RESIDENCY, &c7l, &c7h);
206
207 pkes.pkg_cres[0][0] = ((uint64_t)c2h << 32) | c2l;
208 pkes.pkg_cres[0][1] = ((uint64_t)c3h << 32) | c3l;
209 pkes.pkg_cres[0][2] = ((uint64_t)c6h << 32) | c6l;
210 pkes.pkg_cres[0][3] = ((uint64_t)c7h << 32) | c7l;
211
bd504ef0
A
212 uint64_t c8r = ~0ULL, c9r = ~0ULL, c10r = ~0ULL;
213
fe8ab488
A
214 rdmsr64_carefully(MSR_IA32_PKG_C8_RESIDENCY, &c8r);
215 rdmsr64_carefully(MSR_IA32_PKG_C9_RESIDENCY, &c9r);
216 rdmsr64_carefully(MSR_IA32_PKG_C10_RESIDENCY, &c10r);
bd504ef0
A
217
218 pkes.pkg_cres[0][4] = c8r;
219 pkes.pkg_cres[0][5] = c9r;
220 pkes.pkg_cres[0][6] = c10r;
221
222 pkes.ddr_energy = ~0ULL;
223 rdmsr64_carefully(MSR_IA32_DDR_ENERGY_STATUS, &pkes.ddr_energy);
224 pkes.llc_flushed_cycles = ~0ULL;
225 rdmsr64_carefully(MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER, &pkes.llc_flushed_cycles);
226
227 pkes.ring_ratio_instantaneous = ~0ULL;
228 rdmsr64_carefully(MSR_IA32_RING_PERF_STATUS, &pkes.ring_ratio_instantaneous);
229
230 pkes.IA_frequency_clipping_cause = ~0ULL;
3e170ce0
A
231
232 uint32_t ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS;
2dced7af
A
233 /* Should perhaps be a generic register map module for these
234 * registers with identical functionality that were renumbered.
235 */
236 switch (cpuid_cpufamily()) {
237 case CPUFAMILY_INTEL_SKYLAKE:
5ba3f43e 238 case CPUFAMILY_INTEL_KABYLAKE:
2dced7af
A
239 ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS_SKL;
240 break;
241 default:
242 break;
243 }
3e170ce0
A
244
245 rdmsr64_carefully(ia_perf_limits, &pkes.IA_frequency_clipping_cause);
bd504ef0
A
246
247 pkes.GT_frequency_clipping_cause = ~0ULL;
248 rdmsr64_carefully(MSR_IA32_GT_PERF_LIMIT_REASONS, &pkes.GT_frequency_clipping_cause);
249
4b17d6b6
A
250 rdmsr_carefully(MSR_IA32_PKG_POWER_SKU_UNIT, &pkg_unit_l, &pkg_unit_h);
251 rdmsr_carefully(MSR_IA32_PKG_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
4b17d6b6
A
252 pkes.pkg_power_unit = ((uint64_t)pkg_unit_h << 32) | pkg_unit_l;
253 pkes.pkg_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
254
bd504ef0
A
255 rdmsr_carefully(MSR_IA32_PP0_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
256 pkes.pp0_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
257
258 rdmsr_carefully(MSR_IA32_PP1_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
259 pkes.pp1_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
260
261 pkes.pkg_idle_exits = current_cpu_datap()->lcpu.package->package_idle_exits;
4b17d6b6
A
262 pkes.ncpus = real_ncpus;
263
264 (void) ml_set_interrupts_enabled(TRUE);
265
266 copyout(&pkes, regs->rsi, sizeof(pkes));
267 curpos = regs->rsi + sizeof(pkes);
268
269 mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_powerstats, NULL);
0a7de745 270
4b17d6b6 271 for (i = 0; i < real_ncpus; i++) {
bd504ef0
A
272 (void) ml_set_interrupts_enabled(FALSE);
273
4b17d6b6
A
274 cest.caperf = cpu_data_ptr[i]->cpu_aperf;
275 cest.cmperf = cpu_data_ptr[i]->cpu_mperf;
276 cest.ccres[0] = cpu_data_ptr[i]->cpu_c3res;
277 cest.ccres[1] = cpu_data_ptr[i]->cpu_c6res;
278 cest.ccres[2] = cpu_data_ptr[i]->cpu_c7res;
279
280 bcopy(&cpu_data_ptr[i]->cpu_rtimes[0], &cest.crtimes[0], sizeof(cest.crtimes));
281 bcopy(&cpu_data_ptr[i]->cpu_itimes[0], &cest.citimes[0], sizeof(cest.citimes));
bd504ef0 282
4b17d6b6
A
283 cest.citime_total = cpu_data_ptr[i]->cpu_itime_total;
284 cest.crtime_total = cpu_data_ptr[i]->cpu_rtime_total;
5ba3f43e
A
285 cest.cpu_idle_exits = cpu_data_ptr[i]->cpu_idle_exits;
286#if MONOTONIC
287 cest.cpu_insns = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_INSTRS];
288 cest.cpu_ucc = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_CYCLES];
289 cest.cpu_urc = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_REFCYCLES];
290#endif /* MONOTONIC */
a1c7dba1
A
291#if DIAG_ALL_PMCS
292 bcopy(&cpu_data_ptr[i]->cpu_gpmcs[0], &cest.gpmcs[0], sizeof(cest.gpmcs));
3e170ce0 293#endif /* DIAG_ALL_PMCS */
5ba3f43e 294 (void) ml_set_interrupts_enabled(TRUE);
4b17d6b6
A
295
296 copyout(&cest, curpos, sizeof(cest));
297 curpos += sizeof(cest);
298 }
299 rval = 1;
3e170ce0 300 (void) ml_set_interrupts_enabled(FALSE);
4b17d6b6 301 }
0a7de745
A
302 break;
303 case dgEnaPMC:
304 {
305 boolean_t enable = TRUE;
39236c6e
A
306 uint32_t cpuinfo[4];
307 /* Require architectural PMC v2 or higher, corresponding to
308 * Merom+, or equivalent virtualised facility.
309 */
310 do_cpuid(0xA, &cpuinfo[0]);
311 if ((cpuinfo[0] & 0xFF) >= 2) {
312 mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_pmc_control, &enable);
313 diag_pmc_enabled = TRUE;
314 }
0a7de745
A
315 rval = 1;
316 }
317 break;
318#if DEVELOPMENT || DEBUG
316670eb
A
319 case dgGzallocTest:
320 {
321 (void) ml_set_interrupts_enabled(TRUE);
39236c6e
A
322 if (diagflag) {
323 unsigned *ptr = (unsigned *)kalloc(1024);
324 kfree(ptr, 1024);
325 *ptr = 0x42;
326 }
3e170ce0 327 (void) ml_set_interrupts_enabled(FALSE);
2d21ac55 328 }
bd504ef0 329 break;
316670eb 330#endif
2d21ac55 331
39037602 332#if DEVELOPMENT || DEBUG
0a7de745 333 case dgPermCheck:
316670eb
A
334 {
335 (void) ml_set_interrupts_enabled(TRUE);
0a7de745 336 if (diagflag) {
39236c6e 337 rval = pmap_permissions_verify(kernel_pmap, kernel_map, 0, ~0ULL);
0a7de745 338 }
3e170ce0 339 (void) ml_set_interrupts_enabled(FALSE);
0c530ab8 340 }
0a7de745 341 break;
39037602 342#endif /* DEVELOPMENT || DEBUG */
0a7de745
A
343 default: /* Handle invalid ones */
344 rval = 0; /* Return an exception */
0c530ab8
A
345 }
346
4b17d6b6
A
347 regs->rax = rval;
348
3e170ce0 349 assert(ml_get_interrupts_enabled() == FALSE);
39236c6e 350 return rval;
4b17d6b6
A
351}
352
0a7de745
A
353void
354cpu_powerstats(__unused void *arg)
355{
4b17d6b6 356 cpu_data_t *cdp = current_cpu_datap();
bd504ef0 357 __unused int cnum = cdp->cpu_number;
4b17d6b6
A
358 uint32_t cl = 0, ch = 0, mpl = 0, mph = 0, apl = 0, aph = 0;
359
360 rdmsr_carefully(MSR_IA32_MPERF, &mpl, &mph);
361 rdmsr_carefully(MSR_IA32_APERF, &apl, &aph);
362
363 cdp->cpu_mperf = ((uint64_t)mph << 32) | mpl;
364 cdp->cpu_aperf = ((uint64_t)aph << 32) | apl;
365
bd504ef0
A
366 uint64_t ctime = mach_absolute_time();
367 cdp->cpu_rtime_total += ctime - cdp->cpu_ixtime;
368 cdp->cpu_ixtime = ctime;
4b17d6b6
A
369
370 rdmsr_carefully(MSR_IA32_CORE_C3_RESIDENCY, &cl, &ch);
371 cdp->cpu_c3res = ((uint64_t)ch << 32) | cl;
372
373 rdmsr_carefully(MSR_IA32_CORE_C6_RESIDENCY, &cl, &ch);
374 cdp->cpu_c6res = ((uint64_t)ch << 32) | cl;
375
376 rdmsr_carefully(MSR_IA32_CORE_C7_RESIDENCY, &cl, &ch);
377 cdp->cpu_c7res = ((uint64_t)ch << 32) | cl;
39236c6e
A
378
379 if (diag_pmc_enabled) {
5ba3f43e
A
380#if MONOTONIC
381 mt_update_fixed_counts();
382#else /* MONOTONIC */
39236c6e
A
383 uint64_t insns = read_pmc(FIXED_PMC0);
384 uint64_t ucc = read_pmc(FIXED_PMC1);
385 uint64_t urc = read_pmc(FIXED_PMC2);
5ba3f43e 386#endif /* !MONOTONIC */
a1c7dba1
A
387#if DIAG_ALL_PMCS
388 int i;
389
390 for (i = 0; i < 4; i++) {
391 cdp->cpu_gpmcs[i] = read_pmc(i);
392 }
393#endif /* DIAG_ALL_PMCS */
5ba3f43e 394#if !MONOTONIC
39236c6e
A
395 cdp->cpu_cur_insns = insns;
396 cdp->cpu_cur_ucc = ucc;
397 cdp->cpu_cur_urc = urc;
5ba3f43e 398#endif /* !MONOTONIC */
39236c6e 399 }
bd504ef0
A
400}
401
0a7de745
A
402void
403cpu_pmc_control(void *enablep)
404{
5ba3f43e 405#if !MONOTONIC
bd504ef0 406 boolean_t enable = *(boolean_t *)enablep;
0a7de745 407 cpu_data_t *cdp = current_cpu_datap();
bd504ef0
A
408
409 if (enable) {
410 wrmsr64(0x38F, 0x70000000FULL);
411 wrmsr64(0x38D, 0x333);
412 set_cr4(get_cr4() | CR4_PCE);
bd504ef0
A
413 } else {
414 wrmsr64(0x38F, 0);
415 wrmsr64(0x38D, 0);
416 set_cr4((get_cr4() & ~CR4_PCE));
417 }
418 cdp->cpu_fixed_pmcs_enabled = enable;
5ba3f43e
A
419#else /* !MONOTONIC */
420#pragma unused(enablep)
421#endif /* MONOTONIC */
0c530ab8 422}