[apple/xnu.git] / osfmk / i386 / Diagnostics.c

/*
 * Copyright (c) 2005-2008 Apple Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
/*
 * @OSF_FREE_COPYRIGHT@
 */
/*
 * @APPLE_FREE_COPYRIGHT@
 */

/*
 *	Author: Bill Angell, Apple
 *	Date:	10/auht-five
 *
 *	Random diagnostics, augmented Derek Kumar 2011
 *
 *
 */


#include <kern/machine.h>
#include <kern/processor.h>
#include <mach/machine.h>
#include <mach/processor_info.h>
#include <mach/mach_types.h>
#include <mach/boolean.h>
#include <kern/thread.h>
#include <kern/task.h>
#include <kern/ipc_kobject.h>
#include <mach/vm_param.h>
#include <ipc/port.h>
#include <ipc/ipc_entry.h>
#include <ipc/ipc_space.h>
#include <ipc/ipc_object.h>
#include <ipc/ipc_port.h>
#include <vm/vm_kern.h>
#include <vm/vm_map.h>
#include <vm/vm_page.h>
#include <vm/pmap.h>
#include <pexpert/pexpert.h>
#include <console/video_console.h>
#include <i386/cpu_data.h>
#include <i386/Diagnostics.h>
#include <i386/mp.h>
#include <i386/pmCPU.h>
#include <i386/tsc.h>
#include <mach/i386/syscall_sw.h>
#include <kern/kalloc.h>
#include <sys/kdebug.h>
#include <i386/machine_cpu.h>
#include <i386/misc_protos.h>
#include <i386/cpuid.h>

#define PERMIT_PERMCHECK (0)

diagWork        dgWork;
uint64_t        lastRuptClear = 0ULL;
boolean_t	diag_pmc_enabled = FALSE;
void cpu_powerstats(void *);

typedef struct {
	uint64_t caperf;
	uint64_t cmperf;
	uint64_t ccres[6];
	uint64_t crtimes[CPU_RTIME_BINS];
	uint64_t citimes[CPU_ITIME_BINS];
	uint64_t crtime_total;
	uint64_t citime_total;
	uint64_t cpu_idle_exits;
	uint64_t cpu_insns;
	uint64_t cpu_ucc;
	uint64_t cpu_urc;
#if	DIAG_ALL_PMCS
	uint64_t gpmcs[4];
#endif /* DIAG_ALL_PMCS */
} core_energy_stat_t;

typedef struct {
	uint64_t pkes_version;
	uint64_t pkg_cres[2][7];
	uint64_t pkg_power_unit;
	uint64_t pkg_energy;
	uint64_t pp0_energy;
	uint64_t pp1_energy;
	uint64_t ddr_energy;
	uint64_t llc_flushed_cycles;
	uint64_t ring_ratio_instantaneous;
	uint64_t IA_frequency_clipping_cause;
	uint64_t GT_frequency_clipping_cause;
	uint64_t pkg_idle_exits;
	uint64_t pkg_rtimes[CPU_RTIME_BINS];
	uint64_t pkg_itimes[CPU_ITIME_BINS];
	uint64_t mbus_delay_time;
	uint64_t mint_delay_time;
	uint32_t ncpus;
	core_energy_stat_t cest[];
} pkg_energy_statistics_t;


int 
diagCall64(x86_saved_state_t * state)
{
	uint64_t	curpos, i, j;
	uint64_t	selector, data;
	uint64_t	currNap, durNap;
	x86_saved_state64_t	*regs;
	boolean_t 	diagflag;
	uint32_t	rval = 0;

	assert(is_saved_state64(state));
	regs = saved_state64(state);

	diagflag = ((dgWork.dgFlags & enaDiagSCs) != 0);
	selector = regs->rdi;

	switch (selector) {	/* Select the routine */
	case dgRuptStat:	/* Suck Interruption statistics */
		(void) ml_set_interrupts_enabled(TRUE);
		data = regs->rsi; /* Get the number of processors */

		if (data == 0) { /* If no location is specified for data, clear all
				  * counts
				  */
			for (i = 0; i < real_ncpus; i++) {	/* Cycle through
								 * processors */
				for (j = 0; j < 256; j++)
					cpu_data_ptr[i]->cpu_hwIntCnt[j] = 0;
			}

			lastRuptClear = mach_absolute_time();	/* Get the time of clear */
			rval = 1;	/* Normal return */
			(void) ml_set_interrupts_enabled(FALSE);
			break;
		}

		(void) copyout((char *) &real_ncpus, data, sizeof(real_ncpus));	/* Copy out number of
										 * processors */
		currNap = mach_absolute_time();	/* Get the time now */
		durNap = currNap - lastRuptClear;	/* Get the last interval
							 * duration */
		if (durNap == 0)
			durNap = 1;	/* This is a very short time, make it
					 * bigger */

		curpos = data + sizeof(real_ncpus);	/* Point to the next
							 * available spot */

		for (i = 0; i < real_ncpus; i++) {	/* Move 'em all out */
			(void) copyout((char *) &durNap, curpos, 8);	/* Copy out the time
									 * since last clear */
			(void) copyout((char *) &cpu_data_ptr[i]->cpu_hwIntCnt, curpos + 8, 256 * sizeof(uint32_t));	/* Copy out interrupt
															 * data for this
															 * processor */
			curpos = curpos + (256 * sizeof(uint32_t) + 8);	/* Point to next out put
									 * slot */
		}
		rval = 1;
		(void) ml_set_interrupts_enabled(FALSE);
		break;

	case dgPowerStat:
	{
		uint32_t c2l = 0, c2h = 0, c3l = 0, c3h = 0, c6l = 0, c6h = 0, c7l = 0, c7h = 0;
		uint32_t pkg_unit_l = 0, pkg_unit_h = 0, pkg_ecl = 0, pkg_ech = 0;

		pkg_energy_statistics_t pkes;
		core_energy_stat_t cest;

		bzero(&pkes, sizeof(pkes));
		bzero(&cest, sizeof(cest));

		pkes.pkes_version = 1ULL;
		rdmsr_carefully(MSR_IA32_PKG_C2_RESIDENCY, &c2l, &c2h);
		rdmsr_carefully(MSR_IA32_PKG_C3_RESIDENCY, &c3l, &c3h);
		rdmsr_carefully(MSR_IA32_PKG_C6_RESIDENCY, &c6l, &c6h);
		rdmsr_carefully(MSR_IA32_PKG_C7_RESIDENCY, &c7l, &c7h);

		pkes.pkg_cres[0][0] = ((uint64_t)c2h << 32) | c2l;
		pkes.pkg_cres[0][1] = ((uint64_t)c3h << 32) | c3l;
		pkes.pkg_cres[0][2] = ((uint64_t)c6h << 32) | c6l;
		pkes.pkg_cres[0][3] = ((uint64_t)c7h << 32) | c7l;

		uint64_t c8r = ~0ULL, c9r = ~0ULL, c10r = ~0ULL;

		rdmsr64_carefully(MSR_IA32_PKG_C8_RESIDENCY, &c8r);
		rdmsr64_carefully(MSR_IA32_PKG_C9_RESIDENCY, &c9r);
		rdmsr64_carefully(MSR_IA32_PKG_C10_RESIDENCY, &c10r);

		pkes.pkg_cres[0][4] = c8r;
		pkes.pkg_cres[0][5] = c9r;
		pkes.pkg_cres[0][6] = c10r;

		pkes.ddr_energy = ~0ULL;
		rdmsr64_carefully(MSR_IA32_DDR_ENERGY_STATUS, &pkes.ddr_energy);
		pkes.llc_flushed_cycles = ~0ULL;
		rdmsr64_carefully(MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER, &pkes.llc_flushed_cycles);

		pkes.ring_ratio_instantaneous = ~0ULL;
		rdmsr64_carefully(MSR_IA32_RING_PERF_STATUS, &pkes.ring_ratio_instantaneous);

		pkes.IA_frequency_clipping_cause = ~0ULL;

		uint32_t ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS;
		/* Should perhaps be a generic register map module for these
		 * registers with identical functionality that were renumbered.
		 */
		switch (cpuid_cpufamily()) {
		case CPUFAMILY_INTEL_SKYLAKE:
			ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS_SKL;
			break;
		default:
			break;
		}

		rdmsr64_carefully(ia_perf_limits, &pkes.IA_frequency_clipping_cause);

		pkes.GT_frequency_clipping_cause = ~0ULL;
		rdmsr64_carefully(MSR_IA32_GT_PERF_LIMIT_REASONS, &pkes.GT_frequency_clipping_cause);

		rdmsr_carefully(MSR_IA32_PKG_POWER_SKU_UNIT, &pkg_unit_l, &pkg_unit_h);
		rdmsr_carefully(MSR_IA32_PKG_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
		pkes.pkg_power_unit = ((uint64_t)pkg_unit_h << 32) | pkg_unit_l;
		pkes.pkg_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;

		rdmsr_carefully(MSR_IA32_PP0_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
		pkes.pp0_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;

		rdmsr_carefully(MSR_IA32_PP1_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
		pkes.pp1_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;

		pkes.pkg_idle_exits = current_cpu_datap()->lcpu.package->package_idle_exits;
		pkes.ncpus = real_ncpus;

		(void) ml_set_interrupts_enabled(TRUE);

		copyout(&pkes, regs->rsi, sizeof(pkes));
		curpos = regs->rsi + sizeof(pkes);

		mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_powerstats, NULL);
		
		for (i = 0; i < real_ncpus; i++) {
			(void) ml_set_interrupts_enabled(FALSE);

			cest.caperf = cpu_data_ptr[i]->cpu_aperf;
			cest.cmperf = cpu_data_ptr[i]->cpu_mperf;
			cest.ccres[0] = cpu_data_ptr[i]->cpu_c3res;
			cest.ccres[1] = cpu_data_ptr[i]->cpu_c6res;
			cest.ccres[2] = cpu_data_ptr[i]->cpu_c7res;

			bcopy(&cpu_data_ptr[i]->cpu_rtimes[0], &cest.crtimes[0], sizeof(cest.crtimes));
			bcopy(&cpu_data_ptr[i]->cpu_itimes[0], &cest.citimes[0], sizeof(cest.citimes));

			cest.citime_total = cpu_data_ptr[i]->cpu_itime_total;
			cest.crtime_total = cpu_data_ptr[i]->cpu_rtime_total;
 			cest.cpu_idle_exits = cpu_data_ptr[i]->cpu_idle_exits;
 			cest.cpu_insns = cpu_data_ptr[i]->cpu_cur_insns;
 			cest.cpu_ucc = cpu_data_ptr[i]->cpu_cur_ucc;
 			cest.cpu_urc = cpu_data_ptr[i]->cpu_cur_urc;
#if DIAG_ALL_PMCS
			bcopy(&cpu_data_ptr[i]->cpu_gpmcs[0], &cest.gpmcs[0], sizeof(cest.gpmcs));
#endif /* DIAG_ALL_PMCS */
 			(void) ml_set_interrupts_enabled(TRUE);

			copyout(&cest, curpos, sizeof(cest));
			curpos += sizeof(cest);
		}
		rval = 1;
		(void) ml_set_interrupts_enabled(FALSE);
	}
		break;
 	case dgEnaPMC:
 	{
 		boolean_t enable = TRUE;
		uint32_t cpuinfo[4];
		/* Require architectural PMC v2 or higher, corresponding to
		 * Merom+, or equivalent virtualised facility.
		 */
		do_cpuid(0xA, &cpuinfo[0]);
		if ((cpuinfo[0] & 0xFF) >= 2) {
			mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_pmc_control, &enable);
			diag_pmc_enabled = TRUE;
		}
 		rval = 1;
 	}
 	break;
#if	DEBUG
	case dgGzallocTest:
	{
		(void) ml_set_interrupts_enabled(TRUE);
		if (diagflag) {
			unsigned *ptr = (unsigned *)kalloc(1024);
			kfree(ptr, 1024);
			*ptr = 0x42;
		}
		(void) ml_set_interrupts_enabled(FALSE);
	}
	break;
#endif

#if PERMIT_PERMCHECK	
	case	dgPermCheck:
	{
		(void) ml_set_interrupts_enabled(TRUE);
		if (diagflag)
			rval = pmap_permissions_verify(kernel_pmap, kernel_map, 0, ~0ULL);
		(void) ml_set_interrupts_enabled(FALSE);
	}
 		break;
#endif /* PERMIT_PERMCHECK */
	default:		/* Handle invalid ones */
		rval = 0;	/* Return an exception */
	}

	regs->rax = rval;

	assert(ml_get_interrupts_enabled() == FALSE);
	return rval;
}

void cpu_powerstats(__unused void *arg) {
	cpu_data_t *cdp = current_cpu_datap();
	__unused int cnum = cdp->cpu_number;
	uint32_t cl = 0, ch = 0, mpl = 0, mph = 0, apl = 0, aph = 0;

	rdmsr_carefully(MSR_IA32_MPERF, &mpl, &mph);
	rdmsr_carefully(MSR_IA32_APERF, &apl, &aph);

	cdp->cpu_mperf = ((uint64_t)mph << 32) | mpl;
	cdp->cpu_aperf = ((uint64_t)aph << 32) | apl;

	uint64_t ctime = mach_absolute_time();
	cdp->cpu_rtime_total += ctime - cdp->cpu_ixtime;
	cdp->cpu_ixtime = ctime;

	rdmsr_carefully(MSR_IA32_CORE_C3_RESIDENCY, &cl, &ch);
	cdp->cpu_c3res = ((uint64_t)ch << 32) | cl;

	rdmsr_carefully(MSR_IA32_CORE_C6_RESIDENCY, &cl, &ch);
	cdp->cpu_c6res = ((uint64_t)ch << 32) | cl;

	rdmsr_carefully(MSR_IA32_CORE_C7_RESIDENCY, &cl, &ch);
	cdp->cpu_c7res = ((uint64_t)ch << 32) | cl;

	if (diag_pmc_enabled) {
		uint64_t insns = read_pmc(FIXED_PMC0);
		uint64_t ucc = read_pmc(FIXED_PMC1);
		uint64_t urc = read_pmc(FIXED_PMC2);
#if DIAG_ALL_PMCS
		int i;

		for (i = 0; i < 4; i++) {
			cdp->cpu_gpmcs[i] = read_pmc(i);
		}
#endif /* DIAG_ALL_PMCS */
		cdp->cpu_cur_insns = insns;
		cdp->cpu_cur_ucc = ucc;
		cdp->cpu_cur_urc = urc;
	}
}

void cpu_pmc_control(void *enablep) {
	boolean_t enable = *(boolean_t *)enablep;
	cpu_data_t	*cdp = current_cpu_datap();

	if (enable) {
		wrmsr64(0x38F, 0x70000000FULL);
		wrmsr64(0x38D, 0x333);
		set_cr4(get_cr4() | CR4_PCE);

	} else {
		wrmsr64(0x38F, 0);
		wrmsr64(0x38D, 0);
		set_cr4((get_cr4() & ~CR4_PCE));
	}
	cdp->cpu_fixed_pmcs_enabled = enable;
}
Commit	Line	Data
0c530ab8	1	/*
593a1d5f	2	* Copyright (c) 2005-2008 Apple Inc. All rights reserved.
0c530ab8	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
0c530ab8	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
0c530ab8	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
0c530ab8 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
0c530ab8 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
0c530ab8	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
0c530ab8 A	27	*/
	28	/*
	29	* @OSF_FREE_COPYRIGHT@
	30	*/
	31	/*
	32	* @APPLE_FREE_COPYRIGHT@
	33	*/
	34
	35	/*
	36	* Author: Bill Angell, Apple
	37	* Date: 10/auht-five
	38	*
316670eb	39	* Random diagnostics, augmented Derek Kumar 2011
0c530ab8	40	*
0c530ab8 A	41	*
	42	*/
	43
	44
	45	#include <kern/machine.h>
	46	#include <kern/processor.h>
	47	#include <mach/machine.h>
	48	#include <mach/processor_info.h>
	49	#include <mach/mach_types.h>
	50	#include <mach/boolean.h>
	51	#include <kern/thread.h>
	52	#include <kern/task.h>
	53	#include <kern/ipc_kobject.h>
	54	#include <mach/vm_param.h>
	55	#include <ipc/port.h>
	56	#include <ipc/ipc_entry.h>
	57	#include <ipc/ipc_space.h>
	58	#include <ipc/ipc_object.h>
	59	#include <ipc/ipc_port.h>
	60	#include <vm/vm_kern.h>
	61	#include <vm/vm_map.h>
	62	#include <vm/vm_page.h>
	63	#include <vm/pmap.h>
	64	#include <pexpert/pexpert.h>
	65	#include <console/video_console.h>
	66	#include <i386/cpu_data.h>
	67	#include <i386/Diagnostics.h>
	68	#include <i386/mp.h>
	69	#include <i386/pmCPU.h>
	70	#include <i386/tsc.h>
0c530ab8	71	#include <mach/i386/syscall_sw.h>
316670eb	72	#include <kern/kalloc.h>
db609669	73	#include <sys/kdebug.h>
bd504ef0 A	74	#include <i386/machine_cpu.h>
	75	#include <i386/misc_protos.h>
	76	#include <i386/cpuid.h>
	77
	78	#define PERMIT_PERMCHECK (0)
	79
0c530ab8	80	diagWork dgWork;
0c530ab8	81	uint64_t lastRuptClear = 0ULL;
39236c6e	82	boolean_t diag_pmc_enabled = FALSE;
4b17d6b6 A	83	void cpu_powerstats(void *);
	84
	85	typedef struct {
	86	uint64_t caperf;
	87	uint64_t cmperf;
bd504ef0 A	88	uint64_t ccres[6];
	89	uint64_t crtimes[CPU_RTIME_BINS];
	90	uint64_t citimes[CPU_ITIME_BINS];
4b17d6b6 A	91	uint64_t crtime_total;
4b17d6b6 A	92	uint64_t citime_total;
bd504ef0 A	93	uint64_t cpu_idle_exits;
	94	uint64_t cpu_insns;
	95	uint64_t cpu_ucc;
	96	uint64_t cpu_urc;
a1c7dba1 A	97	#if DIAG_ALL_PMCS
	98	uint64_t gpmcs[4];
	99	#endif /* DIAG_ALL_PMCS */
4b17d6b6 A	100	} core_energy_stat_t;
	101
	102	typedef struct {
39236c6e	103	uint64_t pkes_version;
bd504ef0	104	uint64_t pkg_cres[2][7];
4b17d6b6 A	105	uint64_t pkg_power_unit;
4b17d6b6 A	106	uint64_t pkg_energy;
bd504ef0 A	107	uint64_t pp0_energy;
	108	uint64_t pp1_energy;
	109	uint64_t ddr_energy;
	110	uint64_t llc_flushed_cycles;
	111	uint64_t ring_ratio_instantaneous;
	112	uint64_t IA_frequency_clipping_cause;
	113	uint64_t GT_frequency_clipping_cause;
	114	uint64_t pkg_idle_exits;
	115	uint64_t pkg_rtimes[CPU_RTIME_BINS];
	116	uint64_t pkg_itimes[CPU_ITIME_BINS];
	117	uint64_t mbus_delay_time;
	118	uint64_t mint_delay_time;
4b17d6b6 A	119	uint32_t ncpus;
	120	core_energy_stat_t cest[];
	121	} pkg_energy_statistics_t;
	122
db609669	123
0c530ab8	124	int
2d21ac55	125	diagCall64(x86_saved_state_t * state)
0c530ab8	126	{
bd504ef0 A	127	uint64_t curpos, i, j;
	128	uint64_t selector, data;
	129	uint64_t currNap, durNap;
2d21ac55	130	x86_saved_state64_t *regs;
db609669	131	boolean_t diagflag;
4b17d6b6	132	uint32_t rval = 0;
2d21ac55 A	133
	134	assert(is_saved_state64(state));
	135	regs = saved_state64(state);
39236c6e	136
db609669	137	diagflag = ((dgWork.dgFlags & enaDiagSCs) != 0);
2d21ac55 A	138	selector = regs->rdi;
	139
	140	switch (selector) { /* Select the routine */
	141	case dgRuptStat: /* Suck Interruption statistics */
316670eb	142	(void) ml_set_interrupts_enabled(TRUE);
2d21ac55 A	143	data = regs->rsi; /* Get the number of processors */
	144
	145	if (data == 0) { /* If no location is specified for data, clear all
	146	* counts
	147	*/
	148	for (i = 0; i < real_ncpus; i++) { /* Cycle through
	149	* processors */
	150	for (j = 0; j < 256; j++)
	151	cpu_data_ptr[i]->cpu_hwIntCnt[j] = 0;
	152	}
	153
	154	lastRuptClear = mach_absolute_time(); /* Get the time of clear */
4b17d6b6	155	rval = 1; /* Normal return */
3e170ce0	156	(void) ml_set_interrupts_enabled(FALSE);
4b17d6b6	157	break;
2d21ac55 A	158	}
	159
	160	(void) copyout((char ) &real_ncpus, data, sizeof(real_ncpus)); / Copy out number of
	161	* processors */
2d21ac55 A	162	currNap = mach_absolute_time(); /* Get the time now */
	163	durNap = currNap - lastRuptClear; /* Get the last interval
	164	* duration */
	165	if (durNap == 0)
	166	durNap = 1; /* This is a very short time, make it
	167	* bigger */
	168
	169	curpos = data + sizeof(real_ncpus); /* Point to the next
	170	* available spot */
	171
	172	for (i = 0; i < real_ncpus; i++) { /* Move 'em all out */
	173	(void) copyout((char ) &durNap, curpos, 8); / Copy out the time
	174	* since last clear */
	175	(void) copyout((char ) &cpu_data_ptr[i]->cpu_hwIntCnt, curpos + 8, 256 sizeof(uint32_t)); /* Copy out interrupt
	176	* data for this
	177	* processor */
	178	curpos = curpos + (256 * sizeof(uint32_t) + 8); /* Point to next out put
	179	* slot */
	180	}
4b17d6b6	181	rval = 1;
3e170ce0	182	(void) ml_set_interrupts_enabled(FALSE);
2d21ac55	183	break;
39236c6e	184
4b17d6b6 A	185	case dgPowerStat:
	186	{
	187	uint32_t c2l = 0, c2h = 0, c3l = 0, c3h = 0, c6l = 0, c6h = 0, c7l = 0, c7h = 0;
	188	uint32_t pkg_unit_l = 0, pkg_unit_h = 0, pkg_ecl = 0, pkg_ech = 0;
	189
	190	pkg_energy_statistics_t pkes;
	191	core_energy_stat_t cest;
	192
	193	bzero(&pkes, sizeof(pkes));
	194	bzero(&cest, sizeof(cest));
	195
39236c6e	196	pkes.pkes_version = 1ULL;
4b17d6b6 A	197	rdmsr_carefully(MSR_IA32_PKG_C2_RESIDENCY, &c2l, &c2h);
	198	rdmsr_carefully(MSR_IA32_PKG_C3_RESIDENCY, &c3l, &c3h);
	199	rdmsr_carefully(MSR_IA32_PKG_C6_RESIDENCY, &c6l, &c6h);
	200	rdmsr_carefully(MSR_IA32_PKG_C7_RESIDENCY, &c7l, &c7h);
	201
	202	pkes.pkg_cres[0][0] = ((uint64_t)c2h << 32) \| c2l;
	203	pkes.pkg_cres[0][1] = ((uint64_t)c3h << 32) \| c3l;
	204	pkes.pkg_cres[0][2] = ((uint64_t)c6h << 32) \| c6l;
	205	pkes.pkg_cres[0][3] = ((uint64_t)c7h << 32) \| c7l;
	206
bd504ef0 A	207	uint64_t c8r = ~0ULL, c9r = ~0ULL, c10r = ~0ULL;
bd504ef0 A	208
fe8ab488 A	209	rdmsr64_carefully(MSR_IA32_PKG_C8_RESIDENCY, &c8r);
	210	rdmsr64_carefully(MSR_IA32_PKG_C9_RESIDENCY, &c9r);
	211	rdmsr64_carefully(MSR_IA32_PKG_C10_RESIDENCY, &c10r);
bd504ef0 A	212
	213	pkes.pkg_cres[0][4] = c8r;
	214	pkes.pkg_cres[0][5] = c9r;
	215	pkes.pkg_cres[0][6] = c10r;
	216
	217	pkes.ddr_energy = ~0ULL;
	218	rdmsr64_carefully(MSR_IA32_DDR_ENERGY_STATUS, &pkes.ddr_energy);
	219	pkes.llc_flushed_cycles = ~0ULL;
	220	rdmsr64_carefully(MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER, &pkes.llc_flushed_cycles);
	221
	222	pkes.ring_ratio_instantaneous = ~0ULL;
	223	rdmsr64_carefully(MSR_IA32_RING_PERF_STATUS, &pkes.ring_ratio_instantaneous);
	224
	225	pkes.IA_frequency_clipping_cause = ~0ULL;
3e170ce0 A	226
3e170ce0 A	227	uint32_t ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS;
2dced7af A	228	/* Should perhaps be a generic register map module for these
	229	* registers with identical functionality that were renumbered.
	230	*/
	231	switch (cpuid_cpufamily()) {
	232	case CPUFAMILY_INTEL_SKYLAKE:
	233	ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS_SKL;
	234	break;
	235	default:
	236	break;
	237	}
3e170ce0 A	238
3e170ce0 A	239	rdmsr64_carefully(ia_perf_limits, &pkes.IA_frequency_clipping_cause);
bd504ef0 A	240
	241	pkes.GT_frequency_clipping_cause = ~0ULL;
	242	rdmsr64_carefully(MSR_IA32_GT_PERF_LIMIT_REASONS, &pkes.GT_frequency_clipping_cause);
	243
4b17d6b6 A	244	rdmsr_carefully(MSR_IA32_PKG_POWER_SKU_UNIT, &pkg_unit_l, &pkg_unit_h);
4b17d6b6 A	245	rdmsr_carefully(MSR_IA32_PKG_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
4b17d6b6 A	246	pkes.pkg_power_unit = ((uint64_t)pkg_unit_h << 32) \| pkg_unit_l;
	247	pkes.pkg_energy = ((uint64_t)pkg_ech << 32) \| pkg_ecl;
	248
bd504ef0 A	249	rdmsr_carefully(MSR_IA32_PP0_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
	250	pkes.pp0_energy = ((uint64_t)pkg_ech << 32) \| pkg_ecl;
	251
	252	rdmsr_carefully(MSR_IA32_PP1_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
	253	pkes.pp1_energy = ((uint64_t)pkg_ech << 32) \| pkg_ecl;
	254
	255	pkes.pkg_idle_exits = current_cpu_datap()->lcpu.package->package_idle_exits;
4b17d6b6 A	256	pkes.ncpus = real_ncpus;
	257
	258	(void) ml_set_interrupts_enabled(TRUE);
	259
	260	copyout(&pkes, regs->rsi, sizeof(pkes));
	261	curpos = regs->rsi + sizeof(pkes);
	262
	263	mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_powerstats, NULL);
	264
	265	for (i = 0; i < real_ncpus; i++) {
bd504ef0 A	266	(void) ml_set_interrupts_enabled(FALSE);
bd504ef0 A	267
4b17d6b6 A	268	cest.caperf = cpu_data_ptr[i]->cpu_aperf;
	269	cest.cmperf = cpu_data_ptr[i]->cpu_mperf;
	270	cest.ccres[0] = cpu_data_ptr[i]->cpu_c3res;
	271	cest.ccres[1] = cpu_data_ptr[i]->cpu_c6res;
	272	cest.ccres[2] = cpu_data_ptr[i]->cpu_c7res;
	273
	274	bcopy(&cpu_data_ptr[i]->cpu_rtimes[0], &cest.crtimes[0], sizeof(cest.crtimes));
	275	bcopy(&cpu_data_ptr[i]->cpu_itimes[0], &cest.citimes[0], sizeof(cest.citimes));
bd504ef0	276
4b17d6b6 A	277	cest.citime_total = cpu_data_ptr[i]->cpu_itime_total;
4b17d6b6 A	278	cest.crtime_total = cpu_data_ptr[i]->cpu_rtime_total;
bd504ef0 A	279	cest.cpu_idle_exits = cpu_data_ptr[i]->cpu_idle_exits;
	280	cest.cpu_insns = cpu_data_ptr[i]->cpu_cur_insns;
	281	cest.cpu_ucc = cpu_data_ptr[i]->cpu_cur_ucc;
	282	cest.cpu_urc = cpu_data_ptr[i]->cpu_cur_urc;
a1c7dba1 A	283	#if DIAG_ALL_PMCS
a1c7dba1 A	284	bcopy(&cpu_data_ptr[i]->cpu_gpmcs[0], &cest.gpmcs[0], sizeof(cest.gpmcs));
3e170ce0	285	#endif /* DIAG_ALL_PMCS */
bd504ef0	286	(void) ml_set_interrupts_enabled(TRUE);
4b17d6b6 A	287
	288	copyout(&cest, curpos, sizeof(cest));
	289	curpos += sizeof(cest);
	290	}
	291	rval = 1;
3e170ce0	292	(void) ml_set_interrupts_enabled(FALSE);
4b17d6b6 A	293	}
4b17d6b6 A	294	break;
bd504ef0 A	295	case dgEnaPMC:
	296	{
	297	boolean_t enable = TRUE;
39236c6e A	298	uint32_t cpuinfo[4];
	299	/* Require architectural PMC v2 or higher, corresponding to
	300	* Merom+, or equivalent virtualised facility.
	301	*/
	302	do_cpuid(0xA, &cpuinfo[0]);
	303	if ((cpuinfo[0] & 0xFF) >= 2) {
	304	mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_pmc_control, &enable);
	305	diag_pmc_enabled = TRUE;
	306	}
bd504ef0 A	307	rval = 1;
	308	}
	309	break;
316670eb A	310	#if DEBUG
	311	case dgGzallocTest:
	312	{
	313	(void) ml_set_interrupts_enabled(TRUE);
39236c6e A	314	if (diagflag) {
	315	unsigned ptr = (unsigned )kalloc(1024);
	316	kfree(ptr, 1024);
	317	*ptr = 0x42;
	318	}
3e170ce0	319	(void) ml_set_interrupts_enabled(FALSE);
2d21ac55	320	}
bd504ef0	321	break;
316670eb	322	#endif
2d21ac55	323
bd504ef0	324	#if PERMIT_PERMCHECK
316670eb A	325	case dgPermCheck:
	326	{
	327	(void) ml_set_interrupts_enabled(TRUE);
39236c6e A	328	if (diagflag)
39236c6e A	329	rval = pmap_permissions_verify(kernel_pmap, kernel_map, 0, ~0ULL);
3e170ce0	330	(void) ml_set_interrupts_enabled(FALSE);
0c530ab8	331	}
316670eb	332	break;
bd504ef0	333	#endif /* PERMIT_PERMCHECK */
0c530ab8	334	default: /* Handle invalid ones */
4b17d6b6	335	rval = 0; /* Return an exception */
0c530ab8 A	336	}
0c530ab8 A	337
4b17d6b6 A	338	regs->rax = rval;
4b17d6b6 A	339
3e170ce0	340	assert(ml_get_interrupts_enabled() == FALSE);
39236c6e	341	return rval;
4b17d6b6 A	342	}
	343
	344	void cpu_powerstats(__unused void *arg) {
	345	cpu_data_t *cdp = current_cpu_datap();
bd504ef0	346	__unused int cnum = cdp->cpu_number;
4b17d6b6 A	347	uint32_t cl = 0, ch = 0, mpl = 0, mph = 0, apl = 0, aph = 0;
	348
	349	rdmsr_carefully(MSR_IA32_MPERF, &mpl, &mph);
	350	rdmsr_carefully(MSR_IA32_APERF, &apl, &aph);
	351
	352	cdp->cpu_mperf = ((uint64_t)mph << 32) \| mpl;
	353	cdp->cpu_aperf = ((uint64_t)aph << 32) \| apl;
	354
bd504ef0 A	355	uint64_t ctime = mach_absolute_time();
	356	cdp->cpu_rtime_total += ctime - cdp->cpu_ixtime;
	357	cdp->cpu_ixtime = ctime;
4b17d6b6 A	358
	359	rdmsr_carefully(MSR_IA32_CORE_C3_RESIDENCY, &cl, &ch);
	360	cdp->cpu_c3res = ((uint64_t)ch << 32) \| cl;
	361
	362	rdmsr_carefully(MSR_IA32_CORE_C6_RESIDENCY, &cl, &ch);
	363	cdp->cpu_c6res = ((uint64_t)ch << 32) \| cl;
	364
	365	rdmsr_carefully(MSR_IA32_CORE_C7_RESIDENCY, &cl, &ch);
	366	cdp->cpu_c7res = ((uint64_t)ch << 32) \| cl;
39236c6e A	367
	368	if (diag_pmc_enabled) {
	369	uint64_t insns = read_pmc(FIXED_PMC0);
	370	uint64_t ucc = read_pmc(FIXED_PMC1);
	371	uint64_t urc = read_pmc(FIXED_PMC2);
a1c7dba1 A	372	#if DIAG_ALL_PMCS
	373	int i;
	374
	375	for (i = 0; i < 4; i++) {
	376	cdp->cpu_gpmcs[i] = read_pmc(i);
	377	}
	378	#endif /* DIAG_ALL_PMCS */
39236c6e A	379	cdp->cpu_cur_insns = insns;
	380	cdp->cpu_cur_ucc = ucc;
	381	cdp->cpu_cur_urc = urc;
	382	}
bd504ef0 A	383	}
	384
	385	void cpu_pmc_control(void *enablep) {
	386	boolean_t enable = (boolean_t )enablep;
	387	cpu_data_t *cdp = current_cpu_datap();
	388
	389	if (enable) {
	390	wrmsr64(0x38F, 0x70000000FULL);
	391	wrmsr64(0x38D, 0x333);
	392	set_cr4(get_cr4() \| CR4_PCE);
	393
	394	} else {
	395	wrmsr64(0x38F, 0);
	396	wrmsr64(0x38D, 0);
	397	set_cr4((get_cr4() & ~CR4_PCE));
	398	}
	399	cdp->cpu_fixed_pmcs_enabled = enable;
0c530ab8	400	}