[apple/xnu.git] / osfmk / ppc / machine_routines.c

/*
 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * The contents of this file constitute Original Code as defined in and
 * are subject to the Apple Public Source License Version 1.1 (the
 * "License").  You may not use this file except in compliance with the
 * License.  Please obtain a copy of the License at
 * http://www.apple.com/publicsource and read it before using this file.
 * 
 * This Original Code and all software distributed under the License are
 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
 * License for the specific language governing rights and limitations
 * under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
#include <ppc/machine_routines.h>
#include <ppc/machine_cpu.h>
#include <ppc/exception.h>
#include <ppc/misc_protos.h>
#include <ppc/Firmware.h>
#include <vm/vm_page.h>
#include <ppc/pmap.h>
#include <ppc/proc_reg.h>
#include <kern/processor.h>

unsigned int max_cpus_initialized = 0;
unsigned int LockTimeOut = 12500000;
unsigned int MutexSpin = 0;
extern int forcenap;

#define	MAX_CPUS_SET	0x1
#define	MAX_CPUS_WAIT	0x2

boolean_t get_interrupts_enabled(void);

/* Map memory map IO space */
vm_offset_t 
ml_io_map(
	vm_offset_t phys_addr, 
	vm_size_t size)
{
	return(io_map(phys_addr,size));
}

/* static memory allocation */
vm_offset_t 
ml_static_malloc(
	vm_size_t size)
{
	extern vm_offset_t static_memory_end;
	extern boolean_t pmap_initialized;
	vm_offset_t vaddr;

	if (pmap_initialized)
		return((vm_offset_t)NULL);
	else {
		vaddr = static_memory_end;
		static_memory_end = round_page_32(vaddr+size);
		return(vaddr);
	}
}

vm_offset_t
ml_static_ptovirt(
	vm_offset_t paddr)
{
	extern vm_offset_t static_memory_end;
	vm_offset_t vaddr;

	/* Static memory is map V=R */
	vaddr = paddr;
	if ( (vaddr < static_memory_end) && (pmap_extract(kernel_pmap, vaddr)==paddr) )
		return(vaddr);
	else
		return((vm_offset_t)NULL);
}

void
ml_static_mfree(
	vm_offset_t vaddr,
	vm_size_t size)
{
	vm_offset_t paddr_cur, vaddr_cur;

	for (vaddr_cur = round_page_32(vaddr);
	     vaddr_cur < trunc_page_32(vaddr+size);
	     vaddr_cur += PAGE_SIZE) {
		paddr_cur = pmap_extract(kernel_pmap, vaddr_cur);
		if (paddr_cur != (vm_offset_t)NULL) {
			vm_page_wire_count--;
			pmap_remove(kernel_pmap, (addr64_t)vaddr_cur, (addr64_t)(vaddr_cur+PAGE_SIZE));
			vm_page_create(paddr_cur>>12,(paddr_cur+PAGE_SIZE)>>12);
		}
	}
}

/* virtual to physical on wired pages */
vm_offset_t ml_vtophys(
	vm_offset_t vaddr)
{
	return(pmap_extract(kernel_pmap, vaddr));
}

/* Initialize Interrupt Handler */
void ml_install_interrupt_handler(
	void *nub,
	int source,
	void *target,
	IOInterruptHandler handler,
	void *refCon)
{
	int	current_cpu;
	boolean_t current_state;

	current_cpu = cpu_number();
	current_state = ml_get_interrupts_enabled();

	per_proc_info[current_cpu].interrupt_nub     = nub;
	per_proc_info[current_cpu].interrupt_source  = source;
	per_proc_info[current_cpu].interrupt_target  = target;
	per_proc_info[current_cpu].interrupt_handler = handler;
	per_proc_info[current_cpu].interrupt_refCon  = refCon;

	per_proc_info[current_cpu].interrupts_enabled = TRUE;  
	(void) ml_set_interrupts_enabled(current_state);

	initialize_screen(0, kPEAcquireScreen);
}

/* Initialize Interrupts */
void ml_init_interrupt(void)
{
	int	current_cpu;
	boolean_t current_state;

	current_state = ml_get_interrupts_enabled();

	current_cpu = cpu_number();
	per_proc_info[current_cpu].interrupts_enabled = TRUE;  
	(void) ml_set_interrupts_enabled(current_state);
}

/* Get Interrupts Enabled */
boolean_t ml_get_interrupts_enabled(void)
{
	return((mfmsr() & MASK(MSR_EE)) != 0);
}

/* Check if running at interrupt context */
boolean_t ml_at_interrupt_context(void)
{
	boolean_t	ret;
	boolean_t	current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
 	ret = (per_proc_info[cpu_number()].istackptr == 0);	
	ml_set_interrupts_enabled(current_state);
	return(ret);
}

/* Generate a fake interrupt */
void ml_cause_interrupt(void)
{
	CreateFakeIO();
}

void ml_thread_policy(
	thread_t thread,
	unsigned policy_id,
	unsigned policy_info)
{
        extern int srv;

	if ((policy_id == MACHINE_GROUP) &&
		((per_proc_info[0].pf.Available) & pfSMPcap))
			thread_bind(thread, master_processor);

	if (policy_info & MACHINE_NETWORK_WORKLOOP) {
		spl_t		s = splsched();

		thread_lock(thread);

		if (srv == 0)
		        thread->sched_mode |= TH_MODE_FORCEDPREEMPT;
		set_priority(thread, thread->priority + 1);

		thread_unlock(thread);
		splx(s);
	}
}

void machine_idle(void)
{
        if (per_proc_info[cpu_number()].interrupts_enabled == TRUE) {
	        int cur_decr;

	        machine_idle_ppc();

		/*
		 * protect against a lost decrementer trap
		 * if the current decrementer value is negative
		 * by more than 10 ticks, re-arm it since it's 
		 * unlikely to fire at this point... a hardware
		 * interrupt got us out of machine_idle and may
		 * also be contributing to this state
		 */
		cur_decr = isync_mfdec();

		if (cur_decr < -10) {
		        mtdec(1);
		}
	}
}

void
machine_signal_idle(
	processor_t processor)
{
	if (per_proc_info[processor->slot_num].pf.Available & (pfCanDoze|pfWillNap))
		(void)cpu_signal(processor->slot_num, SIGPwake, 0, 0);
}

kern_return_t
ml_processor_register(
	ml_processor_info_t *processor_info,
	processor_t	    *processor,
	ipi_handler_t       *ipi_handler)
{
	kern_return_t ret;
	int target_cpu, cpu;
	int donap;

	if (processor_info->boot_cpu == FALSE) {
		 if (cpu_register(&target_cpu) != KERN_SUCCESS)
			return KERN_FAILURE;
	} else {
		/* boot_cpu is always 0 */
		target_cpu = 0;
	}

	per_proc_info[target_cpu].cpu_id = processor_info->cpu_id;
	per_proc_info[target_cpu].start_paddr = processor_info->start_paddr;

	donap = processor_info->supports_nap;		/* Assume we use requested nap */
	if(forcenap) donap = forcenap - 1;			/* If there was an override, use that */
	
	if(per_proc_info[target_cpu].pf.Available & pfCanNap)
	  if(donap) 
		per_proc_info[target_cpu].pf.Available |= pfWillNap;

	if(processor_info->time_base_enable !=  (void(*)(cpu_id_t, boolean_t ))NULL)
		per_proc_info[target_cpu].time_base_enable = processor_info->time_base_enable;
	else
		per_proc_info[target_cpu].time_base_enable = (void(*)(cpu_id_t, boolean_t ))NULL;
	
	if(target_cpu == cpu_number()) 
		__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available));	/* Set live value */

	*processor = cpu_to_processor(target_cpu);
	*ipi_handler = cpu_signal_handler;

	return KERN_SUCCESS;
}

boolean_t
ml_enable_nap(int target_cpu, boolean_t nap_enabled)
{
    boolean_t prev_value = (per_proc_info[target_cpu].pf.Available & pfCanNap) && (per_proc_info[target_cpu].pf.Available & pfWillNap);
    
 	if(forcenap) nap_enabled = forcenap - 1;		/* If we are to force nap on or off, do it */
 
 	if(per_proc_info[target_cpu].pf.Available & pfCanNap) {				/* Can the processor nap? */
		if (nap_enabled) per_proc_info[target_cpu].pf.Available |= pfWillNap;	/* Is nap supported on this machine? */
		else per_proc_info[target_cpu].pf.Available &= ~pfWillNap;		/* Clear if not */
	}

	if(target_cpu == cpu_number()) 
		__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available));	/* Set live value */
 
    return (prev_value);
}

void
ml_init_max_cpus(unsigned long max_cpus)
{
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
	if (max_cpus_initialized != MAX_CPUS_SET) {
		if (max_cpus > 0 && max_cpus < NCPUS)
			machine_info.max_cpus = max_cpus;
		if (max_cpus_initialized == MAX_CPUS_WAIT)
			wakeup((event_t)&max_cpus_initialized);
		max_cpus_initialized = MAX_CPUS_SET;
	}
	(void) ml_set_interrupts_enabled(current_state);
}

int
ml_get_max_cpus(void)
{
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
	if (max_cpus_initialized != MAX_CPUS_SET) {
		max_cpus_initialized = MAX_CPUS_WAIT;
		assert_wait((event_t)&max_cpus_initialized, THREAD_UNINT);
		(void)thread_block(THREAD_CONTINUE_NULL);
	}
	(void) ml_set_interrupts_enabled(current_state);
	return(machine_info.max_cpus);
}

void
ml_cpu_get_info(ml_cpu_info_t *cpu_info)
{
  if (cpu_info == 0) return;
  
  cpu_info->vector_unit = (per_proc_info[0].pf.Available & pfAltivec) != 0;
  cpu_info->cache_line_size = per_proc_info[0].pf.lineSize;
  cpu_info->l1_icache_size = per_proc_info[0].pf.l1iSize;
  cpu_info->l1_dcache_size = per_proc_info[0].pf.l1dSize;
  
  if (per_proc_info[0].pf.Available & pfL2) {
    cpu_info->l2_settings = per_proc_info[0].pf.l2cr;
    cpu_info->l2_cache_size = per_proc_info[0].pf.l2Size;
  } else {
    cpu_info->l2_settings = 0;
    cpu_info->l2_cache_size = 0xFFFFFFFF;
  }
  if (per_proc_info[0].pf.Available & pfL3) {
    cpu_info->l3_settings = per_proc_info[0].pf.l3cr;
    cpu_info->l3_cache_size = per_proc_info[0].pf.l3Size;
  } else {
    cpu_info->l3_settings = 0;
    cpu_info->l3_cache_size = 0xFFFFFFFF;
  }
}

#define l2em 0x80000000
#define l3em 0x80000000

extern int real_ncpus;

int
ml_enable_cache_level(int cache_level, int enable)
{
  int old_mode;
  unsigned long available, ccr;
  
  if (real_ncpus != 1) return -1;
  
  available = per_proc_info[0].pf.Available;
  
  if ((cache_level == 2) && (available & pfL2)) {
    ccr = per_proc_info[0].pf.l2cr;
    old_mode = (ccr & l2em) ? TRUE : FALSE;
    if (old_mode != enable) {
      if (enable) ccr = per_proc_info[0].pf.l2crOriginal;
      else ccr = 0;
      per_proc_info[0].pf.l2cr = ccr;
      cacheInit();
    }
    
    return old_mode;
  }
  
  if ((cache_level == 3) && (available & pfL3)) {
    ccr = per_proc_info[0].pf.l3cr;
    old_mode = (ccr & l3em) ? TRUE : FALSE;
    if (old_mode != enable) {
      if (enable) ccr = per_proc_info[0].pf.l3crOriginal;
      else ccr = 0;
      per_proc_info[0].pf.l3cr = ccr;
      cacheInit();
    }
    
    return old_mode;
  }
  
  return -1;
}

void
ml_init_lock_timeout(void)
{
	uint64_t	abstime;
	uint32_t	mtxspin; 

	nanoseconds_to_absolutetime(NSEC_PER_SEC>>2, &abstime);
	LockTimeOut = (unsigned int)abstime;

	if (PE_parse_boot_arg("mtxspin", &mtxspin)) {
		if (mtxspin > USEC_PER_SEC>>4)
			mtxspin =  USEC_PER_SEC>>4;
		nanoseconds_to_absolutetime(mtxspin*NSEC_PER_USEC, &abstime);
	} else {
		nanoseconds_to_absolutetime(20*NSEC_PER_USEC, &abstime);
	}
	MutexSpin = (unsigned int)abstime;
}

void
init_ast_check(processor_t processor)
{}
                
void
cause_ast_check(
	processor_t		processor)
{
	if (	processor != current_processor()								&&
	    	per_proc_info[processor->slot_num].interrupts_enabled == TRUE	)
		cpu_signal(processor->slot_num, SIGPast, NULL, NULL);
}
              
thread_t        
switch_to_shutdown_context(
	thread_t	thread,
	void		(*doshutdown)(processor_t),
	processor_t	processor)
{
	CreateShutdownCTX();   
	return((thread_t)(per_proc_info[cpu_number()].old_thread));
}

int
set_be_bit()
{
	
	int mycpu;
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);	/* Can't allow interruptions when mucking with per_proc flags */
	mycpu = cpu_number();
	per_proc_info[mycpu].cpu_flags |= traceBE;
	(void) ml_set_interrupts_enabled(current_state);
	return(1);
}

int
clr_be_bit()
{
	int mycpu;
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);	/* Can't allow interruptions when mucking with per_proc flags */
	mycpu = cpu_number();
	per_proc_info[mycpu].cpu_flags &= ~traceBE;
	(void) ml_set_interrupts_enabled(current_state);
	return(1);
}

int
be_tracing()
{
  int mycpu = cpu_number();
  return(per_proc_info[mycpu].cpu_flags & traceBE);
}
Commit	Line	Data
1c79356b A	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
e5568f75 A	6	* The contents of this file constitute Original Code as defined in and
	7	* are subject to the Apple Public Source License Version 1.1 (the
	8	* "License"). You may not use this file except in compliance with the
	9	* License. Please obtain a copy of the License at
	10	* http://www.apple.com/publicsource and read it before using this file.
1c79356b	11	*
e5568f75 A	12	* This Original Code and all software distributed under the License are
e5568f75 A	13	* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
1c79356b A	14	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
1c79356b A	15	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
e5568f75 A	16	* FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
	17	* License for the specific language governing rights and limitations
	18	* under the License.
1c79356b A	19	*
	20	* @APPLE_LICENSE_HEADER_END@
	21	*/
	22	#include <ppc/machine_routines.h>
	23	#include <ppc/machine_cpu.h>
	24	#include <ppc/exception.h>
	25	#include <ppc/misc_protos.h>
	26	#include <ppc/Firmware.h>
	27	#include <vm/vm_page.h>
	28	#include <ppc/pmap.h>
	29	#include <ppc/proc_reg.h>
	30	#include <kern/processor.h>
	31
43866e37	32	unsigned int max_cpus_initialized = 0;
ab86ba33 A	33	unsigned int LockTimeOut = 12500000;
ab86ba33 A	34	unsigned int MutexSpin = 0;
55e303ae	35	extern int forcenap;
43866e37 A	36
	37	#define MAX_CPUS_SET 0x1
	38	#define MAX_CPUS_WAIT 0x2
	39
1c79356b	40	boolean_t get_interrupts_enabled(void);
1c79356b A	41
	42	/* Map memory map IO space */
	43	vm_offset_t
	44	ml_io_map(
	45	vm_offset_t phys_addr,
	46	vm_size_t size)
	47	{
	48	return(io_map(phys_addr,size));
	49	}
	50
	51	/* static memory allocation */
	52	vm_offset_t
	53	ml_static_malloc(
	54	vm_size_t size)
	55	{
	56	extern vm_offset_t static_memory_end;
	57	extern boolean_t pmap_initialized;
	58	vm_offset_t vaddr;
	59
	60	if (pmap_initialized)
	61	return((vm_offset_t)NULL);
	62	else {
	63	vaddr = static_memory_end;
55e303ae	64	static_memory_end = round_page_32(vaddr+size);
1c79356b A	65	return(vaddr);
	66	}
	67	}
	68
	69	vm_offset_t
	70	ml_static_ptovirt(
	71	vm_offset_t paddr)
	72	{
	73	extern vm_offset_t static_memory_end;
	74	vm_offset_t vaddr;
	75
	76	/* Static memory is map V=R */
	77	vaddr = paddr;
	78	if ( (vaddr < static_memory_end) && (pmap_extract(kernel_pmap, vaddr)==paddr) )
	79	return(vaddr);
	80	else
	81	return((vm_offset_t)NULL);
	82	}
	83
	84	void
	85	ml_static_mfree(
	86	vm_offset_t vaddr,
	87	vm_size_t size)
	88	{
	89	vm_offset_t paddr_cur, vaddr_cur;
	90
55e303ae A	91	for (vaddr_cur = round_page_32(vaddr);
55e303ae A	92	vaddr_cur < trunc_page_32(vaddr+size);
1c79356b A	93	vaddr_cur += PAGE_SIZE) {
	94	paddr_cur = pmap_extract(kernel_pmap, vaddr_cur);
	95	if (paddr_cur != (vm_offset_t)NULL) {
	96	vm_page_wire_count--;
55e303ae A	97	pmap_remove(kernel_pmap, (addr64_t)vaddr_cur, (addr64_t)(vaddr_cur+PAGE_SIZE));
55e303ae A	98	vm_page_create(paddr_cur>>12,(paddr_cur+PAGE_SIZE)>>12);
1c79356b A	99	}
	100	}
	101	}
	102
	103	/* virtual to physical on wired pages */
	104	vm_offset_t ml_vtophys(
	105	vm_offset_t vaddr)
	106	{
	107	return(pmap_extract(kernel_pmap, vaddr));
	108	}
	109
	110	/* Initialize Interrupt Handler */
	111	void ml_install_interrupt_handler(
	112	void *nub,
	113	int source,
	114	void *target,
	115	IOInterruptHandler handler,
	116	void *refCon)
	117	{
	118	int current_cpu;
	119	boolean_t current_state;
	120
	121	current_cpu = cpu_number();
	122	current_state = ml_get_interrupts_enabled();
	123
	124	per_proc_info[current_cpu].interrupt_nub = nub;
	125	per_proc_info[current_cpu].interrupt_source = source;
	126	per_proc_info[current_cpu].interrupt_target = target;
	127	per_proc_info[current_cpu].interrupt_handler = handler;
	128	per_proc_info[current_cpu].interrupt_refCon = refCon;
	129
0b4e3aa0	130	per_proc_info[current_cpu].interrupts_enabled = TRUE;
1c79356b	131	(void) ml_set_interrupts_enabled(current_state);
9bccf70c A	132
9bccf70c A	133	initialize_screen(0, kPEAcquireScreen);
1c79356b A	134	}
	135
	136	/* Initialize Interrupts */
	137	void ml_init_interrupt(void)
	138	{
	139	int current_cpu;
	140	boolean_t current_state;
	141
	142	current_state = ml_get_interrupts_enabled();
	143
	144	current_cpu = cpu_number();
0b4e3aa0	145	per_proc_info[current_cpu].interrupts_enabled = TRUE;
1c79356b A	146	(void) ml_set_interrupts_enabled(current_state);
	147	}
	148
1c79356b A	149	/* Get Interrupts Enabled */
1c79356b A	150	boolean_t ml_get_interrupts_enabled(void)
1c79356b A	151	{
	152	return((mfmsr() & MASK(MSR_EE)) != 0);
	153	}
	154
1c79356b A	155	/* Check if running at interrupt context */
	156	boolean_t ml_at_interrupt_context(void)
	157	{
0b4e3aa0 A	158	boolean_t ret;
	159	boolean_t current_state;
	160
	161	current_state = ml_set_interrupts_enabled(FALSE);
	162	ret = (per_proc_info[cpu_number()].istackptr == 0);
	163	ml_set_interrupts_enabled(current_state);
	164	return(ret);
1c79356b A	165	}
	166
	167	/* Generate a fake interrupt */
	168	void ml_cause_interrupt(void)
	169	{
	170	CreateFakeIO();
	171	}
	172
9bccf70c	173	void ml_thread_policy(
d52fe63f A	174	thread_t thread,
	175	unsigned policy_id,
	176	unsigned policy_info)
	177	{
55e303ae A	178	extern int srv;
55e303ae A	179
d52fe63f	180	if ((policy_id == MACHINE_GROUP) &&
9bccf70c A	181	((per_proc_info[0].pf.Available) & pfSMPcap))
	182	thread_bind(thread, master_processor);
	183
	184	if (policy_info & MACHINE_NETWORK_WORKLOOP) {
	185	spl_t s = splsched();
	186
	187	thread_lock(thread);
	188
55e303ae A	189	if (srv == 0)
55e303ae A	190	thread->sched_mode \|= TH_MODE_FORCEDPREEMPT;
9bccf70c A	191	set_priority(thread, thread->priority + 1);
	192
	193	thread_unlock(thread);
	194	splx(s);
	195	}
d52fe63f A	196	}
d52fe63f A	197
1c79356b A	198	void machine_idle(void)
1c79356b A	199	{
0b4e3aa0	200	if (per_proc_info[cpu_number()].interrupts_enabled == TRUE) {
1c79356b A	201	int cur_decr;
	202
	203	machine_idle_ppc();
	204
	205	/*
	206	* protect against a lost decrementer trap
	207	* if the current decrementer value is negative
	208	* by more than 10 ticks, re-arm it since it's
	209	* unlikely to fire at this point... a hardware
	210	* interrupt got us out of machine_idle and may
	211	* also be contributing to this state
	212	*/
	213	cur_decr = isync_mfdec();
	214
	215	if (cur_decr < -10) {
	216	mtdec(1);
	217	}
	218	}
	219	}
	220
	221	void
	222	machine_signal_idle(
	223	processor_t processor)
	224	{
55e303ae A	225	if (per_proc_info[processor->slot_num].pf.Available & (pfCanDoze\|pfWillNap))
55e303ae A	226	(void)cpu_signal(processor->slot_num, SIGPwake, 0, 0);
1c79356b A	227	}
	228
	229	kern_return_t
	230	ml_processor_register(
	231	ml_processor_info_t *processor_info,
	232	processor_t *processor,
	233	ipi_handler_t *ipi_handler)
	234	{
	235	kern_return_t ret;
55e303ae A	236	int target_cpu, cpu;
55e303ae A	237	int donap;
1c79356b A	238
	239	if (processor_info->boot_cpu == FALSE) {
	240	if (cpu_register(&target_cpu) != KERN_SUCCESS)
	241	return KERN_FAILURE;
	242	} else {
	243	/* boot_cpu is always 0 */
55e303ae	244	target_cpu = 0;
1c79356b A	245	}
	246
	247	per_proc_info[target_cpu].cpu_id = processor_info->cpu_id;
	248	per_proc_info[target_cpu].start_paddr = processor_info->start_paddr;
	249
55e303ae A	250	donap = processor_info->supports_nap; /* Assume we use requested nap */
	251	if(forcenap) donap = forcenap - 1; /* If there was an override, use that */
	252
1c79356b	253	if(per_proc_info[target_cpu].pf.Available & pfCanNap)
55e303ae	254	if(donap)
1c79356b A	255	per_proc_info[target_cpu].pf.Available \|= pfWillNap;
	256
	257	if(processor_info->time_base_enable != (void(*)(cpu_id_t, boolean_t ))NULL)
	258	per_proc_info[target_cpu].time_base_enable = processor_info->time_base_enable;
	259	else
	260	per_proc_info[target_cpu].time_base_enable = (void(*)(cpu_id_t, boolean_t ))NULL;
	261
	262	if(target_cpu == cpu_number())
	263	__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available)); /* Set live value */
	264
	265	*processor = cpu_to_processor(target_cpu);
	266	*ipi_handler = cpu_signal_handler;
	267
	268	return KERN_SUCCESS;
	269	}
	270
	271	boolean_t
	272	ml_enable_nap(int target_cpu, boolean_t nap_enabled)
	273	{
	274	boolean_t prev_value = (per_proc_info[target_cpu].pf.Available & pfCanNap) && (per_proc_info[target_cpu].pf.Available & pfWillNap);
	275
55e303ae A	276	if(forcenap) nap_enabled = forcenap - 1; /* If we are to force nap on or off, do it */
55e303ae A	277
1c79356b A	278	if(per_proc_info[target_cpu].pf.Available & pfCanNap) { /* Can the processor nap? */
	279	if (nap_enabled) per_proc_info[target_cpu].pf.Available \|= pfWillNap; /* Is nap supported on this machine? */
	280	else per_proc_info[target_cpu].pf.Available &= ~pfWillNap; /* Clear if not */
	281	}
	282
	283	if(target_cpu == cpu_number())
	284	__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available)); /* Set live value */
55e303ae	285
de355530	286	return (prev_value);
d7e50217 A	287	}
	288
	289	void
43866e37 A	290	ml_init_max_cpus(unsigned long max_cpus)
	291	{
	292	boolean_t current_state;
	293
	294	current_state = ml_set_interrupts_enabled(FALSE);
	295	if (max_cpus_initialized != MAX_CPUS_SET) {
	296	if (max_cpus > 0 && max_cpus < NCPUS)
	297	machine_info.max_cpus = max_cpus;
	298	if (max_cpus_initialized == MAX_CPUS_WAIT)
	299	wakeup((event_t)&max_cpus_initialized);
	300	max_cpus_initialized = MAX_CPUS_SET;
	301	}
	302	(void) ml_set_interrupts_enabled(current_state);
	303	}
	304
	305	int
	306	ml_get_max_cpus(void)
	307	{
	308	boolean_t current_state;
	309
	310	current_state = ml_set_interrupts_enabled(FALSE);
	311	if (max_cpus_initialized != MAX_CPUS_SET) {
	312	max_cpus_initialized = MAX_CPUS_WAIT;
	313	assert_wait((event_t)&max_cpus_initialized, THREAD_UNINT);
	314	(void)thread_block(THREAD_CONTINUE_NULL);
	315	}
	316	(void) ml_set_interrupts_enabled(current_state);
	317	return(machine_info.max_cpus);
	318	}
	319
43866e37 A	320	void
43866e37 A	321	ml_cpu_get_info(ml_cpu_info_t *cpu_info)
1c79356b A	322	{
	323	if (cpu_info == 0) return;
	324
	325	cpu_info->vector_unit = (per_proc_info[0].pf.Available & pfAltivec) != 0;
	326	cpu_info->cache_line_size = per_proc_info[0].pf.lineSize;
	327	cpu_info->l1_icache_size = per_proc_info[0].pf.l1iSize;
	328	cpu_info->l1_dcache_size = per_proc_info[0].pf.l1dSize;
	329
	330	if (per_proc_info[0].pf.Available & pfL2) {
	331	cpu_info->l2_settings = per_proc_info[0].pf.l2cr;
	332	cpu_info->l2_cache_size = per_proc_info[0].pf.l2Size;
	333	} else {
	334	cpu_info->l2_settings = 0;
	335	cpu_info->l2_cache_size = 0xFFFFFFFF;
	336	}
	337	if (per_proc_info[0].pf.Available & pfL3) {
	338	cpu_info->l3_settings = per_proc_info[0].pf.l3cr;
	339	cpu_info->l3_cache_size = per_proc_info[0].pf.l3Size;
	340	} else {
	341	cpu_info->l3_settings = 0;
	342	cpu_info->l3_cache_size = 0xFFFFFFFF;
	343	}
	344	}
	345
d52fe63f A	346	#define l2em 0x80000000
	347	#define l3em 0x80000000
	348
	349	extern int real_ncpus;
	350
	351	int
	352	ml_enable_cache_level(int cache_level, int enable)
	353	{
	354	int old_mode;
	355	unsigned long available, ccr;
	356
	357	if (real_ncpus != 1) return -1;
	358
	359	available = per_proc_info[0].pf.Available;
	360
	361	if ((cache_level == 2) && (available & pfL2)) {
	362	ccr = per_proc_info[0].pf.l2cr;
	363	old_mode = (ccr & l2em) ? TRUE : FALSE;
	364	if (old_mode != enable) {
	365	if (enable) ccr = per_proc_info[0].pf.l2crOriginal;
	366	else ccr = 0;
	367	per_proc_info[0].pf.l2cr = ccr;
	368	cacheInit();
	369	}
	370
	371	return old_mode;
	372	}
	373
	374	if ((cache_level == 3) && (available & pfL3)) {
	375	ccr = per_proc_info[0].pf.l3cr;
	376	old_mode = (ccr & l3em) ? TRUE : FALSE;
	377	if (old_mode != enable) {
	378	if (enable) ccr = per_proc_info[0].pf.l3crOriginal;
	379	else ccr = 0;
	380	per_proc_info[0].pf.l3cr = ccr;
	381	cacheInit();
	382	}
	383
	384	return old_mode;
	385	}
	386
	387	return -1;
	388	}
	389
ab86ba33 A	390	void
	391	ml_init_lock_timeout(void)
	392	{
	393	uint64_t abstime;
	394	uint32_t mtxspin;
	395
	396	nanoseconds_to_absolutetime(NSEC_PER_SEC>>2, &abstime);
	397	LockTimeOut = (unsigned int)abstime;
	398
	399	if (PE_parse_boot_arg("mtxspin", &mtxspin)) {
	400	if (mtxspin > USEC_PER_SEC>>4)
	401	mtxspin = USEC_PER_SEC>>4;
	402	nanoseconds_to_absolutetime(mtxspin*NSEC_PER_USEC, &abstime);
	403	} else {
	404	nanoseconds_to_absolutetime(20*NSEC_PER_USEC, &abstime);
	405	}
	406	MutexSpin = (unsigned int)abstime;
	407	}
	408
1c79356b A	409	void
	410	init_ast_check(processor_t processor)
	411	{}
	412
	413	void
9bccf70c A	414	cause_ast_check(
9bccf70c A	415	processor_t processor)
1c79356b	416	{
9bccf70c A	417	if ( processor != current_processor() &&
9bccf70c A	418	per_proc_info[processor->slot_num].interrupts_enabled == TRUE )
1c79356b A	419	cpu_signal(processor->slot_num, SIGPast, NULL, NULL);
	420	}
	421
	422	thread_t
	423	switch_to_shutdown_context(
	424	thread_t thread,
	425	void (*doshutdown)(processor_t),
	426	processor_t processor)
	427	{
1c79356b	428	CreateShutdownCTX();
1c79356b A	429	return((thread_t)(per_proc_info[cpu_number()].old_thread));
	430	}
	431
	432	int
	433	set_be_bit()
	434	{
	435
	436	int mycpu;
	437	boolean_t current_state;
	438
	439	current_state = ml_set_interrupts_enabled(FALSE); /* Can't allow interruptions when mucking with per_proc flags */
	440	mycpu = cpu_number();
	441	per_proc_info[mycpu].cpu_flags \|= traceBE;
	442	(void) ml_set_interrupts_enabled(current_state);
	443	return(1);
	444	}
	445
	446	int
	447	clr_be_bit()
	448	{
	449	int mycpu;
	450	boolean_t current_state;
	451
	452	current_state = ml_set_interrupts_enabled(FALSE); /* Can't allow interruptions when mucking with per_proc flags */
	453	mycpu = cpu_number();
	454	per_proc_info[mycpu].cpu_flags &= ~traceBE;
	455	(void) ml_set_interrupts_enabled(current_state);
	456	return(1);
	457	}
	458
	459	int
	460	be_tracing()
	461	{
	462	int mycpu = cpu_number();
	463	return(per_proc_info[mycpu].cpu_flags & traceBE);
	464	}
0b4e3aa0	465