[apple/xnu.git] / osfmk / ppc / machine_routines.c

/*
 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this
 * file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
#include <ppc/machine_routines.h>
#include <ppc/machine_cpu.h>
#include <ppc/exception.h>
#include <ppc/misc_protos.h>
#include <ppc/Firmware.h>
#include <vm/vm_page.h>
#include <ppc/pmap.h>
#include <ppc/proc_reg.h>
#include <kern/processor.h>

unsigned int max_cpus_initialized = 0;
extern int forcenap;

#define	MAX_CPUS_SET	0x1
#define	MAX_CPUS_WAIT	0x2

boolean_t get_interrupts_enabled(void);

/* Map memory map IO space */
vm_offset_t 
ml_io_map(
	vm_offset_t phys_addr, 
	vm_size_t size)
{
	return(io_map(phys_addr,size));
}

/* static memory allocation */
vm_offset_t 
ml_static_malloc(
	vm_size_t size)
{
	extern vm_offset_t static_memory_end;
	extern boolean_t pmap_initialized;
	vm_offset_t vaddr;

	if (pmap_initialized)
		return((vm_offset_t)NULL);
	else {
		vaddr = static_memory_end;
		static_memory_end = round_page_32(vaddr+size);
		return(vaddr);
	}
}

vm_offset_t
ml_static_ptovirt(
	vm_offset_t paddr)
{
	extern vm_offset_t static_memory_end;
	vm_offset_t vaddr;

	/* Static memory is map V=R */
	vaddr = paddr;
	if ( (vaddr < static_memory_end) && (pmap_extract(kernel_pmap, vaddr)==paddr) )
		return(vaddr);
	else
		return((vm_offset_t)NULL);
}

void
ml_static_mfree(
	vm_offset_t vaddr,
	vm_size_t size)
{
	vm_offset_t paddr_cur, vaddr_cur;

	for (vaddr_cur = round_page_32(vaddr);
	     vaddr_cur < trunc_page_32(vaddr+size);
	     vaddr_cur += PAGE_SIZE) {
		paddr_cur = pmap_extract(kernel_pmap, vaddr_cur);
		if (paddr_cur != (vm_offset_t)NULL) {
			vm_page_wire_count--;
			pmap_remove(kernel_pmap, (addr64_t)vaddr_cur, (addr64_t)(vaddr_cur+PAGE_SIZE));
			vm_page_create(paddr_cur>>12,(paddr_cur+PAGE_SIZE)>>12);
		}
	}
}

/* virtual to physical on wired pages */
vm_offset_t ml_vtophys(
	vm_offset_t vaddr)
{
	return(pmap_extract(kernel_pmap, vaddr));
}

/* Initialize Interrupt Handler */
void ml_install_interrupt_handler(
	void *nub,
	int source,
	void *target,
	IOInterruptHandler handler,
	void *refCon)
{
	int	current_cpu;
	boolean_t current_state;

	current_cpu = cpu_number();
	current_state = ml_get_interrupts_enabled();

	per_proc_info[current_cpu].interrupt_nub     = nub;
	per_proc_info[current_cpu].interrupt_source  = source;
	per_proc_info[current_cpu].interrupt_target  = target;
	per_proc_info[current_cpu].interrupt_handler = handler;
	per_proc_info[current_cpu].interrupt_refCon  = refCon;

	per_proc_info[current_cpu].interrupts_enabled = TRUE;  
	(void) ml_set_interrupts_enabled(current_state);

	initialize_screen(0, kPEAcquireScreen);
}

/* Initialize Interrupts */
void ml_init_interrupt(void)
{
	int	current_cpu;
	boolean_t current_state;

	current_state = ml_get_interrupts_enabled();

	current_cpu = cpu_number();
	per_proc_info[current_cpu].interrupts_enabled = TRUE;  
	(void) ml_set_interrupts_enabled(current_state);
}

/* Get Interrupts Enabled */
boolean_t ml_get_interrupts_enabled(void)
{
	return((mfmsr() & MASK(MSR_EE)) != 0);
}

/* Check if running at interrupt context */
boolean_t ml_at_interrupt_context(void)
{
	boolean_t	ret;
	boolean_t	current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
 	ret = (per_proc_info[cpu_number()].istackptr == 0);	
	ml_set_interrupts_enabled(current_state);
	return(ret);
}

/* Generate a fake interrupt */
void ml_cause_interrupt(void)
{
	CreateFakeIO();
}

void ml_thread_policy(
	thread_t thread,
	unsigned policy_id,
	unsigned policy_info)
{
	if ((policy_id == MACHINE_GROUP) &&
		((per_proc_info[0].pf.Available) & pfSMPcap))
			thread_bind(thread, master_processor);

	if (policy_info & MACHINE_NETWORK_WORKLOOP) {
		spl_t		s = splsched();

		thread_lock(thread);

		thread->sched_mode |= TH_MODE_FORCEDPREEMPT;
		set_priority(thread, thread->priority + 1);

		thread_unlock(thread);
		splx(s);
	}
}

void machine_idle(void)
{
        if (per_proc_info[cpu_number()].interrupts_enabled == TRUE) {
	        int cur_decr;

	        machine_idle_ppc();

		/*
		 * protect against a lost decrementer trap
		 * if the current decrementer value is negative
		 * by more than 10 ticks, re-arm it since it's 
		 * unlikely to fire at this point... a hardware
		 * interrupt got us out of machine_idle and may
		 * also be contributing to this state
		 */
		cur_decr = isync_mfdec();

		if (cur_decr < -10) {
		        mtdec(1);
		}
	}
}

void
machine_signal_idle(
	processor_t processor)
{
	(void)cpu_signal(processor->slot_num, SIGPwake, 0, 0);
}

kern_return_t
ml_processor_register(
	ml_processor_info_t *processor_info,
	processor_t	    *processor,
	ipi_handler_t       *ipi_handler)
{
	kern_return_t ret;
	int target_cpu, cpu;
	int donap;

	if (processor_info->boot_cpu == FALSE) {
		 if (cpu_register(&target_cpu) != KERN_SUCCESS)
			return KERN_FAILURE;
	} else {
		/* boot_cpu is always 0 */
		target_cpu = 0;
	}

	per_proc_info[target_cpu].cpu_id = processor_info->cpu_id;
	per_proc_info[target_cpu].start_paddr = processor_info->start_paddr;

	donap = processor_info->supports_nap;		/* Assume we use requested nap */
	if(forcenap) donap = forcenap - 1;			/* If there was an override, use that */
	
	if(per_proc_info[target_cpu].pf.Available & pfCanNap)
	  if(donap) 
		per_proc_info[target_cpu].pf.Available |= pfWillNap;

	if(processor_info->time_base_enable !=  (void(*)(cpu_id_t, boolean_t ))NULL)
		per_proc_info[target_cpu].time_base_enable = processor_info->time_base_enable;
	else
		per_proc_info[target_cpu].time_base_enable = (void(*)(cpu_id_t, boolean_t ))NULL;
	
	if(target_cpu == cpu_number()) 
		__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available));	/* Set live value */

	*processor = cpu_to_processor(target_cpu);
	*ipi_handler = cpu_signal_handler;

	return KERN_SUCCESS;
}

boolean_t
ml_enable_nap(int target_cpu, boolean_t nap_enabled)
{
    boolean_t prev_value = (per_proc_info[target_cpu].pf.Available & pfCanNap) && (per_proc_info[target_cpu].pf.Available & pfWillNap);
    
 	if(forcenap) nap_enabled = forcenap - 1;		/* If we are to force nap on or off, do it */
 
 	if(per_proc_info[target_cpu].pf.Available & pfCanNap) {				/* Can the processor nap? */
		if (nap_enabled) per_proc_info[target_cpu].pf.Available |= pfWillNap;	/* Is nap supported on this machine? */
		else per_proc_info[target_cpu].pf.Available &= ~pfWillNap;		/* Clear if not */
	}

	if(target_cpu == cpu_number()) 
		__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available));	/* Set live value */
 
    return (prev_value);
}

void
ml_init_max_cpus(unsigned long max_cpus)
{
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
	if (max_cpus_initialized != MAX_CPUS_SET) {
		if (max_cpus > 0 && max_cpus < NCPUS)
			machine_info.max_cpus = max_cpus;
		if (max_cpus_initialized == MAX_CPUS_WAIT)
			wakeup((event_t)&max_cpus_initialized);
		max_cpus_initialized = MAX_CPUS_SET;
	}
	(void) ml_set_interrupts_enabled(current_state);
}

int
ml_get_max_cpus(void)
{
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);
	if (max_cpus_initialized != MAX_CPUS_SET) {
		max_cpus_initialized = MAX_CPUS_WAIT;
		assert_wait((event_t)&max_cpus_initialized, THREAD_UNINT);
		(void)thread_block(THREAD_CONTINUE_NULL);
	}
	(void) ml_set_interrupts_enabled(current_state);
	return(machine_info.max_cpus);
}

int
ml_get_current_cpus(void)
{
	return machine_info.avail_cpus;
}

void
ml_cpu_get_info(ml_cpu_info_t *cpu_info)
{
  if (cpu_info == 0) return;
  
  cpu_info->vector_unit = (per_proc_info[0].pf.Available & pfAltivec) != 0;
  cpu_info->cache_line_size = per_proc_info[0].pf.lineSize;
  cpu_info->l1_icache_size = per_proc_info[0].pf.l1iSize;
  cpu_info->l1_dcache_size = per_proc_info[0].pf.l1dSize;
  
  if (per_proc_info[0].pf.Available & pfL2) {
    cpu_info->l2_settings = per_proc_info[0].pf.l2cr;
    cpu_info->l2_cache_size = per_proc_info[0].pf.l2Size;
  } else {
    cpu_info->l2_settings = 0;
    cpu_info->l2_cache_size = 0xFFFFFFFF;
  }
  if (per_proc_info[0].pf.Available & pfL3) {
    cpu_info->l3_settings = per_proc_info[0].pf.l3cr;
    cpu_info->l3_cache_size = per_proc_info[0].pf.l3Size;
  } else {
    cpu_info->l3_settings = 0;
    cpu_info->l3_cache_size = 0xFFFFFFFF;
  }
}

#define l2em 0x80000000
#define l3em 0x80000000

extern int real_ncpus;

int
ml_enable_cache_level(int cache_level, int enable)
{
  int old_mode;
  unsigned long available, ccr;
  
  if (real_ncpus != 1) return -1;
  
  available = per_proc_info[0].pf.Available;
  
  if ((cache_level == 2) && (available & pfL2)) {
    ccr = per_proc_info[0].pf.l2cr;
    old_mode = (ccr & l2em) ? TRUE : FALSE;
    if (old_mode != enable) {
      if (enable) ccr = per_proc_info[0].pf.l2crOriginal;
      else ccr = 0;
      per_proc_info[0].pf.l2cr = ccr;
      cacheInit();
    }
    
    return old_mode;
  }
  
  if ((cache_level == 3) && (available & pfL3)) {
    ccr = per_proc_info[0].pf.l3cr;
    old_mode = (ccr & l3em) ? TRUE : FALSE;
    if (old_mode != enable) {
      if (enable) ccr = per_proc_info[0].pf.l3crOriginal;
      else ccr = 0;
      per_proc_info[0].pf.l3cr = ccr;
      cacheInit();
    }
    
    return old_mode;
  }
  
  return -1;
}

void
init_ast_check(processor_t processor)
{}
                
void
cause_ast_check(
	processor_t		processor)
{
	if (	processor != current_processor()								&&
	    	per_proc_info[processor->slot_num].interrupts_enabled == TRUE	)
		cpu_signal(processor->slot_num, SIGPast, NULL, NULL);
}
              
thread_t        
switch_to_shutdown_context(
	thread_t	thread,
	void		(*doshutdown)(processor_t),
	processor_t	processor)
{
	CreateShutdownCTX();   
	return((thread_t)(per_proc_info[cpu_number()].old_thread));
}

int
set_be_bit()
{
	
	int mycpu;
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);	/* Can't allow interruptions when mucking with per_proc flags */
	mycpu = cpu_number();
	per_proc_info[mycpu].cpu_flags |= traceBE;
	(void) ml_set_interrupts_enabled(current_state);
	return(1);
}

int
clr_be_bit()
{
	int mycpu;
	boolean_t current_state;

	current_state = ml_set_interrupts_enabled(FALSE);	/* Can't allow interruptions when mucking with per_proc flags */
	mycpu = cpu_number();
	per_proc_info[mycpu].cpu_flags &= ~traceBE;
	(void) ml_set_interrupts_enabled(current_state);
	return(1);
}

int
be_tracing()
{
  int mycpu = cpu_number();
  return(per_proc_info[mycpu].cpu_flags & traceBE);
}
Commit	Line	Data
1c79356b A	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
d7e50217	6	* Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
1c79356b	7	*
d7e50217 A	8	* This file contains Original Code and/or Modifications of Original Code
	9	* as defined in and that are subject to the Apple Public Source License
	10	* Version 2.0 (the 'License'). You may not use this file except in
	11	* compliance with the License. Please obtain a copy of the License at
	12	* http://www.opensource.apple.com/apsl/ and read it before using this
	13	* file.
	14	*
	15	* The Original Code and all software distributed under the License are
	16	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
1c79356b A	17	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
1c79356b A	18	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
d7e50217 A	19	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	20	* Please see the License for the specific language governing rights and
	21	* limitations under the License.
1c79356b A	22	*
	23	* @APPLE_LICENSE_HEADER_END@
	24	*/
	25	#include <ppc/machine_routines.h>
	26	#include <ppc/machine_cpu.h>
	27	#include <ppc/exception.h>
	28	#include <ppc/misc_protos.h>
	29	#include <ppc/Firmware.h>
	30	#include <vm/vm_page.h>
	31	#include <ppc/pmap.h>
	32	#include <ppc/proc_reg.h>
	33	#include <kern/processor.h>
	34
d7e50217 A	35	unsigned int max_cpus_initialized = 0;
	36	extern int forcenap;
	37
	38	#define MAX_CPUS_SET 0x1
	39	#define MAX_CPUS_WAIT 0x2
	40
1c79356b	41	boolean_t get_interrupts_enabled(void);
1c79356b A	42
	43	/* Map memory map IO space */
	44	vm_offset_t
	45	ml_io_map(
	46	vm_offset_t phys_addr,
	47	vm_size_t size)
	48	{
	49	return(io_map(phys_addr,size));
	50	}
	51
	52	/* static memory allocation */
	53	vm_offset_t
	54	ml_static_malloc(
	55	vm_size_t size)
	56	{
	57	extern vm_offset_t static_memory_end;
	58	extern boolean_t pmap_initialized;
	59	vm_offset_t vaddr;
	60
	61	if (pmap_initialized)
	62	return((vm_offset_t)NULL);
	63	else {
	64	vaddr = static_memory_end;
d7e50217	65	static_memory_end = round_page_32(vaddr+size);
1c79356b A	66	return(vaddr);
	67	}
	68	}
	69
	70	vm_offset_t
	71	ml_static_ptovirt(
	72	vm_offset_t paddr)
	73	{
	74	extern vm_offset_t static_memory_end;
	75	vm_offset_t vaddr;
	76
	77	/* Static memory is map V=R */
	78	vaddr = paddr;
	79	if ( (vaddr < static_memory_end) && (pmap_extract(kernel_pmap, vaddr)==paddr) )
	80	return(vaddr);
	81	else
	82	return((vm_offset_t)NULL);
	83	}
	84
	85	void
	86	ml_static_mfree(
	87	vm_offset_t vaddr,
	88	vm_size_t size)
	89	{
	90	vm_offset_t paddr_cur, vaddr_cur;
	91
d7e50217 A	92	for (vaddr_cur = round_page_32(vaddr);
d7e50217 A	93	vaddr_cur < trunc_page_32(vaddr+size);
1c79356b A	94	vaddr_cur += PAGE_SIZE) {
	95	paddr_cur = pmap_extract(kernel_pmap, vaddr_cur);
	96	if (paddr_cur != (vm_offset_t)NULL) {
	97	vm_page_wire_count--;
d7e50217 A	98	pmap_remove(kernel_pmap, (addr64_t)vaddr_cur, (addr64_t)(vaddr_cur+PAGE_SIZE));
d7e50217 A	99	vm_page_create(paddr_cur>>12,(paddr_cur+PAGE_SIZE)>>12);
1c79356b A	100	}
	101	}
	102	}
	103
	104	/* virtual to physical on wired pages */
	105	vm_offset_t ml_vtophys(
	106	vm_offset_t vaddr)
	107	{
	108	return(pmap_extract(kernel_pmap, vaddr));
	109	}
	110
	111	/* Initialize Interrupt Handler */
	112	void ml_install_interrupt_handler(
	113	void *nub,
	114	int source,
	115	void *target,
	116	IOInterruptHandler handler,
	117	void *refCon)
	118	{
	119	int current_cpu;
	120	boolean_t current_state;
	121
	122	current_cpu = cpu_number();
	123	current_state = ml_get_interrupts_enabled();
	124
	125	per_proc_info[current_cpu].interrupt_nub = nub;
	126	per_proc_info[current_cpu].interrupt_source = source;
	127	per_proc_info[current_cpu].interrupt_target = target;
	128	per_proc_info[current_cpu].interrupt_handler = handler;
	129	per_proc_info[current_cpu].interrupt_refCon = refCon;
	130
0b4e3aa0	131	per_proc_info[current_cpu].interrupts_enabled = TRUE;
1c79356b	132	(void) ml_set_interrupts_enabled(current_state);
9bccf70c A	133
9bccf70c A	134	initialize_screen(0, kPEAcquireScreen);
1c79356b A	135	}
	136
	137	/* Initialize Interrupts */
	138	void ml_init_interrupt(void)
	139	{
	140	int current_cpu;
	141	boolean_t current_state;
	142
	143	current_state = ml_get_interrupts_enabled();
	144
	145	current_cpu = cpu_number();
0b4e3aa0	146	per_proc_info[current_cpu].interrupts_enabled = TRUE;
1c79356b A	147	(void) ml_set_interrupts_enabled(current_state);
	148	}
	149
1c79356b A	150	/* Get Interrupts Enabled */
1c79356b A	151	boolean_t ml_get_interrupts_enabled(void)
1c79356b A	152	{
	153	return((mfmsr() & MASK(MSR_EE)) != 0);
	154	}
	155
1c79356b A	156	/* Check if running at interrupt context */
	157	boolean_t ml_at_interrupt_context(void)
	158	{
0b4e3aa0 A	159	boolean_t ret;
	160	boolean_t current_state;
	161
	162	current_state = ml_set_interrupts_enabled(FALSE);
	163	ret = (per_proc_info[cpu_number()].istackptr == 0);
	164	ml_set_interrupts_enabled(current_state);
	165	return(ret);
1c79356b A	166	}
	167
	168	/* Generate a fake interrupt */
	169	void ml_cause_interrupt(void)
	170	{
	171	CreateFakeIO();
	172	}
	173
9bccf70c	174	void ml_thread_policy(
d52fe63f A	175	thread_t thread,
	176	unsigned policy_id,
	177	unsigned policy_info)
	178	{
	179	if ((policy_id == MACHINE_GROUP) &&
9bccf70c A	180	((per_proc_info[0].pf.Available) & pfSMPcap))
	181	thread_bind(thread, master_processor);
	182
	183	if (policy_info & MACHINE_NETWORK_WORKLOOP) {
	184	spl_t s = splsched();
	185
	186	thread_lock(thread);
	187
	188	thread->sched_mode \|= TH_MODE_FORCEDPREEMPT;
	189	set_priority(thread, thread->priority + 1);
	190
	191	thread_unlock(thread);
	192	splx(s);
	193	}
d52fe63f A	194	}
d52fe63f A	195
1c79356b A	196	void machine_idle(void)
1c79356b A	197	{
0b4e3aa0	198	if (per_proc_info[cpu_number()].interrupts_enabled == TRUE) {
1c79356b A	199	int cur_decr;
	200
	201	machine_idle_ppc();
	202
	203	/*
	204	* protect against a lost decrementer trap
	205	* if the current decrementer value is negative
	206	* by more than 10 ticks, re-arm it since it's
	207	* unlikely to fire at this point... a hardware
	208	* interrupt got us out of machine_idle and may
	209	* also be contributing to this state
	210	*/
	211	cur_decr = isync_mfdec();
	212
	213	if (cur_decr < -10) {
	214	mtdec(1);
	215	}
	216	}
	217	}
	218
	219	void
	220	machine_signal_idle(
	221	processor_t processor)
	222	{
	223	(void)cpu_signal(processor->slot_num, SIGPwake, 0, 0);
	224	}
	225
	226	kern_return_t
	227	ml_processor_register(
	228	ml_processor_info_t *processor_info,
	229	processor_t *processor,
	230	ipi_handler_t *ipi_handler)
	231	{
	232	kern_return_t ret;
d7e50217 A	233	int target_cpu, cpu;
d7e50217 A	234	int donap;
1c79356b A	235
	236	if (processor_info->boot_cpu == FALSE) {
	237	if (cpu_register(&target_cpu) != KERN_SUCCESS)
	238	return KERN_FAILURE;
	239	} else {
	240	/* boot_cpu is always 0 */
d7e50217	241	target_cpu = 0;
1c79356b A	242	}
	243
	244	per_proc_info[target_cpu].cpu_id = processor_info->cpu_id;
	245	per_proc_info[target_cpu].start_paddr = processor_info->start_paddr;
	246
d7e50217 A	247	donap = processor_info->supports_nap; /* Assume we use requested nap */
	248	if(forcenap) donap = forcenap - 1; /* If there was an override, use that */
	249
1c79356b	250	if(per_proc_info[target_cpu].pf.Available & pfCanNap)
d7e50217	251	if(donap)
1c79356b A	252	per_proc_info[target_cpu].pf.Available \|= pfWillNap;
	253
	254	if(processor_info->time_base_enable != (void(*)(cpu_id_t, boolean_t ))NULL)
	255	per_proc_info[target_cpu].time_base_enable = processor_info->time_base_enable;
	256	else
	257	per_proc_info[target_cpu].time_base_enable = (void(*)(cpu_id_t, boolean_t ))NULL;
	258
	259	if(target_cpu == cpu_number())
	260	__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available)); /* Set live value */
	261
	262	*processor = cpu_to_processor(target_cpu);
	263	*ipi_handler = cpu_signal_handler;
	264
	265	return KERN_SUCCESS;
	266	}
	267
	268	boolean_t
	269	ml_enable_nap(int target_cpu, boolean_t nap_enabled)
	270	{
	271	boolean_t prev_value = (per_proc_info[target_cpu].pf.Available & pfCanNap) && (per_proc_info[target_cpu].pf.Available & pfWillNap);
	272
d7e50217 A	273	if(forcenap) nap_enabled = forcenap - 1; /* If we are to force nap on or off, do it */
d7e50217 A	274
1c79356b A	275	if(per_proc_info[target_cpu].pf.Available & pfCanNap) { /* Can the processor nap? */
	276	if (nap_enabled) per_proc_info[target_cpu].pf.Available \|= pfWillNap; /* Is nap supported on this machine? */
	277	else per_proc_info[target_cpu].pf.Available &= ~pfWillNap; /* Clear if not */
	278	}
	279
	280	if(target_cpu == cpu_number())
	281	__asm__ volatile("mtsprg 2,%0" : : "r" (per_proc_info[target_cpu].pf.Available)); /* Set live value */
d7e50217	282
1c79356b A	283	return (prev_value);
	284	}
	285
	286	void
d7e50217 A	287	ml_init_max_cpus(unsigned long max_cpus)
	288	{
	289	boolean_t current_state;
	290
	291	current_state = ml_set_interrupts_enabled(FALSE);
	292	if (max_cpus_initialized != MAX_CPUS_SET) {
	293	if (max_cpus > 0 && max_cpus < NCPUS)
	294	machine_info.max_cpus = max_cpus;
	295	if (max_cpus_initialized == MAX_CPUS_WAIT)
	296	wakeup((event_t)&max_cpus_initialized);
	297	max_cpus_initialized = MAX_CPUS_SET;
	298	}
	299	(void) ml_set_interrupts_enabled(current_state);
	300	}
	301
	302	int
	303	ml_get_max_cpus(void)
	304	{
	305	boolean_t current_state;
	306
	307	current_state = ml_set_interrupts_enabled(FALSE);
	308	if (max_cpus_initialized != MAX_CPUS_SET) {
	309	max_cpus_initialized = MAX_CPUS_WAIT;
	310	assert_wait((event_t)&max_cpus_initialized, THREAD_UNINT);
	311	(void)thread_block(THREAD_CONTINUE_NULL);
	312	}
	313	(void) ml_set_interrupts_enabled(current_state);
	314	return(machine_info.max_cpus);
	315	}
	316
	317	int
	318	ml_get_current_cpus(void)
	319	{
	320	return machine_info.avail_cpus;
	321	}
	322
	323	void
	324	ml_cpu_get_info(ml_cpu_info_t *cpu_info)
1c79356b A	325	{
	326	if (cpu_info == 0) return;
	327
	328	cpu_info->vector_unit = (per_proc_info[0].pf.Available & pfAltivec) != 0;
	329	cpu_info->cache_line_size = per_proc_info[0].pf.lineSize;
	330	cpu_info->l1_icache_size = per_proc_info[0].pf.l1iSize;
	331	cpu_info->l1_dcache_size = per_proc_info[0].pf.l1dSize;
	332
	333	if (per_proc_info[0].pf.Available & pfL2) {
	334	cpu_info->l2_settings = per_proc_info[0].pf.l2cr;
	335	cpu_info->l2_cache_size = per_proc_info[0].pf.l2Size;
	336	} else {
	337	cpu_info->l2_settings = 0;
	338	cpu_info->l2_cache_size = 0xFFFFFFFF;
	339	}
	340	if (per_proc_info[0].pf.Available & pfL3) {
	341	cpu_info->l3_settings = per_proc_info[0].pf.l3cr;
	342	cpu_info->l3_cache_size = per_proc_info[0].pf.l3Size;
	343	} else {
	344	cpu_info->l3_settings = 0;
	345	cpu_info->l3_cache_size = 0xFFFFFFFF;
	346	}
	347	}
	348
d52fe63f A	349	#define l2em 0x80000000
	350	#define l3em 0x80000000
	351
	352	extern int real_ncpus;
	353
	354	int
	355	ml_enable_cache_level(int cache_level, int enable)
	356	{
	357	int old_mode;
	358	unsigned long available, ccr;
	359
	360	if (real_ncpus != 1) return -1;
	361
	362	available = per_proc_info[0].pf.Available;
	363
	364	if ((cache_level == 2) && (available & pfL2)) {
	365	ccr = per_proc_info[0].pf.l2cr;
	366	old_mode = (ccr & l2em) ? TRUE : FALSE;
	367	if (old_mode != enable) {
	368	if (enable) ccr = per_proc_info[0].pf.l2crOriginal;
	369	else ccr = 0;
	370	per_proc_info[0].pf.l2cr = ccr;
	371	cacheInit();
	372	}
	373
	374	return old_mode;
	375	}
	376
	377	if ((cache_level == 3) && (available & pfL3)) {
	378	ccr = per_proc_info[0].pf.l3cr;
	379	old_mode = (ccr & l3em) ? TRUE : FALSE;
	380	if (old_mode != enable) {
	381	if (enable) ccr = per_proc_info[0].pf.l3crOriginal;
	382	else ccr = 0;
	383	per_proc_info[0].pf.l3cr = ccr;
	384	cacheInit();
	385	}
	386
	387	return old_mode;
	388	}
	389
	390	return -1;
	391	}
	392
1c79356b A	393	void
	394	init_ast_check(processor_t processor)
	395	{}
	396
	397	void
9bccf70c A	398	cause_ast_check(
9bccf70c A	399	processor_t processor)
1c79356b	400	{
9bccf70c A	401	if ( processor != current_processor() &&
9bccf70c A	402	per_proc_info[processor->slot_num].interrupts_enabled == TRUE )
1c79356b A	403	cpu_signal(processor->slot_num, SIGPast, NULL, NULL);
	404	}
	405
	406	thread_t
	407	switch_to_shutdown_context(
	408	thread_t thread,
	409	void (*doshutdown)(processor_t),
	410	processor_t processor)
	411	{
1c79356b	412	CreateShutdownCTX();
1c79356b A	413	return((thread_t)(per_proc_info[cpu_number()].old_thread));
	414	}
	415
	416	int
	417	set_be_bit()
	418	{
	419
	420	int mycpu;
	421	boolean_t current_state;
	422
	423	current_state = ml_set_interrupts_enabled(FALSE); /* Can't allow interruptions when mucking with per_proc flags */
	424	mycpu = cpu_number();
	425	per_proc_info[mycpu].cpu_flags \|= traceBE;
	426	(void) ml_set_interrupts_enabled(current_state);
	427	return(1);
	428	}
	429
	430	int
	431	clr_be_bit()
	432	{
	433	int mycpu;
	434	boolean_t current_state;
	435
	436	current_state = ml_set_interrupts_enabled(FALSE); /* Can't allow interruptions when mucking with per_proc flags */
	437	mycpu = cpu_number();
	438	per_proc_info[mycpu].cpu_flags &= ~traceBE;
	439	(void) ml_set_interrupts_enabled(current_state);
	440	return(1);
	441	}
	442
	443	int
	444	be_tracing()
	445	{
	446	int mycpu = cpu_number();
	447	return(per_proc_info[mycpu].cpu_flags & traceBE);
	448	}
0b4e3aa0	449