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1/*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
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6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
1c79356b 11 *
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12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
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14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
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16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
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19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22/*
23 * @OSF_COPYRIGHT@
24 */
25/*
26 * Mach Operating System
27 * Copyright (c) 1991 Carnegie Mellon University
28 * All Rights Reserved.
29 *
30 * Permission to use, copy, modify and distribute this software and its
31 * documentation is hereby granted, provided that both the copyright
32 * notice and this permission notice appear in all copies of the
33 * software, derivative works or modified versions, and any portions
34 * thereof, and that both notices appear in supporting documentation.
35 *
36 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
37 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
38 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
39 *
40 * Carnegie Mellon requests users of this software to return to
41 *
42 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
43 * School of Computer Science
44 * Carnegie Mellon University
45 * Pittsburgh PA 15213-3890
46 *
47 * any improvements or extensions that they make and grant Carnegie Mellon
48 * the rights to redistribute these changes.
49 */
50
51/*
52 */
53
54#ifndef _I386_FPU_H_
55#define _I386_FPU_H_
56
57/*
58 * Macro definitions for routines to manipulate the
59 * floating-point processor.
60 */
61
62#include <cpus.h>
63#include <i386/proc_reg.h>
64#include <i386/thread.h>
65#include <kern/kern_types.h>
66#include <mach/i386/kern_return.h>
67#include <mach/i386/thread_status.h>
68
69/*
70 * FPU instructions.
71 */
72#define fninit() \
73 __asm__ volatile("fninit")
74
75#define fnstcw(control) \
76 __asm__("fnstcw %0" : "=m" (*(unsigned short *)(control)))
77
78#define fldcw(control) \
79 __asm__ volatile("fldcw %0" : : "m" (*(unsigned short *) &(control)) )
80
81extern unsigned short fnstsw(void);
82
83extern __inline__ unsigned short fnstsw(void)
84{
85 unsigned short status;
86 __asm__ volatile("fnstsw %0" : "=ma" (status));
87 return(status);
88}
89
90#define fnclex() \
91 __asm__ volatile("fnclex")
92
55e303ae 93#define fnsave(state) \
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94 __asm__ volatile("fnsave %0" : "=m" (*state))
95
96#define frstor(state) \
97 __asm__ volatile("frstor %0" : : "m" (state))
98
99#define fwait() \
100 __asm__("fwait");
101
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102#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
103#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
104
105#define FXSAFE() (fp_kind == FP_FXSR)
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106
107#define fpu_load_context(pcb)
108
109/*
110 * Save thread`s FPU context.
111 * If only one CPU, we just set the task-switched bit,
112 * to keep the new thread from using the coprocessor.
113 * If multiple CPUs, we save the entire state.
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114 * NOTE: in order to provide backwards compatible support in the kernel. When saving SSE2 state, we also save the
115 * FP state in it's old location. Otherwise fpu_get_state() and fpu_set_state() will stop working
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116 */
117#if NCPUS > 1
118#define fpu_save_context(thread) \
119 { \
120 register struct i386_fpsave_state *ifps; \
121 ifps = (thread)->top_act->mact.pcb->ims.ifps; \
122 if (ifps != 0 && !ifps->fp_valid) { \
123 /* registers are in FPU - save to memory */ \
124 ifps->fp_valid = TRUE; \
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125 ifps->fp_save_flavor = FP_387; \
126 if (FXSAFE()) { \
127 fxsave(&ifps->fx_save_state); \
128 ifps->fp_save_flavor = FP_FXSR; \
129 } \
130 fnsave(&ifps->fp_save_state); \
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131 } \
132 set_ts(); \
133 }
134
135#else /* NCPUS == 1 */
136#define fpu_save_context(thread) \
137 { \
138 set_ts(); \
139 }
140
141#endif /* NCPUS == 1 */
142
143
144extern int fp_kind;
145
146extern void init_fpu(void);
147extern void fpu_module_init(void);
148extern void fp_free(
149 struct i386_fpsave_state * fps);
150extern kern_return_t fpu_set_state(
151 thread_act_t thr_act,
152 struct i386_float_state * st);
153extern kern_return_t fpu_get_state(
154 thread_act_t thr_act,
155 struct i386_float_state * st);
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156/* extern kern_return_t fpu_set_fxstate(
157 thread_act_t thr_act,
158 struct i386_float_state * st);
159extern kern_return_t fpu_get_fxstate(
160 thread_act_t thr_act,
161 struct i386_float_state * st); */
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162extern void fpnoextflt(void);
163extern void fpextovrflt(void);
164extern void fpexterrflt(void);
165extern void fp_state_alloc(void);
166extern void fpintr(void);
167extern void fpflush(thread_act_t);
168
169#endif /* _I386_FPU_H_ */