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1c79356b 1/*
0a7de745 2 * Copyright (c) 2000-2019 Apple Inc. All rights reserved.
1c79356b 3 *
2d21ac55 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
0a7de745 5 *
2d21ac55
A
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
0a7de745 14 *
2d21ac55
A
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
0a7de745 17 *
2d21ac55
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18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5
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20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55
A
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
0a7de745 25 *
2d21ac55 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b
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27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31
0a7de745
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32#ifndef _I386_MACHINE_ROUTINES_H_
33#define _I386_MACHINE_ROUTINES_H_
1c79356b
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34
35#include <mach/mach_types.h>
36#include <mach/boolean.h>
37#include <kern/kern_types.h>
38#include <pexpert/pexpert.h>
39
91447636 40#include <sys/cdefs.h>
9bccf70c 41#include <sys/appleapiopts.h>
1c79356b 42
5ba3f43e
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43#include <stdarg.h>
44
91447636
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45__BEGIN_DECLS
46
b0d623f7
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47#ifdef XNU_KERNEL_PRIVATE
48
0c530ab8
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49/* are we a 64 bit platform ? */
50
51boolean_t ml_is64bit(void);
52
53/* is this a 64bit thread? */
54
55boolean_t ml_thread_is64bit(thread_t);
56
57/* is this a 64bit thread? */
58
59boolean_t ml_state_is64bit(void *);
60
61/* set state of fpu save area for signal handling */
62
0a7de745 63void ml_fp_setvalid(boolean_t);
0c530ab8 64
0a7de745 65void ml_cpu_set_ldt(int);
0c530ab8 66
1c79356b
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67/* Interrupt handling */
68
55e303ae
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69/* Initialize Interrupts */
70void ml_init_interrupt(void);
71
1c79356b
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72/* Generate a fake interrupt */
73void ml_cause_interrupt(void);
74
b0d623f7
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75/* Initialize Interrupts */
76void ml_install_interrupt_handler(
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77 void *nub,
78 int source,
79 void *target,
80 IOInterruptHandler handler,
81 void *refCon);
b0d623f7 82
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83void ml_entropy_collect(void);
84
5ba3f43e 85uint64_t ml_get_timebase(void);
0a7de745 86void ml_init_lock_timeout(void);
bd504ef0 87void ml_init_delay_spin_threshold(int);
316670eb
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88
89boolean_t ml_delay_should_spin(uint64_t interval);
d52fe63f 90
e8c3f781
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91extern void ml_delay_on_yield(void);
92
b0d623f7 93vm_offset_t
0a7de745 94 ml_static_ptovirt(
b0d623f7
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95 vm_offset_t);
96
97void ml_static_mfree(
98 vm_offset_t,
99 vm_size_t);
100
101/* boot memory allocation */
102vm_offset_t ml_static_malloc(
103 vm_size_t size);
104
d9a64523
A
105vm_offset_t ml_static_slide(
106 vm_offset_t vaddr);
107
108vm_offset_t ml_static_unslide(
109 vm_offset_t vaddr);
110
b0d623f7
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111/* virtual to physical on wired pages */
112vm_offset_t ml_vtophys(
113 vm_offset_t vaddr);
114
115vm_size_t ml_nofault_copy(
116 vm_offset_t virtsrc, vm_offset_t virtdst, vm_size_t size);
117
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118boolean_t ml_validate_nofault(
119 vm_offset_t virtsrc, vm_size_t size);
120
b0d623f7 121/* Machine topology info */
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122uint64_t ml_cpu_cache_size(unsigned int level);
123uint64_t ml_cpu_cache_sharing(unsigned int level);
b0d623f7
A
124
125/* Initialize the maximum number of CPUs */
126void ml_init_max_cpus(
127 unsigned long max_cpus);
128
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129extern void ml_cpu_up(void);
130extern void ml_cpu_down(void);
b0d623f7
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131
132void bzero_phys_nc(
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133 addr64_t phys_address,
134 uint32_t length);
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135extern uint32_t interrupt_timer_coalescing_enabled;
136extern uint32_t idle_entry_timer_processing_hdeadline_threshold;
137
138#if TCOAL_INSTRUMENT
139#define TCOAL_DEBUG KERNEL_DEBUG_CONSTANT
140#else
141#define TCOAL_DEBUG(x, a, b, c, d, e) do { } while(0)
142#endif /* TCOAL_INSTRUMENT */
b0d623f7 143
0a7de745 144#if defined(PEXPERT_KERNEL_PRIVATE) || defined(MACH_KERNEL_PRIVATE)
b0d623f7
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145/* IO memory map services */
146
147/* Map memory map IO space */
148vm_offset_t ml_io_map(
0a7de745 149 vm_offset_t phys_addr,
b0d623f7
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150 vm_size_t size);
151
b0d623f7 152
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153void ml_get_bouncepool_info(
154 vm_offset_t *phys_addr,
155 vm_size_t *size);
060df5ea
A
156/* Indicates if spinlock, IPI and other timeouts should be suspended */
157boolean_t machine_timeout_suspended(void);
39037602 158void plctrace_disable(void);
b0d623f7
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159#endif /* PEXPERT_KERNEL_PRIVATE || MACH_KERNEL_PRIVATE */
160
6d2010ae
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161/* Warm up a CPU to receive an interrupt */
162kern_return_t ml_interrupt_prewarm(uint64_t deadline);
060df5ea 163
5ba3f43e
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164/* Check if the machine layer wants to intercept a panic call */
165boolean_t ml_wants_panic_trap_to_debugger(void);
166
167/* Machine layer routine for intercepting panics */
168void ml_panic_trap_to_debugger(const char *panic_format_str,
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169 va_list *panic_args,
170 unsigned int reason,
171 void *ctx,
172 uint64_t panic_options_mask,
173 unsigned long panic_caller);
b0d623f7
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174#endif /* XNU_KERNEL_PRIVATE */
175
176#ifdef KERNEL_PRIVATE
177
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178/* Type for the Time Base Enable function */
179typedef void (*time_base_enable_t)(cpu_id_t cpu_id, boolean_t enable);
180
9bccf70c
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181/* Type for the IPI Hander */
182typedef void (*ipi_handler_t)(void);
183
55e303ae
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184/* Struct for ml_processor_register */
185struct ml_processor_info {
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186 cpu_id_t cpu_id;
187 boolean_t boot_cpu;
188 vm_offset_t start_paddr;
189 boolean_t supports_nap;
190 unsigned long l2cr_value;
191 time_base_enable_t time_base_enable;
55e303ae
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192};
193
194typedef struct ml_processor_info ml_processor_info_t;
195
91447636 196
9bccf70c 197/* Register a processor */
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198kern_return_t
199ml_processor_register(
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200 cpu_id_t cpu_id,
201 uint32_t lapic_id,
202 processor_t *processor_out,
203 boolean_t boot_cpu,
b0d623f7 204 boolean_t start );
0c530ab8 205
43866e37
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206/* PCI config cycle probing */
207boolean_t ml_probe_read(
208 vm_offset_t paddr,
209 unsigned int *val);
55e303ae
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210boolean_t ml_probe_read_64(
211 addr64_t paddr,
212 unsigned int *val);
43866e37
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213
214/* Read physical address byte */
215unsigned int ml_phys_read_byte(
216 vm_offset_t paddr);
55e303ae
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217unsigned int ml_phys_read_byte_64(
218 addr64_t paddr);
43866e37
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219
220/* Read physical address half word */
221unsigned int ml_phys_read_half(
222 vm_offset_t paddr);
55e303ae
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223unsigned int ml_phys_read_half_64(
224 addr64_t paddr);
43866e37
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225
226/* Read physical address word*/
227unsigned int ml_phys_read(
228 vm_offset_t paddr);
55e303ae
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229unsigned int ml_phys_read_64(
230 addr64_t paddr);
43866e37
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231unsigned int ml_phys_read_word(
232 vm_offset_t paddr);
55e303ae
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233unsigned int ml_phys_read_word_64(
234 addr64_t paddr);
43866e37
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235
236/* Read physical address double word */
237unsigned long long ml_phys_read_double(
238 vm_offset_t paddr);
55e303ae
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239unsigned long long ml_phys_read_double_64(
240 addr64_t paddr);
43866e37 241
813fb2f6
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242unsigned long long ml_io_read(uintptr_t iovaddr, int iovsz);
243unsigned int ml_io_read8(uintptr_t iovaddr);
244unsigned int ml_io_read16(uintptr_t iovaddr);
245unsigned int ml_io_read32(uintptr_t iovaddr);
246unsigned long long ml_io_read64(uintptr_t iovaddr);
247
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248extern void ml_io_write(uintptr_t vaddr, uint64_t val, int size);
249extern void ml_io_write8(uintptr_t vaddr, uint8_t val);
250extern void ml_io_write16(uintptr_t vaddr, uint16_t val);
251extern void ml_io_write32(uintptr_t vaddr, uint32_t val);
252extern void ml_io_write64(uintptr_t vaddr, uint64_t val);
253
254extern uint32_t ml_port_io_read(uint16_t ioport, int size);
255extern uint8_t ml_port_io_read8(uint16_t ioport);
256extern uint16_t ml_port_io_read16(uint16_t ioport);
257extern uint32_t ml_port_io_read32(uint16_t ioport);
258extern void ml_port_io_write(uint16_t ioport, uint32_t val, int size);
259extern void ml_port_io_write8(uint16_t ioport, uint8_t val);
260extern void ml_port_io_write16(uint16_t ioport, uint16_t val);
261extern void ml_port_io_write32(uint16_t ioport, uint32_t val);
262
43866e37
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263/* Write physical address byte */
264void ml_phys_write_byte(
265 vm_offset_t paddr, unsigned int data);
55e303ae
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266void ml_phys_write_byte_64(
267 addr64_t paddr, unsigned int data);
43866e37
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268
269/* Write physical address half word */
270void ml_phys_write_half(
271 vm_offset_t paddr, unsigned int data);
55e303ae
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272void ml_phys_write_half_64(
273 addr64_t paddr, unsigned int data);
43866e37
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274
275/* Write physical address word */
276void ml_phys_write(
277 vm_offset_t paddr, unsigned int data);
55e303ae
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278void ml_phys_write_64(
279 addr64_t paddr, unsigned int data);
43866e37
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280void ml_phys_write_word(
281 vm_offset_t paddr, unsigned int data);
55e303ae
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282void ml_phys_write_word_64(
283 addr64_t paddr, unsigned int data);
43866e37
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284
285/* Write physical address double word */
286void ml_phys_write_double(
287 vm_offset_t paddr, unsigned long long data);
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288void ml_phys_write_double_64(
289 addr64_t paddr, unsigned long long data);
43866e37 290
43866e37
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291/* Struct for ml_cpu_get_info */
292struct ml_cpu_info {
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293 uint32_t vector_unit;
294 uint32_t cache_line_size;
295 uint32_t l1_icache_size;
296 uint32_t l1_dcache_size;
297 uint32_t l2_settings;
298 uint32_t l2_cache_size;
299 uint32_t l3_settings;
300 uint32_t l3_cache_size;
43866e37
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301};
302
303typedef struct ml_cpu_info ml_cpu_info_t;
304
305/* Get processor info */
91447636 306void ml_cpu_get_info(ml_cpu_info_t *ml_cpu_info);
43866e37 307
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308void ml_thread_policy(
309 thread_t thread,
310 unsigned policy_id,
311 unsigned policy_info);
1c79356b 312
0a7de745
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313#define MACHINE_GROUP 0x00000001
314#define MACHINE_NETWORK_GROUP 0x10000000
315#define MACHINE_NETWORK_WORKLOOP 0x00000001
316#define MACHINE_NETWORK_NETISR 0x00000002
1c79356b 317
43866e37
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318/* Return the maximum number of CPUs set by ml_init_max_cpus() */
319int ml_get_max_cpus(
320 void);
321
2d21ac55
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322/*
323 * The following are in pmCPU.c not machine_routines.c.
324 */
0c530ab8
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325extern void ml_set_maxsnoop(uint32_t maxdelay);
326extern unsigned ml_get_maxsnoop(void);
327extern void ml_set_maxbusdelay(uint32_t mdelay);
328extern uint32_t ml_get_maxbusdelay(void);
593a1d5f
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329extern void ml_set_maxintdelay(uint64_t mdelay);
330extern uint64_t ml_get_maxintdelay(void);
6d2010ae 331extern boolean_t ml_get_interrupt_prewake_applicable(void);
2d21ac55
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332
333
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334extern uint64_t tmrCvt(uint64_t time, uint64_t conversion);
335
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336extern uint64_t ml_cpu_int_event_time(void);
337
b0d623f7
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338#endif /* KERNEL_PRIVATE */
339
340/* Get Interrupts Enabled */
341boolean_t ml_get_interrupts_enabled(void);
342
343/* Set Interrupts Enabled */
344boolean_t ml_set_interrupts_enabled(boolean_t enable);
0a7de745 345boolean_t ml_early_set_interrupts_enabled(boolean_t enable);
b0d623f7
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346
347/* Check if running at interrupt context */
348boolean_t ml_at_interrupt_context(void);
349
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350#ifdef XNU_KERNEL_PRIVATE
351extern boolean_t ml_is_quiescing(void);
352extern void ml_set_is_quiescing(boolean_t);
353extern uint64_t ml_get_booter_memory_size(void);
354#endif
355
b0d623f7
A
356/* Zero bytes starting at a physical address */
357void bzero_phys(
358 addr64_t phys_address,
359 uint32_t length);
360
361/* Bytes available on current stack */
362vm_offset_t ml_stack_remaining(void);
363
91447636 364__END_DECLS
813fb2f6 365#if defined(MACH_KERNEL_PRIVATE)
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366__private_extern__ uint64_t ml_phys_read_data(uint64_t paddr, int psz);
367__private_extern__ void ml_phys_write_data(uint64_t paddr,
368 unsigned long long data, int size);
369__private_extern__ uintptr_t
813fb2f6
A
370pmap_verify_noncacheable(uintptr_t vaddr);
371#endif /* MACH_KERNEL_PRIVATE */
0a7de745 372#ifdef XNU_KERNEL_PRIVATE
316670eb 373
6d2010ae 374boolean_t ml_fpu_avx_enabled(void);
5ba3f43e
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375#if !defined(RC_HIDE_XNU_J137)
376boolean_t ml_fpu_avx512_enabled(void);
377#endif
316670eb 378
6d2010ae
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379void interrupt_latency_tracker_setup(void);
380void interrupt_reset_latency_stats(void);
381void interrupt_populate_latency_stats(char *, unsigned);
4b17d6b6 382void ml_get_power_state(boolean_t *, boolean_t *);
060df5ea 383
39236c6e
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384void timer_queue_expire_local(void*);
385void timer_queue_expire_rescan(void*);
386void ml_timer_evaluate(void);
387boolean_t ml_timer_forced_evaluation(void);
39236c6e 388
39037602 389uint64_t ml_energy_stat(thread_t);
fe8ab488
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390void ml_gpu_stat_update(uint64_t);
391uint64_t ml_gpu_stat(thread_t);
143464d5 392boolean_t ml_recent_wake(void);
3e170ce0 393
0a7de745
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394#define ALL_CORES_RECOMMENDED (~(uint64_t)0)
395
396extern void sched_usercontrol_update_recommended_cores(uint64_t recommended_cores);
397
398
3e170ce0 399extern uint64_t reportphyreaddelayabs;
0a7de745 400extern uint64_t reportphywritedelayabs;
3e170ce0 401extern uint32_t reportphyreadosbt;
0a7de745 402extern uint32_t reportphywriteosbt;
813fb2f6 403extern uint32_t phyreadpanic;
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404extern uint32_t phywritepanic;
405extern uint64_t tracephyreaddelayabs;
406extern uint64_t tracephywritedelayabs;
3e170ce0 407
6d2010ae 408#endif /* XNU_KERNEL_PRIVATE */
1c79356b 409#endif /* _I386_MACHINE_ROUTINES_H_ */