[apple/xnu.git] / osfmk / i386 / machine_routines.h

/*
 * Copyright (c) 2000-2009 Apple Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */

#ifndef	_I386_MACHINE_ROUTINES_H_
#define	_I386_MACHINE_ROUTINES_H_

#include <mach/mach_types.h>
#include <mach/boolean.h>
#include <kern/kern_types.h>
#include <pexpert/pexpert.h>

#include <sys/cdefs.h>
#include <sys/appleapiopts.h>

__BEGIN_DECLS

#ifdef XNU_KERNEL_PRIVATE

/* are we a 64 bit platform ? */

boolean_t ml_is64bit(void);

/* is this a 64bit thread? */

boolean_t ml_thread_is64bit(thread_t);

/* is this a 64bit thread? */

boolean_t ml_state_is64bit(void *);

/* set state of fpu save area for signal handling */

void	ml_fp_setvalid(boolean_t);

void	ml_cpu_set_ldt(int);

/* Interrupt handling */

/* Initialize Interrupts */
void    ml_init_interrupt(void);

/* Generate a fake interrupt */
void ml_cause_interrupt(void);

/* Initialize Interrupts */
void ml_install_interrupt_handler(
    void *nub,
    int source,
    void *target,
    IOInterruptHandler handler,
    void *refCon);

void ml_get_timebase(unsigned long long *timestamp);
void ml_init_lock_timeout(void); 
void ml_init_delay_spin_threshold(int);

boolean_t ml_delay_should_spin(uint64_t interval);

vm_offset_t
ml_static_ptovirt(
	vm_offset_t);

void ml_static_mfree(
	vm_offset_t,
	vm_size_t);

/* boot memory allocation */
vm_offset_t ml_static_malloc(
	vm_size_t size);

/* virtual to physical on wired pages */
vm_offset_t ml_vtophys(
	vm_offset_t vaddr);

vm_size_t ml_nofault_copy(
	vm_offset_t virtsrc, vm_offset_t virtdst, vm_size_t size);

boolean_t ml_validate_nofault(
	vm_offset_t virtsrc, vm_size_t size);

/* Machine topology info */
uint64_t ml_cpu_cache_size(unsigned int level);	
uint64_t ml_cpu_cache_sharing(unsigned int level);	

/* Initialize the maximum number of CPUs */
void ml_init_max_cpus(
	unsigned long max_cpus);

extern void	ml_cpu_up(void);
extern void	ml_cpu_down(void);

void bzero_phys_nc(
				   addr64_t phys_address,
				   uint32_t length);
#define NUM_LATENCY_QOS_TIERS (6)
typedef struct {
	int32_t timer_coalesce_rt_shift;
	int32_t timer_coalesce_bg_shift;
	int32_t timer_coalesce_kt_shift;
	int32_t timer_coalesce_fp_shift;
	int32_t timer_coalesce_ts_shift;

	uint64_t timer_coalesce_rt_ns_max;
	uint64_t timer_coalesce_bg_ns_max;
	uint64_t timer_coalesce_kt_ns_max;
	uint64_t timer_coalesce_fp_ns_max;
	uint64_t timer_coalesce_ts_ns_max;

	uint32_t latency_qos_scale[NUM_LATENCY_QOS_TIERS];
	uint64_t latency_qos_ns_max[NUM_LATENCY_QOS_TIERS];
	boolean_t latency_tier_rate_limited[NUM_LATENCY_QOS_TIERS];
} timer_coalescing_priority_params_t;
extern timer_coalescing_priority_params_t tcoal_prio_params;
extern uint32_t interrupt_timer_coalescing_enabled;
extern uint32_t idle_entry_timer_processing_hdeadline_threshold;

#if TCOAL_INSTRUMENT
#define TCOAL_DEBUG KERNEL_DEBUG_CONSTANT
#else
#define TCOAL_DEBUG(x, a, b, c, d, e) do { } while(0)
#endif /* TCOAL_INSTRUMENT */

#if	defined(PEXPERT_KERNEL_PRIVATE) || defined(MACH_KERNEL_PRIVATE)
/* IO memory map services */

/* Map memory map IO space */
vm_offset_t ml_io_map(
	vm_offset_t phys_addr, 
	vm_size_t size);


void	ml_get_bouncepool_info(
			       vm_offset_t *phys_addr,
			       vm_size_t   *size);
/* Indicates if spinlock, IPI and other timeouts should be suspended */
boolean_t machine_timeout_suspended(void);
#endif /* PEXPERT_KERNEL_PRIVATE || MACH_KERNEL_PRIVATE  */

/* Warm up a CPU to receive an interrupt */
kern_return_t ml_interrupt_prewarm(uint64_t deadline);

#endif /* XNU_KERNEL_PRIVATE */

#ifdef KERNEL_PRIVATE

/* Type for the Time Base Enable function */
typedef void (*time_base_enable_t)(cpu_id_t cpu_id, boolean_t enable);

/* Type for the IPI Hander */
typedef void (*ipi_handler_t)(void);

/* Struct for ml_processor_register */
struct ml_processor_info {
	cpu_id_t			cpu_id;
	boolean_t			boot_cpu;
	vm_offset_t			start_paddr;
	boolean_t			supports_nap;
	unsigned long		l2cr_value;
	time_base_enable_t	time_base_enable;
};

typedef struct ml_processor_info ml_processor_info_t;


/* Register a processor */
kern_return_t
ml_processor_register(
        cpu_id_t        cpu_id,
        uint32_t        lapic_id,
        processor_t     *processor_out,
        boolean_t       boot_cpu,
	boolean_t       start );

/* PCI config cycle probing */
boolean_t ml_probe_read(
	vm_offset_t paddr,
	unsigned int *val);
boolean_t ml_probe_read_64(
	addr64_t paddr,
	unsigned int *val);

/* Read physical address byte */
unsigned int ml_phys_read_byte(
	vm_offset_t paddr);
unsigned int ml_phys_read_byte_64(
	addr64_t paddr);

/* Read physical address half word */
unsigned int ml_phys_read_half(
	vm_offset_t paddr);
unsigned int ml_phys_read_half_64(
	addr64_t paddr);

/* Read physical address word*/
unsigned int ml_phys_read(
	vm_offset_t paddr);
unsigned int ml_phys_read_64(
	addr64_t paddr);
unsigned int ml_phys_read_word(
	vm_offset_t paddr);
unsigned int ml_phys_read_word_64(
	addr64_t paddr);

/* Read physical address double word */
unsigned long long ml_phys_read_double(
	vm_offset_t paddr);
unsigned long long ml_phys_read_double_64(
	addr64_t paddr);

/* Write physical address byte */
void ml_phys_write_byte(
	vm_offset_t paddr, unsigned int data);
void ml_phys_write_byte_64(
	addr64_t paddr, unsigned int data);

/* Write physical address half word */
void ml_phys_write_half(
	vm_offset_t paddr, unsigned int data);
void ml_phys_write_half_64(
	addr64_t paddr, unsigned int data);

/* Write physical address word */
void ml_phys_write(
	vm_offset_t paddr, unsigned int data);
void ml_phys_write_64(
	addr64_t paddr, unsigned int data);
void ml_phys_write_word(
	vm_offset_t paddr, unsigned int data);
void ml_phys_write_word_64(
	addr64_t paddr, unsigned int data);

/* Write physical address double word */
void ml_phys_write_double(
	vm_offset_t paddr, unsigned long long data);
void ml_phys_write_double_64(
	addr64_t paddr, unsigned long long data);

/* Struct for ml_cpu_get_info */
struct ml_cpu_info {
	uint32_t	vector_unit;
	uint32_t	cache_line_size;
	uint32_t	l1_icache_size;
	uint32_t	l1_dcache_size;
	uint32_t	l2_settings;
	uint32_t	l2_cache_size;
	uint32_t	l3_settings;
	uint32_t	l3_cache_size;
};

typedef struct ml_cpu_info ml_cpu_info_t;

/* Get processor info */
void ml_cpu_get_info(ml_cpu_info_t *ml_cpu_info);

void ml_thread_policy(
	thread_t thread,
	unsigned policy_id,
	unsigned policy_info);

#define MACHINE_GROUP					0x00000001
#define MACHINE_NETWORK_GROUP			0x10000000
#define MACHINE_NETWORK_WORKLOOP		0x00000001
#define MACHINE_NETWORK_NETISR			0x00000002

/* Return the maximum number of CPUs set by ml_init_max_cpus() */
int ml_get_max_cpus(
	void);

/*
 * The following are in pmCPU.c not machine_routines.c.
 */
extern void ml_set_maxsnoop(uint32_t maxdelay);
extern unsigned ml_get_maxsnoop(void);
extern void ml_set_maxbusdelay(uint32_t mdelay);
extern uint32_t ml_get_maxbusdelay(void);
extern void ml_set_maxintdelay(uint64_t mdelay);
extern uint64_t ml_get_maxintdelay(void);
extern boolean_t ml_get_interrupt_prewake_applicable(void);


extern uint64_t tmrCvt(uint64_t time, uint64_t conversion);

extern uint64_t ml_cpu_int_event_time(void);

#endif /* KERNEL_PRIVATE */

/* Get Interrupts Enabled */
boolean_t ml_get_interrupts_enabled(void);

/* Set Interrupts Enabled */
boolean_t ml_set_interrupts_enabled(boolean_t enable);

/* Check if running at interrupt context */
boolean_t ml_at_interrupt_context(void);

/* Zero bytes starting at a physical address */
void bzero_phys(
	addr64_t phys_address,
	uint32_t length);

/* Bytes available on current stack */
vm_offset_t ml_stack_remaining(void);

#if CONFIG_COUNTERS
void ml_get_csw_threads(thread_t * /*old*/, thread_t * /*new*/);
#endif /* CONFIG_COUNTERS */

__END_DECLS

#ifdef	XNU_KERNEL_PRIVATE

boolean_t ml_fpu_avx_enabled(void);

void interrupt_latency_tracker_setup(void);
void interrupt_reset_latency_stats(void);
void interrupt_populate_latency_stats(char *, unsigned);
void ml_get_power_state(boolean_t *, boolean_t *);

void timer_queue_expire_local(void*);
void timer_queue_expire_rescan(void*);
void ml_timer_evaluate(void);
boolean_t ml_timer_forced_evaluation(void);
int ml_timer_get_user_idle_level(void);
kern_return_t ml_timer_set_user_idle_level(int);

#endif /* XNU_KERNEL_PRIVATE */
#endif /* _I386_MACHINE_ROUTINES_H_ */
Commit	Line	Data
1c79356b	1	/*
b0d623f7	2	* Copyright (c) 2000-2009 Apple Inc. All rights reserved.
1c79356b	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
1c79356b	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b A	27	*/
	28	/*
	29	* @OSF_COPYRIGHT@
	30	*/
	31
	32	#ifndef _I386_MACHINE_ROUTINES_H_
	33	#define _I386_MACHINE_ROUTINES_H_
	34
	35	#include <mach/mach_types.h>
	36	#include <mach/boolean.h>
	37	#include <kern/kern_types.h>
	38	#include <pexpert/pexpert.h>
	39
91447636	40	#include <sys/cdefs.h>
9bccf70c	41	#include <sys/appleapiopts.h>
1c79356b	42
91447636 A	43	__BEGIN_DECLS
91447636 A	44
b0d623f7 A	45	#ifdef XNU_KERNEL_PRIVATE
b0d623f7 A	46
0c530ab8 A	47	/* are we a 64 bit platform ? */
	48
	49	boolean_t ml_is64bit(void);
	50
	51	/* is this a 64bit thread? */
	52
	53	boolean_t ml_thread_is64bit(thread_t);
	54
	55	/* is this a 64bit thread? */
	56
	57	boolean_t ml_state_is64bit(void *);
	58
	59	/* set state of fpu save area for signal handling */
	60
	61	void ml_fp_setvalid(boolean_t);
	62
	63	void ml_cpu_set_ldt(int);
	64
1c79356b A	65	/* Interrupt handling */
1c79356b A	66
55e303ae A	67	/* Initialize Interrupts */
	68	void ml_init_interrupt(void);
	69
1c79356b A	70	/* Generate a fake interrupt */
	71	void ml_cause_interrupt(void);
	72
b0d623f7 A	73	/* Initialize Interrupts */
	74	void ml_install_interrupt_handler(
	75	void *nub,
	76	int source,
	77	void *target,
	78	IOInterruptHandler handler,
	79	void *refCon);
	80
9bccf70c	81	void ml_get_timebase(unsigned long long *timestamp);
0c530ab8	82	void ml_init_lock_timeout(void);
bd504ef0	83	void ml_init_delay_spin_threshold(int);
316670eb A	84
316670eb A	85	boolean_t ml_delay_should_spin(uint64_t interval);
d52fe63f	86
b0d623f7 A	87	vm_offset_t
	88	ml_static_ptovirt(
	89	vm_offset_t);
	90
	91	void ml_static_mfree(
	92	vm_offset_t,
	93	vm_size_t);
	94
	95	/* boot memory allocation */
	96	vm_offset_t ml_static_malloc(
	97	vm_size_t size);
	98
	99	/* virtual to physical on wired pages */
	100	vm_offset_t ml_vtophys(
	101	vm_offset_t vaddr);
	102
	103	vm_size_t ml_nofault_copy(
	104	vm_offset_t virtsrc, vm_offset_t virtdst, vm_size_t size);
	105
39236c6e A	106	boolean_t ml_validate_nofault(
	107	vm_offset_t virtsrc, vm_size_t size);
	108
b0d623f7 A	109	/* Machine topology info */
	110	uint64_t ml_cpu_cache_size(unsigned int level);
	111	uint64_t ml_cpu_cache_sharing(unsigned int level);
	112
	113	/* Initialize the maximum number of CPUs */
	114	void ml_init_max_cpus(
	115	unsigned long max_cpus);
	116
	117	extern void ml_cpu_up(void);
	118	extern void ml_cpu_down(void);
	119
	120	void bzero_phys_nc(
	121	addr64_t phys_address,
	122	uint32_t length);
39236c6e A	123	#define NUM_LATENCY_QOS_TIERS (6)
	124	typedef struct {
	125	int32_t timer_coalesce_rt_shift;
	126	int32_t timer_coalesce_bg_shift;
	127	int32_t timer_coalesce_kt_shift;
	128	int32_t timer_coalesce_fp_shift;
	129	int32_t timer_coalesce_ts_shift;
	130
	131	uint64_t timer_coalesce_rt_ns_max;
	132	uint64_t timer_coalesce_bg_ns_max;
	133	uint64_t timer_coalesce_kt_ns_max;
	134	uint64_t timer_coalesce_fp_ns_max;
	135	uint64_t timer_coalesce_ts_ns_max;
	136
	137	uint32_t latency_qos_scale[NUM_LATENCY_QOS_TIERS];
	138	uint64_t latency_qos_ns_max[NUM_LATENCY_QOS_TIERS];
	139	boolean_t latency_tier_rate_limited[NUM_LATENCY_QOS_TIERS];
	140	} timer_coalescing_priority_params_t;
	141	extern timer_coalescing_priority_params_t tcoal_prio_params;
	142	extern uint32_t interrupt_timer_coalescing_enabled;
	143	extern uint32_t idle_entry_timer_processing_hdeadline_threshold;
	144
	145	#if TCOAL_INSTRUMENT
	146	#define TCOAL_DEBUG KERNEL_DEBUG_CONSTANT
	147	#else
	148	#define TCOAL_DEBUG(x, a, b, c, d, e) do { } while(0)
	149	#endif /* TCOAL_INSTRUMENT */
b0d623f7 A	150
	151	#if defined(PEXPERT_KERNEL_PRIVATE) \|\| defined(MACH_KERNEL_PRIVATE)
	152	/* IO memory map services */
	153
	154	/* Map memory map IO space */
	155	vm_offset_t ml_io_map(
	156	vm_offset_t phys_addr,
	157	vm_size_t size);
	158
b0d623f7 A	159
	160	void ml_get_bouncepool_info(
	161	vm_offset_t *phys_addr,
	162	vm_size_t *size);
060df5ea A	163	/* Indicates if spinlock, IPI and other timeouts should be suspended */
060df5ea A	164	boolean_t machine_timeout_suspended(void);
b0d623f7 A	165	#endif /* PEXPERT_KERNEL_PRIVATE \|\| MACH_KERNEL_PRIVATE */
b0d623f7 A	166
6d2010ae A	167	/* Warm up a CPU to receive an interrupt */
6d2010ae A	168	kern_return_t ml_interrupt_prewarm(uint64_t deadline);
060df5ea	169
b0d623f7 A	170	#endif /* XNU_KERNEL_PRIVATE */
	171
	172	#ifdef KERNEL_PRIVATE
	173
55e303ae A	174	/* Type for the Time Base Enable function */
	175	typedef void (*time_base_enable_t)(cpu_id_t cpu_id, boolean_t enable);
	176
9bccf70c A	177	/* Type for the IPI Hander */
	178	typedef void (*ipi_handler_t)(void);
	179
55e303ae A	180	/* Struct for ml_processor_register */
	181	struct ml_processor_info {
	182	cpu_id_t cpu_id;
	183	boolean_t boot_cpu;
	184	vm_offset_t start_paddr;
	185	boolean_t supports_nap;
	186	unsigned long l2cr_value;
	187	time_base_enable_t time_base_enable;
	188	};
	189
	190	typedef struct ml_processor_info ml_processor_info_t;
	191
91447636	192
9bccf70c	193	/* Register a processor */
b0d623f7 A	194	kern_return_t
	195	ml_processor_register(
	196	cpu_id_t cpu_id,
	197	uint32_t lapic_id,
	198	processor_t *processor_out,
	199	boolean_t boot_cpu,
	200	boolean_t start );
0c530ab8	201
43866e37 A	202	/* PCI config cycle probing */
	203	boolean_t ml_probe_read(
	204	vm_offset_t paddr,
	205	unsigned int *val);
55e303ae A	206	boolean_t ml_probe_read_64(
	207	addr64_t paddr,
	208	unsigned int *val);
43866e37 A	209
	210	/* Read physical address byte */
	211	unsigned int ml_phys_read_byte(
	212	vm_offset_t paddr);
55e303ae A	213	unsigned int ml_phys_read_byte_64(
55e303ae A	214	addr64_t paddr);
43866e37 A	215
	216	/* Read physical address half word */
	217	unsigned int ml_phys_read_half(
	218	vm_offset_t paddr);
55e303ae A	219	unsigned int ml_phys_read_half_64(
55e303ae A	220	addr64_t paddr);
43866e37 A	221
	222	/* Read physical address word*/
	223	unsigned int ml_phys_read(
	224	vm_offset_t paddr);
55e303ae A	225	unsigned int ml_phys_read_64(
55e303ae A	226	addr64_t paddr);
43866e37 A	227	unsigned int ml_phys_read_word(
43866e37 A	228	vm_offset_t paddr);
55e303ae A	229	unsigned int ml_phys_read_word_64(
55e303ae A	230	addr64_t paddr);
43866e37 A	231
	232	/* Read physical address double word */
	233	unsigned long long ml_phys_read_double(
	234	vm_offset_t paddr);
55e303ae A	235	unsigned long long ml_phys_read_double_64(
55e303ae A	236	addr64_t paddr);
43866e37 A	237
	238	/* Write physical address byte */
	239	void ml_phys_write_byte(
	240	vm_offset_t paddr, unsigned int data);
55e303ae A	241	void ml_phys_write_byte_64(
55e303ae A	242	addr64_t paddr, unsigned int data);
43866e37 A	243
	244	/* Write physical address half word */
	245	void ml_phys_write_half(
	246	vm_offset_t paddr, unsigned int data);
55e303ae A	247	void ml_phys_write_half_64(
55e303ae A	248	addr64_t paddr, unsigned int data);
43866e37 A	249
	250	/* Write physical address word */
	251	void ml_phys_write(
	252	vm_offset_t paddr, unsigned int data);
55e303ae A	253	void ml_phys_write_64(
55e303ae A	254	addr64_t paddr, unsigned int data);
43866e37 A	255	void ml_phys_write_word(
43866e37 A	256	vm_offset_t paddr, unsigned int data);
55e303ae A	257	void ml_phys_write_word_64(
55e303ae A	258	addr64_t paddr, unsigned int data);
43866e37 A	259
	260	/* Write physical address double word */
	261	void ml_phys_write_double(
	262	vm_offset_t paddr, unsigned long long data);
55e303ae A	263	void ml_phys_write_double_64(
55e303ae A	264	addr64_t paddr, unsigned long long data);
43866e37	265
43866e37 A	266	/* Struct for ml_cpu_get_info */
43866e37 A	267	struct ml_cpu_info {
6d2010ae A	268	uint32_t vector_unit;
	269	uint32_t cache_line_size;
	270	uint32_t l1_icache_size;
	271	uint32_t l1_dcache_size;
	272	uint32_t l2_settings;
	273	uint32_t l2_cache_size;
	274	uint32_t l3_settings;
	275	uint32_t l3_cache_size;
43866e37 A	276	};
	277
	278	typedef struct ml_cpu_info ml_cpu_info_t;
	279
	280	/* Get processor info */
91447636	281	void ml_cpu_get_info(ml_cpu_info_t *ml_cpu_info);
43866e37	282
9bccf70c A	283	void ml_thread_policy(
	284	thread_t thread,
	285	unsigned policy_id,
	286	unsigned policy_info);
1c79356b	287
9bccf70c A	288	#define MACHINE_GROUP 0x00000001
	289	#define MACHINE_NETWORK_GROUP 0x10000000
	290	#define MACHINE_NETWORK_WORKLOOP 0x00000001
	291	#define MACHINE_NETWORK_NETISR 0x00000002
1c79356b	292
43866e37 A	293	/* Return the maximum number of CPUs set by ml_init_max_cpus() */
	294	int ml_get_max_cpus(
	295	void);
	296
2d21ac55 A	297	/*
	298	* The following are in pmCPU.c not machine_routines.c.
	299	*/
0c530ab8 A	300	extern void ml_set_maxsnoop(uint32_t maxdelay);
	301	extern unsigned ml_get_maxsnoop(void);
	302	extern void ml_set_maxbusdelay(uint32_t mdelay);
	303	extern uint32_t ml_get_maxbusdelay(void);
593a1d5f A	304	extern void ml_set_maxintdelay(uint64_t mdelay);
593a1d5f A	305	extern uint64_t ml_get_maxintdelay(void);
6d2010ae	306	extern boolean_t ml_get_interrupt_prewake_applicable(void);
2d21ac55 A	307
2d21ac55 A	308
0c530ab8 A	309	extern uint64_t tmrCvt(uint64_t time, uint64_t conversion);
0c530ab8 A	310
2d21ac55 A	311	extern uint64_t ml_cpu_int_event_time(void);
2d21ac55 A	312
b0d623f7 A	313	#endif /* KERNEL_PRIVATE */
	314
	315	/* Get Interrupts Enabled */
	316	boolean_t ml_get_interrupts_enabled(void);
	317
	318	/* Set Interrupts Enabled */
	319	boolean_t ml_set_interrupts_enabled(boolean_t enable);
	320
	321	/* Check if running at interrupt context */
	322	boolean_t ml_at_interrupt_context(void);
	323
	324	/* Zero bytes starting at a physical address */
	325	void bzero_phys(
	326	addr64_t phys_address,
	327	uint32_t length);
	328
	329	/* Bytes available on current stack */
	330	vm_offset_t ml_stack_remaining(void);
	331
	332	#if CONFIG_COUNTERS
	333	void ml_get_csw_threads(thread_t * /old/, thread_t * /new/);
	334	#endif /* CONFIG_COUNTERS */
1c79356b	335
91447636 A	336	__END_DECLS
91447636 A	337
6d2010ae	338	#ifdef XNU_KERNEL_PRIVATE
316670eb	339
6d2010ae	340	boolean_t ml_fpu_avx_enabled(void);
316670eb	341
6d2010ae A	342	void interrupt_latency_tracker_setup(void);
	343	void interrupt_reset_latency_stats(void);
	344	void interrupt_populate_latency_stats(char *, unsigned);
4b17d6b6	345	void ml_get_power_state(boolean_t , boolean_t );
060df5ea	346
39236c6e A	347	void timer_queue_expire_local(void*);
	348	void timer_queue_expire_rescan(void*);
	349	void ml_timer_evaluate(void);
	350	boolean_t ml_timer_forced_evaluation(void);
	351	int ml_timer_get_user_idle_level(void);
	352	kern_return_t ml_timer_set_user_idle_level(int);
	353
6d2010ae	354	#endif /* XNU_KERNEL_PRIVATE */
1c79356b	355	#endif /* _I386_MACHINE_ROUTINES_H_ */