xnu-4570.31.3.tar.gz

[apple/xnu.git] / osfmk / i386 / mp_native.c

diff --git a/osfmk/i386/mp_native.c b/osfmk/i386/mp_native.c
index ea379978071846753499f7ffbe1160ea711bca07..e64344db7230893bb8f78858649532b8cce76aa0 100644 (file)
--- a/osfmk/i386/mp_native.c
+++ b/osfmk/i386/mp_native.c
@@ -33,6 +33,7 @@
 #include <i386/machine_routines.h>
 #include <i386/cpu_data.h>
 #include <i386/pmap.h>
+#include <i386/bit_routines.h>
 
 /* PAL-related routines */
 void i386_cpu_IPI(int cpu);
@@ -41,6 +42,7 @@ boolean_t i386_smp_init(int nmi_vector, i386_intr_func_t nmi_handler,
 void i386_start_cpu(int lapic_id, int cpu_num);
 void i386_send_NMI(int cpu);
 void handle_pending_TLB_flushes(void);
+void NMIPI_enable(boolean_t);
 
 extern void    slave_pstart(void);
 
@@ -68,24 +70,33 @@ i386_smp_init(int nmi_vector, i386_intr_func_t nmi_handler, int ipi_vector, i386
 void
 i386_start_cpu(int lapic_id, __unused int cpu_num )
 {
-       LAPIC_WRITE(ICRD, lapic_id << LAPIC_ICRD_DEST_SHIFT);
-       LAPIC_WRITE(ICR, LAPIC_ICR_DM_INIT);
+       LAPIC_WRITE_ICR(lapic_id, LAPIC_ICR_DM_INIT);
        delay(100);
+       LAPIC_WRITE_ICR(lapic_id,
+                       LAPIC_ICR_DM_STARTUP|(REAL_MODE_BOOTSTRAP_OFFSET>>12));
+}
+
+static boolean_t NMIPIs_enabled = FALSE;
 
-       LAPIC_WRITE(ICRD, lapic_id << LAPIC_ICRD_DEST_SHIFT);
-       LAPIC_WRITE(ICR, LAPIC_ICR_DM_STARTUP|(REAL_MODE_BOOTSTRAP_OFFSET>>12));
+void NMIPI_enable(boolean_t enable) {
+       NMIPIs_enabled = enable;
 }
 
 void
 i386_send_NMI(int cpu)
 {
        boolean_t state = ml_set_interrupts_enabled(FALSE);
+
+       if (NMIPIs_enabled == FALSE) {
+               i386_cpu_IPI(cpu);
+       } else {
        /* Program the interrupt command register */
-       LAPIC_WRITE(ICRD, cpu_to_lapic[cpu] << LAPIC_ICRD_DEST_SHIFT);
        /* The vector is ignored in this case--the target CPU will enter on the
         * NMI vector.
         */
-       LAPIC_WRITE(ICR, LAPIC_VECTOR(INTERPROCESSOR)|LAPIC_ICR_DM_NMI);
+       LAPIC_WRITE_ICR(cpu_to_lapic[cpu],
+                       LAPIC_VECTOR(INTERPROCESSOR)|LAPIC_ICR_DM_NMI);
+       }
        (void) ml_set_interrupts_enabled(state);
 }