X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/316670eb35587141e969394ae8537d66b9211e80..5c9f46613a83ebfc29a5b1f099448259e96a98f0:/osfmk/i386/mp_native.c

diff --git a/osfmk/i386/mp_native.c b/osfmk/i386/mp_native.c
index ea3799780..e64344db7 100644
--- a/osfmk/i386/mp_native.c
+++ b/osfmk/i386/mp_native.c
@@ -33,6 +33,7 @@
 #include <i386/machine_routines.h>
 #include <i386/cpu_data.h>
 #include <i386/pmap.h>
+#include <i386/bit_routines.h>
 
 /* PAL-related routines */
 void i386_cpu_IPI(int cpu);
@@ -41,6 +42,7 @@ boolean_t i386_smp_init(int nmi_vector, i386_intr_func_t nmi_handler,
 void i386_start_cpu(int lapic_id, int cpu_num);
 void i386_send_NMI(int cpu);
 void handle_pending_TLB_flushes(void);
+void NMIPI_enable(boolean_t);
 
 extern void	slave_pstart(void);
 
@@ -68,24 +70,33 @@ i386_smp_init(int nmi_vector, i386_intr_func_t nmi_handler, int ipi_vector, i386
 void
 i386_start_cpu(int lapic_id, __unused int cpu_num )
 {
-	LAPIC_WRITE(ICRD, lapic_id << LAPIC_ICRD_DEST_SHIFT);
-	LAPIC_WRITE(ICR, LAPIC_ICR_DM_INIT);
+	LAPIC_WRITE_ICR(lapic_id, LAPIC_ICR_DM_INIT);
 	delay(100);
+	LAPIC_WRITE_ICR(lapic_id,
+			LAPIC_ICR_DM_STARTUP|(REAL_MODE_BOOTSTRAP_OFFSET>>12));
+}
+
+static boolean_t NMIPIs_enabled = FALSE;
 
-	LAPIC_WRITE(ICRD, lapic_id << LAPIC_ICRD_DEST_SHIFT);
-	LAPIC_WRITE(ICR, LAPIC_ICR_DM_STARTUP|(REAL_MODE_BOOTSTRAP_OFFSET>>12));
+void NMIPI_enable(boolean_t enable) {
+	NMIPIs_enabled = enable;
 }
 
 void
 i386_send_NMI(int cpu)
 {
 	boolean_t state = ml_set_interrupts_enabled(FALSE);
+
+	if (NMIPIs_enabled == FALSE) {
+		i386_cpu_IPI(cpu);
+	} else {
 	/* Program the interrupt command register */
-	LAPIC_WRITE(ICRD, cpu_to_lapic[cpu] << LAPIC_ICRD_DEST_SHIFT);
 	/* The vector is ignored in this case--the target CPU will enter on the
 	 * NMI vector.
 	 */
-	LAPIC_WRITE(ICR, LAPIC_VECTOR(INTERPROCESSOR)|LAPIC_ICR_DM_NMI);
+	LAPIC_WRITE_ICR(cpu_to_lapic[cpu],
+			LAPIC_VECTOR(INTERPROCESSOR)|LAPIC_ICR_DM_NMI);
+	}
 	(void) ml_set_interrupts_enabled(state);
 }