tests/fp_exception.c

   1 /*
   2  * Copyright (c) 2019 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /**
  29  * On devices that support it, this test ensures that a mach exception is
  30  * generated when an ARMv8 floating point exception is triggered.
  31  * Also verifies that the main thread's FPCR value matches its expected default.
  32  */
  33 #include <darwintest.h>
  34 #include <stdbool.h>
  35 #include <stdint.h>
  36 #include <stdio.h>
  37 #include <stdlib.h>
  38 #include <mach/mach.h>
  39 #include <mach/thread_status.h>
  40 #include <sys/sysctl.h>
  41 #include <inttypes.h>
  42
  43 #include "exc_helpers.h"
  44
  45 T_GLOBAL_META(T_META_RUN_CONCURRENTLY(true));
  46
  47 /* The bit to set in FPCR to enable the divide-by-zero floating point exception. */
  48 #define FPCR_DIV_EXC 0x200
  49 #define FPCR_INIT (0x0)
  50
  51 /* Whether we caught the EXC_ARITHMETIC mach exception or not. */
  52 static volatile bool mach_exc_caught = false;
  53
  54 #ifdef __arm64__
  55 static size_t
  56 exc_arithmetic_handler(
  57         __unused mach_port_t task,
  58         __unused mach_port_t thread,
  59         exception_type_t type,
  60         mach_exception_data_t codes_64)
  61 {
  62         /* Floating point divide by zero should cause an EXC_ARITHMETIC exception. */
  63         T_ASSERT_EQ(type, EXC_ARITHMETIC, "Caught an EXC_ARITHMETIC exception");
  64
  65         /* Verify the exception is a floating point divide-by-zero exception. */
  66         T_ASSERT_EQ(codes_64[0], (mach_exception_data_type_t)EXC_ARM_FP_DZ, "The subcode is EXC_ARM_FP_DZ (floating point divide-by-zero)");
  67
  68         mach_exc_caught = true;
  69         return 4;
  70 }
  71 #endif
  72
  73 #define KERNEL_BOOTARGS_MAX_SIZE 1024
  74 static char kernel_bootargs[KERNEL_BOOTARGS_MAX_SIZE];
  75
  76 T_DECL(armv8_fp_exception,
  77     "Test that ARMv8 floating point exceptions generate Mach exceptions, verify default FPCR value.")
  78 {
  79 #ifndef __arm64__
  80         T_SKIP("Running on non-arm64 target, skipping...");
  81 #else
  82         mach_port_t exc_port = MACH_PORT_NULL;
  83         size_t kernel_bootargs_len;
  84
  85         uint64_t fpcr = __builtin_arm_rsr64("FPCR");
  86
  87         if (fpcr != FPCR_INIT) {
  88                 T_FAIL("The floating point control register has a non-default value" "%" PRIx64, fpcr);
  89         }
  90
  91         /* Attempt to enable Divide-by-Zero floating point exceptions in hardware. */
  92         uint64_t fpcr_divexc = fpcr | FPCR_DIV_EXC;
  93         __builtin_arm_wsr64("FPCR", fpcr_divexc);
  94 #define DSB_ISH 0xb
  95         __builtin_arm_dsb(DSB_ISH);
  96
  97         /* Devices that don't support floating point exceptions have FPCR as RAZ/WI. */
  98         if (__builtin_arm_rsr64("FPCR") != fpcr_divexc) {
  99                 T_SKIP("Running on a device that doesn't support floating point exceptions, skipping...");
 100         }
 101
 102         /* Check if floating-point exceptions are enabled */
 103         kernel_bootargs_len = sizeof(kernel_bootargs);
 104         kern_return_t kr = sysctlbyname("kern.bootargs", kernel_bootargs, &kernel_bootargs_len, NULL, 0);
 105         if (kr != 0) {
 106                 T_SKIP("Could not get kernel bootargs, skipping...");
 107         }
 108
 109         if (NULL == strstr(kernel_bootargs, "-fp_exceptions")) {
 110                 T_SKIP("Floating-point exceptions are disabled, skipping...");
 111         }
 112
 113         /* Create the mach port the exception messages will be sent to. */
 114         exc_port = create_exception_port(EXC_MASK_ARITHMETIC);
 115         /* Spawn the exception server's thread. */
 116         run_exception_handler(exc_port, exc_arithmetic_handler);
 117
 118         /**
 119          * This should cause a floating point divide-by-zero exception to get triggered.
 120          *
 121          * The kernel shouldn't resume this thread until the mach exception is handled
 122          * by the exception server that was just spawned. The exception handler will
 123          * explicitly increment the PC += 4 to move to the next instruction.
 124          */
 125         float a = 6.5f;
 126         float b = 0.0f;
 127         __asm volatile ("fdiv %s0, %s1, %s2" : "=w" (a) : "w" (a), "w" (b));
 128
 129         if (mach_exc_caught) {
 130                 T_PASS("The expected floating point divide-by-zero exception was caught!");
 131         } else {
 132                 T_FAIL("The floating point divide-by-zero exception was not captured :(");
 133         }
 134 #endif /* __arm64__ */
 135 }