osfmk/arm/arm_init.c

   1 /*
   2  * Copyright (c) 2007-2009 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31
  32 #include <debug.h>
  33 #include <mach_ldebug.h>
  34 #include <mach_kdp.h>
  35
  36 #include <kern/misc_protos.h>
  37 #include <kern/thread.h>
  38 #include <kern/timer_queue.h>
  39 #include <kern/processor.h>
  40 #include <kern/startup.h>
  41 #include <kern/debug.h>
  42 #include <prng/random.h>
  43 #include <machine/machine_routines.h>
  44 #include <machine/commpage.h>
  45 #if HIBERNATION
  46 #include <machine/pal_hibernate.h>
  47 #endif /* HIBERNATION */
  48 /* ARM64_TODO unify boot.h */
  49 #if __arm64__
  50 #include <pexpert/arm64/apple_arm64_common.h>
  51 #include <pexpert/arm64/boot.h>
  52 #elif __arm__
  53 #include <pexpert/arm/boot.h>
  54 #else
  55 #error Unsupported arch
  56 #endif
  57 #include <pexpert/arm/consistent_debug.h>
  58 #include <pexpert/device_tree.h>
  59 #include <arm/proc_reg.h>
  60 #include <arm/pmap.h>
  61 #include <arm/caches_internal.h>
  62 #include <arm/cpu_internal.h>
  63 #include <arm/cpu_data_internal.h>
  64 #include <arm/cpuid_internal.h>
  65 #include <arm/io_map_entries.h>
  66 #include <arm/misc_protos.h>
  67 #include <arm/machine_cpu.h>
  68 #include <arm/rtclock.h>
  69 #include <vm/vm_map.h>
  70
  71 #include <libkern/kernel_mach_header.h>
  72 #include <libkern/stack_protector.h>
  73 #include <libkern/section_keywords.h>
  74 #include <san/kasan.h>
  75 #include <sys/kdebug.h>
  76
  77 #include <pexpert/pexpert.h>
  78
  79 #include <console/serial_protos.h>
  80
  81 #if CONFIG_TELEMETRY
  82 #include <kern/telemetry.h>
  83 #endif
  84 #if MONOTONIC
  85 #include <kern/monotonic.h>
  86 #endif /* MONOTONIC */
  87
  88 #if HIBERNATION
  89 #include <IOKit/IOPlatformExpert.h>
  90 #endif /* HIBERNATION */
  91
  92 extern void     patch_low_glo(void);
  93 extern int      serial_init(void);
  94 extern void sleep_token_buffer_init(void);
  95
  96 extern vm_offset_t intstack_top;
  97 #if __arm64__
  98 extern vm_offset_t excepstack_top;
  99 #else
 100 extern vm_offset_t fiqstack_top;
 101 #endif
 102
 103 extern const char version[];
 104 extern const char version_variant[];
 105 extern int      disableConsoleOutput;
 106
 107 int             pc_trace_buf[PC_TRACE_BUF_SIZE] = {0};
 108 int             pc_trace_cnt = PC_TRACE_BUF_SIZE;
 109 int             debug_task;
 110
 111 bool need_wa_rdar_55577508 = false;
 112 SECURITY_READ_ONLY_LATE(bool) static_kernelcache = false;
 113
 114 #if HAS_BP_RET
 115 /* Enable both branch target retention (0x2) and branch direction retention (0x1) across sleep */
 116 uint32_t bp_ret = 3;
 117 extern void set_bp_ret(void);
 118 #endif
 119
 120 #if INTERRUPT_MASKED_DEBUG
 121 boolean_t interrupt_masked_debug = 1;
 122 /* the following are in mach timebase units */
 123 uint64_t interrupt_masked_timeout = 0xd0000;
 124 uint64_t stackshot_interrupt_masked_timeout = 0xf9999;
 125 #endif
 126
 127 /*
 128  * A 6-second timeout will give the watchdog code a chance to run
 129  * before a panic is triggered by the xcall routine.
 130  */
 131 #define XCALL_ACK_TIMEOUT_NS ((uint64_t) 6000000000)
 132 uint64_t xcall_ack_timeout_abstime;
 133
 134
 135 boot_args const_boot_args __attribute__((section("__DATA, __const")));
 136 boot_args      *BootArgs __attribute__((section("__DATA, __const")));
 137
 138 TUNABLE(uint32_t, arm_diag, "diag", 0);
 139 #ifdef  APPLETYPHOON
 140 static unsigned cpus_defeatures = 0x0;
 141 extern void cpu_defeatures_set(unsigned int);
 142 #endif
 143
 144 #if __arm64__ && __ARM_GLOBAL_SLEEP_BIT__
 145 extern volatile boolean_t arm64_stall_sleep;
 146 #endif
 147
 148 extern boolean_t force_immediate_debug_halt;
 149
 150 #if HAS_APPLE_PAC
 151 SECURITY_READ_ONLY_LATE(boolean_t) diversify_user_jop = TRUE;
 152 #endif
 153
 154 SECURITY_READ_ONLY_LATE(uint64_t) gDramBase;
 155 SECURITY_READ_ONLY_LATE(uint64_t) gDramSize;
 156
 157 SECURITY_READ_ONLY_LATE(bool) serial_console_enabled = false;
 158
 159 /*
 160  * Forward definition
 161  */
 162 void arm_init(boot_args * args);
 163
 164 #if __arm64__
 165 unsigned int page_shift_user32; /* for page_size as seen by a 32-bit task */
 166
 167 extern void configure_misc_apple_boot_args(void);
 168 extern void configure_misc_apple_regs(void);
 169 #endif /* __arm64__ */
 170
 171
 172 /*
 173  * JOP rebasing
 174  */
 175
 176 #define dyldLogFunc(msg, ...)
 177 #include <mach/dyld_kernel_fixups.h>
 178
 179 extern uint32_t __thread_starts_sect_start[] __asm("section$start$__TEXT$__thread_starts");
 180 extern uint32_t __thread_starts_sect_end[]   __asm("section$end$__TEXT$__thread_starts");
 181 #if defined(HAS_APPLE_PAC)
 182 extern void OSRuntimeSignStructors(kernel_mach_header_t * header);
 183 extern void OSRuntimeSignStructorsInFileset(kernel_mach_header_t * header);
 184 #endif /* defined(HAS_APPLE_PAC) */
 185
 186 extern vm_offset_t vm_kernel_slide;
 187 extern vm_offset_t segLOWESTKC, segHIGHESTKC, segLOWESTROKC, segHIGHESTROKC;
 188 extern vm_offset_t segLOWESTAuxKC, segHIGHESTAuxKC, segLOWESTROAuxKC, segHIGHESTROAuxKC;
 189 extern vm_offset_t segLOWESTRXAuxKC, segHIGHESTRXAuxKC, segHIGHESTNLEAuxKC;
 190
 191 static void
 192 arm_slide_rebase_and_sign_image(void)
 193 {
 194         kernel_mach_header_t *k_mh, *kc_mh = NULL;
 195         kernel_segment_command_t *seg;
 196         uintptr_t slide;
 197
 198         k_mh = &_mh_execute_header;
 199         if (kernel_mach_header_is_in_fileset(k_mh)) {
 200                 /*
 201                  * The kernel is part of a MH_FILESET kernel collection, determine slide
 202                  * based on first segment's mach-o vmaddr (requires first kernel load
 203                  * command to be LC_SEGMENT_64 of the __TEXT segment)
 204                  */
 205                 seg = (kernel_segment_command_t *)((uintptr_t)k_mh + sizeof(*k_mh));
 206                 assert(seg->cmd == LC_SEGMENT_KERNEL);
 207                 slide = (uintptr_t)k_mh - seg->vmaddr;
 208
 209                 /*
 210                  * The kernel collection linker guarantees that the boot collection mach
 211                  * header vmaddr is the hardcoded kernel link address (as specified to
 212                  * ld64 when linking the kernel).
 213                  */
 214                 kc_mh = (kernel_mach_header_t*)(VM_KERNEL_LINK_ADDRESS + slide);
 215                 assert(kc_mh->filetype == MH_FILESET);
 216
 217                 /*
 218                  * rebase and sign jops
 219                  * Note that we can't call any functions before this point, so
 220                  * we have to hard-code the knowledge that the base of the KC
 221                  * is the KC's mach-o header. This would change if any
 222                  * segment's VA started *before* the text segment
 223                  * (as the HIB segment does on x86).
 224                  */
 225                 const void *collection_base_pointers[KCNumKinds] = {[0] = kc_mh, };
 226                 kernel_collection_slide((struct mach_header_64 *)kc_mh, collection_base_pointers);
 227
 228                 PE_set_kc_header(KCKindPrimary, kc_mh, slide);
 229
 230                 /*
 231                  * iBoot doesn't slide load command vmaddrs in an MH_FILESET kernel
 232                  * collection, so adjust them now, and determine the vmaddr range
 233                  * covered by read-only segments for the CTRR rorgn.
 234                  */
 235                 kernel_collection_adjust_mh_addrs((struct mach_header_64 *)kc_mh, slide, false,
 236                     (uintptr_t *)&segLOWESTKC, (uintptr_t *)&segHIGHESTKC,
 237                     (uintptr_t *)&segLOWESTROKC, (uintptr_t *)&segHIGHESTROKC,
 238                     NULL, NULL, NULL);
 239 #if defined(HAS_APPLE_PAC)
 240                 OSRuntimeSignStructorsInFileset(kc_mh);
 241 #endif /* defined(HAS_APPLE_PAC) */
 242         } else {
 243                 /*
 244                  * Static kernelcache: iBoot slid kernel MachO vmaddrs, determine slide
 245                  * using hardcoded kernel link address
 246                  */
 247                 slide = (uintptr_t)k_mh - VM_KERNEL_LINK_ADDRESS;
 248
 249                 /* rebase and sign jops */
 250                 static_kernelcache = &__thread_starts_sect_end[0] != &__thread_starts_sect_start[0];
 251                 if (static_kernelcache) {
 252                         rebase_threaded_starts( &__thread_starts_sect_start[0],
 253                             &__thread_starts_sect_end[0],
 254                             (uintptr_t)k_mh, (uintptr_t)k_mh - slide, slide);
 255                 }
 256 #if defined(HAS_APPLE_PAC)
 257                 OSRuntimeSignStructors(&_mh_execute_header);
 258 #endif /* defined(HAS_APPLE_PAC) */
 259         }
 260
 261
 262         /*
 263          * Initialize slide global here to avoid duplicating this logic in
 264          * arm_vm_init()
 265          */
 266         vm_kernel_slide = slide;
 267 }
 268
 269 void
 270 arm_auxkc_init(void *mh, void *base)
 271 {
 272         /*
 273          * The kernel collection linker guarantees that the lowest vmaddr in an
 274          * AuxKC collection is 0 (but note that the mach header is higher up since
 275          * RW segments precede RO segments in the AuxKC).
 276          */
 277         uintptr_t slide = (uintptr_t)base;
 278         kernel_mach_header_t *akc_mh = (kernel_mach_header_t*)mh;
 279
 280         assert(akc_mh->filetype == MH_FILESET);
 281         PE_set_kc_header_and_base(KCKindAuxiliary, akc_mh, base, slide);
 282
 283         /* rebase and sign jops */
 284         const void *collection_base_pointers[KCNumKinds];
 285         memcpy(collection_base_pointers, PE_get_kc_base_pointers(), sizeof(collection_base_pointers));
 286         kernel_collection_slide((struct mach_header_64 *)akc_mh, collection_base_pointers);
 287
 288         kernel_collection_adjust_mh_addrs((struct mach_header_64 *)akc_mh, slide, false,
 289             (uintptr_t *)&segLOWESTAuxKC, (uintptr_t *)&segHIGHESTAuxKC, (uintptr_t *)&segLOWESTROAuxKC,
 290             (uintptr_t *)&segHIGHESTROAuxKC, (uintptr_t *)&segLOWESTRXAuxKC, (uintptr_t *)&segHIGHESTRXAuxKC,
 291             (uintptr_t *)&segHIGHESTNLEAuxKC);
 292 #if defined(HAS_APPLE_PAC)
 293         OSRuntimeSignStructorsInFileset(akc_mh);
 294 #endif /* defined(HAS_APPLE_PAC) */
 295 }
 296
 297 /*
 298  *              Routine:                arm_init
 299  *              Function:               Runs on the boot CPU, once, on entry from iBoot.
 300  */
 301
 302 __startup_func
 303 void
 304 arm_init(
 305         boot_args       *args)
 306 {
 307         unsigned int    maxmem;
 308         uint32_t        memsize;
 309         uint64_t        xmaxmem;
 310         thread_t        thread;
 311
 312         arm_slide_rebase_and_sign_image();
 313
 314         /* If kernel integrity is supported, use a constant copy of the boot args. */
 315         const_boot_args = *args;
 316         BootArgs = args = &const_boot_args;
 317
 318         cpu_data_init(&BootCpuData);
 319 #if defined(HAS_APPLE_PAC)
 320         /* bootstrap cpu process dependent key for kernel has been loaded by start.s */
 321         BootCpuData.rop_key = ml_default_rop_pid();
 322         BootCpuData.jop_key = ml_default_jop_pid();
 323 #endif /* defined(HAS_APPLE_PAC) */
 324
 325         PE_init_platform(FALSE, args); /* Get platform expert set up */
 326
 327 #if __arm64__
 328         wfe_timeout_configure();
 329
 330         configure_misc_apple_boot_args();
 331         configure_misc_apple_regs();
 332
 333
 334         {
 335                 /*
 336                  * Select the advertised kernel page size.
 337                  */
 338                 if (args->memSize > 1ULL * 1024 * 1024 * 1024) {
 339                         /*
 340                          * arm64 device with > 1GB of RAM:
 341                          * kernel uses 16KB pages.
 342                          */
 343                         PAGE_SHIFT_CONST = PAGE_MAX_SHIFT;
 344                 } else {
 345                         /*
 346                          * arm64 device with <= 1GB of RAM:
 347                          * kernel uses hardware page size
 348                          * (4KB for H6/H7, 16KB for H8+).
 349                          */
 350                         PAGE_SHIFT_CONST = ARM_PGSHIFT;
 351                 }
 352
 353                 /* 32-bit apps always see 16KB page size */
 354                 page_shift_user32 = PAGE_MAX_SHIFT;
 355 #ifdef  APPLETYPHOON
 356                 if (PE_parse_boot_argn("cpus_defeatures", &cpus_defeatures, sizeof(cpus_defeatures))) {
 357                         if ((cpus_defeatures & 0xF) != 0) {
 358                                 cpu_defeatures_set(cpus_defeatures & 0xF);
 359                         }
 360                 }
 361 #endif
 362         }
 363 #endif
 364
 365         ml_parse_cpu_topology();
 366
 367         master_cpu = ml_get_boot_cpu_number();
 368         assert(master_cpu >= 0 && master_cpu <= ml_get_max_cpu_number());
 369
 370         BootCpuData.cpu_number = (unsigned short)master_cpu;
 371 #if     __arm__
 372         BootCpuData.cpu_exc_vectors = (vm_offset_t)&ExceptionVectorsTable;
 373 #endif
 374         BootCpuData.intstack_top = (vm_offset_t) &intstack_top;
 375         BootCpuData.istackptr = BootCpuData.intstack_top;
 376 #if __arm64__
 377         BootCpuData.excepstack_top = (vm_offset_t) &excepstack_top;
 378         BootCpuData.excepstackptr = BootCpuData.excepstack_top;
 379 #else
 380         BootCpuData.fiqstack_top = (vm_offset_t) &fiqstack_top;
 381         BootCpuData.fiqstackptr = BootCpuData.fiqstack_top;
 382 #endif
 383         BootCpuData.cpu_console_buf = (void *)NULL;
 384         CpuDataEntries[master_cpu].cpu_data_vaddr = &BootCpuData;
 385         CpuDataEntries[master_cpu].cpu_data_paddr = (void *)((uintptr_t)(args->physBase)
 386             + ((uintptr_t)&BootCpuData
 387             - (uintptr_t)(args->virtBase)));
 388
 389         thread = thread_bootstrap();
 390         thread->machine.CpuDatap = &BootCpuData;
 391         thread->machine.pcpu_data_base = (vm_offset_t)0;
 392         machine_set_current_thread(thread);
 393
 394         /*
 395          * Preemption is enabled for this thread so that it can lock mutexes without
 396          * tripping the preemption check. In reality scheduling is not enabled until
 397          * this thread completes, and there are no other threads to switch to, so
 398          * preemption level is not really meaningful for the bootstrap thread.
 399          */
 400         thread->machine.preemption_count = 0;
 401 #if     __arm__ && __ARM_USER_PROTECT__
 402         {
 403                 unsigned int ttbr0_val, ttbr1_val;
 404                 __asm__ volatile ("mrc p15,0,%0,c2,c0,0\n" : "=r"(ttbr0_val));
 405                 __asm__ volatile ("mrc p15,0,%0,c2,c0,1\n" : "=r"(ttbr1_val));
 406                 thread->machine.uptw_ttb = ttbr0_val;
 407                 thread->machine.kptw_ttb = ttbr1_val;
 408         }
 409 #endif
 410         processor_t boot_processor = PERCPU_GET_MASTER(processor);
 411         boot_processor->kernel_timer = &thread->system_timer;
 412         boot_processor->thread_timer = &thread->system_timer;
 413
 414         cpu_bootstrap();
 415
 416         rtclock_early_init();
 417
 418         kernel_debug_string_early("kernel_startup_bootstrap");
 419         kernel_startup_bootstrap();
 420
 421         /*
 422          * Initialize the timer callout world
 423          */
 424         timer_call_init();
 425
 426         cpu_init();
 427
 428         processor_bootstrap();
 429
 430         if (PE_parse_boot_argn("maxmem", &maxmem, sizeof(maxmem))) {
 431                 xmaxmem = (uint64_t) maxmem * (1024 * 1024);
 432         } else if (PE_get_default("hw.memsize", &memsize, sizeof(memsize))) {
 433                 xmaxmem = (uint64_t) memsize;
 434         } else {
 435                 xmaxmem = 0;
 436         }
 437
 438 #if INTERRUPT_MASKED_DEBUG
 439         int wdt_boot_arg = 0;
 440         /* Disable if WDT is disabled or no_interrupt_mask_debug in boot-args */
 441         if (PE_parse_boot_argn("no_interrupt_masked_debug", &interrupt_masked_debug,
 442             sizeof(interrupt_masked_debug)) || (PE_parse_boot_argn("wdt", &wdt_boot_arg,
 443             sizeof(wdt_boot_arg)) && (wdt_boot_arg == -1)) || kern_feature_override(KF_INTERRUPT_MASKED_DEBUG_OVRD)) {
 444                 interrupt_masked_debug = 0;
 445         }
 446
 447         PE_parse_boot_argn("interrupt_masked_debug_timeout", &interrupt_masked_timeout, sizeof(interrupt_masked_timeout));
 448
 449 #endif /* INTERRUPT_MASKED_DEBUG */
 450
 451         nanoseconds_to_absolutetime(XCALL_ACK_TIMEOUT_NS, &xcall_ack_timeout_abstime);
 452
 453
 454 #if HAS_BP_RET
 455         PE_parse_boot_argn("bpret", &bp_ret, sizeof(bp_ret));
 456         set_bp_ret(); // Apply branch predictor retention settings to boot CPU
 457 #endif
 458
 459         PE_parse_boot_argn("immediate_NMI", &force_immediate_debug_halt, sizeof(force_immediate_debug_halt));
 460
 461 #if __ARM_PAN_AVAILABLE__
 462         __builtin_arm_wsr("pan", 1);
 463 #endif  /* __ARM_PAN_AVAILABLE__ */
 464
 465         arm_vm_init(xmaxmem, args);
 466
 467         if (debug_boot_arg) {
 468                 patch_low_glo();
 469         }
 470
 471 #if __arm64__ && WITH_CLASSIC_S2R
 472         sleep_token_buffer_init();
 473 #endif
 474
 475         PE_consistent_debug_inherit();
 476
 477         /*
 478          * rdar://54622819 Insufficient HSP purge window can cause incorrect translation when ASID and TTBR base address is changed at same time)
 479          * (original info on HSP purge window issues can be found in rdar://55577508)
 480          * We need a flag to check for this, so calculate and set it here. We'll use it in machine_switch_amx_context().
 481          */
 482 #if __arm64__
 483         need_wa_rdar_55577508 = cpuid_get_cpufamily() == CPUFAMILY_ARM_LIGHTNING_THUNDER;
 484 #ifndef RC_HIDE_XNU_FIRESTORM
 485         need_wa_rdar_55577508 |= (cpuid_get_cpufamily() == CPUFAMILY_ARM_FIRESTORM_ICESTORM && get_arm_cpu_version() == CPU_VERSION_A0);
 486 #endif
 487 #endif
 488
 489         /* setup debugging output if one has been chosen */
 490         kernel_startup_initialize_upto(STARTUP_SUB_KPRINTF);
 491         kprintf("kprintf initialized\n");
 492
 493         serialmode = 0;
 494         if (PE_parse_boot_argn("serial", &serialmode, sizeof(serialmode))) {
 495                 /* Do we want a serial keyboard and/or console? */
 496                 kprintf("Serial mode specified: %08X\n", serialmode);
 497                 int force_sync = serialmode & SERIALMODE_SYNCDRAIN;
 498                 if (force_sync || PE_parse_boot_argn("drain_uart_sync", &force_sync, sizeof(force_sync))) {
 499                         if (force_sync) {
 500                                 serialmode |= SERIALMODE_SYNCDRAIN;
 501                                 kprintf(
 502                                         "WARNING: Forcing uart driver to output synchronously."
 503                                         "printf()s/IOLogs will impact kernel performance.\n"
 504                                         "You are advised to avoid using 'drain_uart_sync' boot-arg.\n");
 505                         }
 506                 }
 507         }
 508         if (kern_feature_override(KF_SERIAL_OVRD)) {
 509                 serialmode = 0;
 510         }
 511
 512         if (serialmode & SERIALMODE_OUTPUT) {                 /* Start serial if requested */
 513                 serial_console_enabled = true;
 514                 (void)switch_to_serial_console(); /* Switch into serial mode */
 515                 disableConsoleOutput = FALSE;     /* Allow printfs to happen */
 516         }
 517         PE_create_console();
 518
 519         /* setup console output */
 520         PE_init_printf(FALSE);
 521
 522 #if __arm64__
 523 #if DEBUG
 524         dump_kva_space();
 525 #endif
 526 #endif
 527
 528         cpu_machine_idle_init(TRUE);
 529
 530 #if     (__ARM_ARCH__ == 7)
 531         if (arm_diag & 0x8000) {
 532                 set_mmu_control((get_mmu_control()) ^ SCTLR_PREDIC);
 533         }
 534 #endif
 535
 536         PE_init_platform(TRUE, &BootCpuData);
 537
 538 #if __arm64__
 539         ml_map_cpu_pio();
 540 #endif
 541
 542         cpu_timebase_init(TRUE);
 543         PE_init_cpu();
 544         fiq_context_init(TRUE);
 545
 546
 547 #if HIBERNATION
 548         pal_hib_init();
 549 #endif /* HIBERNATION */
 550
 551         /*
 552          * gPhysBase/Size only represent kernel-managed memory. These globals represent
 553          * the actual DRAM base address and size as reported by iBoot through the
 554          * device tree.
 555          */
 556         DTEntry chosen;
 557         unsigned int dt_entry_size;
 558         unsigned long const *dram_base;
 559         unsigned long const *dram_size;
 560         if (SecureDTLookupEntry(NULL, "/chosen", &chosen) != kSuccess) {
 561                 panic("%s: Unable to find 'chosen' DT node", __FUNCTION__);
 562         }
 563
 564         if (SecureDTGetProperty(chosen, "dram-base", (void const **)&dram_base, &dt_entry_size) != kSuccess) {
 565                 panic("%s: Unable to find 'dram-base' entry in the 'chosen' DT node", __FUNCTION__);
 566         }
 567
 568         if (SecureDTGetProperty(chosen, "dram-size", (void const **)&dram_size, &dt_entry_size) != kSuccess) {
 569                 panic("%s: Unable to find 'dram-size' entry in the 'chosen' DT node", __FUNCTION__);
 570         }
 571
 572         gDramBase = *dram_base;
 573         gDramSize = *dram_size;
 574
 575         /*
 576          * Initialize the stack protector for all future calls
 577          * to C code. Since kernel_bootstrap() eventually
 578          * switches stack context without returning through this
 579          * function, we do not risk failing the check even though
 580          * we mutate the guard word during execution.
 581          */
 582         __stack_chk_guard = (unsigned long)early_random();
 583         /* Zero a byte of the protector to guard
 584          * against string vulnerabilities
 585          */
 586         __stack_chk_guard &= ~(0xFFULL << 8);
 587         machine_startup(args);
 588 }
 589
 590 /*
 591  * Routine:        arm_init_cpu
 592  * Function:
 593  *    Runs on S2R resume (all CPUs) and SMP boot (non-boot CPUs only).
 594  */
 595
 596 void
 597 arm_init_cpu(
 598         cpu_data_t      *cpu_data_ptr)
 599 {
 600 #if __ARM_PAN_AVAILABLE__
 601         __builtin_arm_wsr("pan", 1);
 602 #endif
 603
 604 #ifdef __arm64__
 605         configure_misc_apple_regs();
 606 #endif
 607
 608         cpu_data_ptr->cpu_flags &= ~SleepState;
 609 #if     defined(ARMA7)
 610         cpu_data_ptr->cpu_CLW_active = 1;
 611 #endif
 612
 613         machine_set_current_thread(cpu_data_ptr->cpu_active_thread);
 614
 615 #if HIBERNATION
 616         if ((cpu_data_ptr == &BootCpuData) && (gIOHibernateState == kIOHibernateStateWakingFromHibernate)) {
 617                 // the "normal" S2R code captures wake_abstime too early, so on a hibernation resume we fix it up here
 618                 extern uint64_t wake_abstime;
 619                 wake_abstime = gIOHibernateCurrentHeader->lastHibAbsTime;
 620
 621                 // since the hw clock stops ticking across hibernation, we need to apply an offset;
 622                 // iBoot computes this offset for us and passes it via the hibernation header
 623                 extern uint64_t hwclock_conttime_offset;
 624                 hwclock_conttime_offset = gIOHibernateCurrentHeader->hwClockOffset;
 625
 626                 // during hibernation, we captured the idle thread's state from inside the PPL context, so we have to
 627                 // fix up its preemption count
 628                 unsigned int expected_preemption_count = (gEnforceQuiesceSafety ? 2 : 1);
 629                 if (cpu_data_ptr->cpu_active_thread->machine.preemption_count != expected_preemption_count) {
 630                         panic("unexpected preemption count %u on boot cpu thread (should be %u)\n",
 631                             cpu_data_ptr->cpu_active_thread->machine.preemption_count,
 632                             expected_preemption_count);
 633                 }
 634                 cpu_data_ptr->cpu_active_thread->machine.preemption_count--;
 635         }
 636 #endif /* HIBERNATION */
 637
 638 #if __arm64__
 639         wfe_timeout_init();
 640         pmap_clear_user_ttb();
 641         flush_mmu_tlb();
 642 #endif
 643
 644         cpu_machine_idle_init(FALSE);
 645
 646         cpu_init();
 647
 648 #if     (__ARM_ARCH__ == 7)
 649         if (arm_diag & 0x8000) {
 650                 set_mmu_control((get_mmu_control()) ^ SCTLR_PREDIC);
 651         }
 652 #endif
 653 #ifdef  APPLETYPHOON
 654         if ((cpus_defeatures & (0xF << 4 * cpu_data_ptr->cpu_number)) != 0) {
 655                 cpu_defeatures_set((cpus_defeatures >> 4 * cpu_data_ptr->cpu_number) & 0xF);
 656         }
 657 #endif
 658         /* Initialize the timebase before serial_init, as some serial
 659          * drivers use mach_absolute_time() to implement rate control
 660          */
 661         cpu_timebase_init(FALSE);
 662
 663         if (cpu_data_ptr == &BootCpuData) {
 664 #if __arm64__ && __ARM_GLOBAL_SLEEP_BIT__
 665                 /*
 666                  * Prevent CPUs from going into deep sleep until all
 667                  * CPUs are ready to do so.
 668                  */
 669                 arm64_stall_sleep = TRUE;
 670 #endif
 671                 serial_init();
 672                 PE_init_platform(TRUE, NULL);
 673                 commpage_update_timebase();
 674         }
 675         PE_init_cpu();
 676
 677         fiq_context_init(TRUE);
 678         cpu_data_ptr->rtcPop = EndOfAllTime;
 679         timer_resync_deadlines();
 680
 681 #if DEVELOPMENT || DEBUG
 682         PE_arm_debug_enable_trace();
 683 #endif
 684
 685
 686         kprintf("arm_cpu_init(): cpu %d online\n", cpu_data_ptr->cpu_number);
 687
 688         if (cpu_data_ptr == &BootCpuData) {
 689                 if (kdebug_enable == 0) {
 690                         __kdebug_only uint64_t elapsed = kdebug_wake();
 691                         KDBG(IOKDBG_CODE(DBG_HIBERNATE, 15), mach_absolute_time() - elapsed);
 692                 }
 693
 694 #if CONFIG_TELEMETRY
 695                 bootprofile_wake_from_sleep();
 696 #endif /* CONFIG_TELEMETRY */
 697         }
 698 #if MONOTONIC && defined(__arm64__)
 699         mt_wake_per_core();
 700 #endif /* MONOTONIC && defined(__arm64__) */
 701
 702 #if defined(KERNEL_INTEGRITY_CTRR)
 703         if (ctrr_cluster_locked[cpu_data_ptr->cpu_cluster_id] != CTRR_LOCKED) {
 704                 lck_spin_lock(&ctrr_cpu_start_lck);
 705                 ctrr_cluster_locked[cpu_data_ptr->cpu_cluster_id] = CTRR_LOCKED;
 706                 thread_wakeup(&ctrr_cluster_locked[cpu_data_ptr->cpu_cluster_id]);
 707                 lck_spin_unlock(&ctrr_cpu_start_lck);
 708         }
 709 #endif
 710
 711         slave_main(NULL);
 712 }
 713
 714 /*
 715  * Routine:             arm_init_idle_cpu
 716  * Function:    Resume from non-retention WFI.  Called from the reset vector.
 717  */
 718 void __attribute__((noreturn))
 719 arm_init_idle_cpu(
 720         cpu_data_t      *cpu_data_ptr)
 721 {
 722 #if __ARM_PAN_AVAILABLE__
 723         __builtin_arm_wsr("pan", 1);
 724 #endif
 725 #if     defined(ARMA7)
 726         cpu_data_ptr->cpu_CLW_active = 1;
 727 #endif
 728
 729         machine_set_current_thread(cpu_data_ptr->cpu_active_thread);
 730
 731 #if __arm64__
 732         wfe_timeout_init();
 733         pmap_clear_user_ttb();
 734         flush_mmu_tlb();
 735         /* Enable asynchronous exceptions */
 736         __builtin_arm_wsr("DAIFClr", DAIFSC_ASYNCF);
 737 #endif
 738
 739 #if     (__ARM_ARCH__ == 7)
 740         if (arm_diag & 0x8000) {
 741                 set_mmu_control((get_mmu_control()) ^ SCTLR_PREDIC);
 742         }
 743 #endif
 744 #ifdef  APPLETYPHOON
 745         if ((cpus_defeatures & (0xF << 4 * cpu_data_ptr->cpu_number)) != 0) {
 746                 cpu_defeatures_set((cpus_defeatures >> 4 * cpu_data_ptr->cpu_number) & 0xF);
 747         }
 748 #endif
 749
 750         fiq_context_init(FALSE);
 751
 752         cpu_idle_exit(TRUE);
 753 }