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1 /*
2 * Copyright (c) 2000-2004 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23 /*
24 * @OSF_COPYRIGHT@
25 */
26
27 #define __APPLE_API_PRIVATE
28
29 #include <mach_kdb.h>
30 #include <mach_kdp.h>
31 #include <mach_kgdb.h>
32 #include <ppc/asm.h>
33 #include <ppc/proc_reg.h>
34 #include <ppc/spec_reg.h>
35 #include <machine/cpu_capabilities.h>
36 #include <mach/ppc/vm_param.h>
37 #include <assym.s>
38
39
40 ; Definitions of the processor type table format, which drives this code.
41 ; The table ("processor_types") is assembled in at the end of this file.
42
43 #define ptFilter 0
44 #define ptVersion 4
45 #define ptRevision 6
46 #define ptFeatures 8
47 #define ptCPUCap 12
48 #define ptPwrModes 16
49 #define ptPatch 20
50 #define ptInitRout 24
51 #define ptRptdProc 28
52 #define ptLineSize 32
53 #define ptl1iSize 36
54 #define ptl1dSize 40
55 #define ptPTEG 44
56 #define ptMaxVAddr 48
57 #define ptMaxPAddr 52
58 #define ptSize 56
59
60
61 ; We use cr2 for flags:
62
63 #define bootCPU 10
64 #define firstInit 9
65 #define firstBoot 8
66
67 /*
68 * Interrupt and bootup stack for initial processor
69 */
70
71 .file "start.s"
72
73 /*
74 * All CPUs start here.
75 *
76 * This code is called from SecondaryLoader
77 *
78 * Various arguments are passed via a table:
79 * R3 = pointer to other startup parameters
80 */
81 .text
82
83 ENTRY(resetPOR,TAG_NO_FRAME_USED)
84
85 li r12,0 ; Get a 0
86 stw r12,0xF0(0) ; Make sure the special flag is clear
87 mtmsrd r12 ; Make sure we are in 32-bit mode
88 isync ; Really make sure
89 lwz r3,0xF4(0) ; Get the boot_args pointer
90 b startJoin ; Join up...
91
92
93 ENTRY(_start_cpu,TAG_NO_FRAME_USED)
94 crclr bootCPU ; Set non-boot processor
95 crclr firstInit ; Set not first time init
96 lwz r30,ppe_paddr(r3) ; Set current per_proc
97 lwz r28,ppe_paddr+4(r3) ; Set current per_proc
98 rlwinm r30,r30,0,1,0 ; Copy low 32 bits to top 32
99 rlwimi r30,r28,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
100 subi r29,r3,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
101 mr r3,r30 ; Set current per_proc
102
103 ;
104 ; Note that we are just trying to get close. The real TB sync will take
105 ; place later. The value we are loading is set in two places. For the
106 ; main processor, it will be the TB at the last interrupt before we went
107 ; to sleep. For the others, it will be the time just before the main
108 ; processor woke us up.
109 ;
110
111 lwz r15,ruptStamp(r3) ; Get the timebase from the other processor
112 li r17,0 ; Clear this out
113 lwz r16,ruptStamp+4(r3) ; Get the timebase from the other processor
114 mtspr tbl,r17 ; Clear bottom so we do not tick
115 mtspr tbu,r15 ; Set top
116 mtspr tbl,r16 ; Then bottom again
117 b allstart
118
119 ENTRY(_start,TAG_NO_FRAME_USED)
120
121 startJoin:
122 mflr r2 ; Save the return address
123 lis r28,hi16(EXT(PerProcTable)) ; Set PerProcTable
124 lis r30,hi16(EXT(BootProcInfo)) ; Set current per_proc
125 ori r28,r28,lo16(EXT(PerProcTable)) ; Set PerProcTable
126 ori r30,r30,lo16(EXT(BootProcInfo)) ; Set current per_proc
127 stw r30,ppe_paddr+4(r28) ; Set per_proc_entry
128 stw r30,ppe_vaddr(r28) ; Set per_proc_entry
129 subi r29,r28,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
130 crset bootCPU ; Set boot processor
131
132 lwz r17,pfAvailable(r30) ; Get the available bits
133 rlwinm. r0,r17,0,pfValidb,pfValidb ; Have we initialized the feature flags yet?
134 crmove firstInit,cr0_eq ; Set if we are doing first time init
135 bne allstart ; Yeah, we must be waking up from sleep...
136
137 ;
138 ; Here is where we do any one time general low-level initialization
139
140 lis r20,HIGH_ADDR(fwdisplock) ; Get address of the firmware display lock
141 li r19,0 ; Zorch a register
142 ori r20,r20,LOW_ADDR(fwdisplock) ; Get address of the firmware display lock
143 stw r19,0(r20) ; Make sure the lock is free
144
145 allstart:
146 mr r31,r3 ; Save away arguments
147
148 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
149
150 mtsprg 0,r30 ; Set per_proc paddr
151 mtsprg 1,r29 ; Set spr1
152
153 li r9,0 ; Clear out a register
154 mtsprg 2,r9
155 mtsprg 3,r9
156
157 li r7,MSR_VM_OFF ; Get real mode MSR
158 mtmsr r7 ; Set the real mode SRR
159 isync
160
161 lis r26,hi16(processor_types) ; Point to processor table
162 ori r26,r26,lo16(processor_types) ; Other half
163 mfpvr r10 ; Get the PVR
164
165 nextPVR: lwz r28,ptFilter(r26) ; Get the filter
166 lwz r27,ptVersion(r26) ; Get the version and revision codes
167 and r28,r10,r28 ; Throw away dont care bits
168 cmplw r27,r28 ; Is this the right set?
169 beq donePVR ; We have the right one...
170 addi r26,r26,ptSize ; Point to the next type
171 b nextPVR ; Check it out...
172
173 donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine
174 mtlr r20 ; Setup to call the init
175
176 bf firstBoot,notFirst ; Not first boot, go...
177
178 ;
179 ; The following code just does a general initialization of the features just
180 ; after the initial first-time boot. This is not done after waking up or on
181 ; any "secondary" processor. Just after the boot-processor init, we copy the
182 ; features to any possible per_proc.
183 ;
184 ; We are just setting defaults. The specific initialization code will modify these
185 ; if necessary.
186 ;
187 lis r18,hi16(EXT(_cpu_capabilities)) ; Get the address of _cpu_capabilities
188 ori r18,r18,lo16(EXT(_cpu_capabilities))
189 lwz r17,ptCPUCap(r26) ; Get the default cpu capabilities
190 stw r17, 0(r18) ; Save the default value in _cpu_capabilities
191
192 lwz r17,ptFeatures(r26) ; Pick up the features
193
194 lwz r18,ptRptdProc(r26) ; Get the reported processor
195 sth r18,pfrptdProc(r30) ; Set the reported processor
196
197 lwz r13,ptPwrModes(r26) ; Get the supported power modes
198 stw r13,pfPowerModes(r30) ; Set the supported power modes
199
200 lwz r13,ptLineSize(r26) ; Get the cache line size
201 sth r13,pflineSize(r30) ; Save it
202 lwz r13,ptl1iSize(r26) ; Get icache size
203 stw r13,pfl1iSize(r30) ; Save it
204 lwz r13,ptl1dSize(r26) ; Get dcache size
205 stw r13,pfl1dSize(r30) ; Save it
206 lwz r13,ptPTEG(r26) ; Get PTEG size address
207 stw r13,pfPTEG(r30) ; Save it
208 lwz r13,ptMaxVAddr(r26) ; Get max virtual address
209 stw r13,pfMaxVAddr(r30) ; Save it
210 lwz r13,ptMaxPAddr(r26) ; Get max physical address
211 stw r13,pfMaxPAddr(r30) ; Save it
212
213
214 ; Go through the patch table, changing performance sensitive kernel routines based on the
215 ; processor type or other things.
216
217 lis r11,hi16(EXT(patch_table))
218 ori r11,r11,lo16(EXT(patch_table))
219 lwz r19,ptPatch(r26) ; Get ptPatch field
220 patch_loop:
221 lwz r16,patchType(r11) ; Load the patch type
222 lwz r15,patchValue(r11) ; Load the patch value
223 cmplwi cr1,r16,PATCH_FEATURE ; Is it a patch feature entry
224 cmplwi cr7,r16,PATCH_END_OF_TABLE ; end of table?
225 and. r14,r15,r19 ; Is it set in the patch feature
226 crandc cr0_eq,cr1_eq,cr0_eq ; Do we have a match
227 beq cr7,doOurInit ; end of table, Go do processor specific initialization
228 beq patch_apply ; proc feature matches, so patch memory
229 cmplwi cr1,r16,PATCH_PROCESSOR ; Is it a patch processor entry
230 cmplw cr0,r15,r18 ; Check matching processor
231 crand cr0_eq,cr1_eq,cr0_eq ; Do we have a match
232 bne patch_skip ; No, skip patch memory
233 patch_apply:
234 lwz r13,patchAddr(r11) ; Load the address to patch
235 lwz r14,patchData(r11) ; Load the patch data
236 stw r14,0(r13) ; Patch the location
237 dcbf 0,r13 ; Flush the old one
238 sync ; Make sure we see it all
239 icbi 0,r13 ; Flush the i-cache
240 isync ; Hang out
241 sync ; Hang out some more...
242 patch_skip:
243 addi r11,r11,peSize ; Point to the next patch entry
244 b patch_loop ; handle next
245
246
247 ; Additional processors join here after skipping above code.
248
249 notFirst: lwz r17,pfAvailable(r30) ; Get our features
250
251 doOurInit: mr. r20,r20 ; See if initialization routine
252 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
253 bnelrl ; Do the initialization
254
255 ori r17,r17,lo16(pfValid) ; Set the valid bit
256 stw r17,pfAvailable(r30) ; Set the available features
257
258 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
259 mtsprg 2,r17 ; Remember the feature flags
260
261 bne++ start64 ; Skip following if 64-bit...
262
263 mfspr r6,hid0 ; Get the HID0
264 rlwinm r6,r6,0,sleep+1,doze-1 ; Remove any vestiges of sleep
265 mtspr hid0,r6 ; Set the insominac HID0
266 isync
267
268 ; Clear the BAT registers
269
270 li r9,0 ; Clear out a register
271 sync
272 isync
273 mtdbatu 0,r9 ; Invalidate maps
274 mtdbatl 0,r9 ; Invalidate maps
275 mtdbatu 1,r9 ; Invalidate maps
276 mtdbatl 1,r9 ; Invalidate maps
277 mtdbatu 2,r9 ; Invalidate maps
278 mtdbatl 2,r9 ; Invalidate maps
279 mtdbatu 3,r9 ; Invalidate maps
280 mtdbatl 3,r9 ; Invalidate maps
281 sync
282 isync
283 mtibatu 0,r9 ; Invalidate maps
284 mtibatl 0,r9 ; Invalidate maps
285 mtibatu 1,r9 ; Invalidate maps
286 mtibatl 1,r9 ; Invalidate maps
287 mtibatu 2,r9 ; Invalidate maps
288 mtibatl 2,r9 ; Invalidate maps
289 mtibatu 3,r9 ; Invalidate maps
290 mtibatl 3,r9 ; Invalidate maps
291 sync
292 isync
293 b startcommon ; Go join up the common start routine
294
295 start64: lis r5,hi16(startcommon) ; Get top of address of continue point
296 mfspr r6,hid0 ; Get the HID0
297 ori r5,r5,lo16(startcommon) ; Get low of address of continue point
298 lis r9,hi16(MASK(MSR_HV)|MASK(MSR_SF)) ; ?
299 lis r20,hi16(dozem|napm|sleepm) ; Get mask of power saving features
300 li r7,MSR_VM_OFF ; Get real mode MSR
301 sldi r9,r9,32 ; Slide into position
302 sldi r20,r20,32 ; Slide power stuff into position
303 or r9,r9,r7 ; Form initial MSR
304 andc r6,r6,r20 ; Remove any vestiges of sleep
305 isync
306 mtspr hid0,r6 ; Set the insominac HID0
307 mfspr r6,hid0 ; Get it
308 mfspr r6,hid0 ; Get it
309 mfspr r6,hid0 ; Get it
310 mfspr r6,hid0 ; Get it
311 mfspr r6,hid0 ; Get it
312 mfspr r6,hid0 ; Get it
313 isync
314 mtsrr0 r5 ; Set the continue point
315 mtsrr1 r9 ; Set our normal disabled MSR
316 rfid ; Tally ho...
317
318 .align 5
319
320 startcommon:
321 rlwinm. r0,r17,0,pfFloatb,pfFloatb ; See if there is floating point
322 beq- noFloat ; Nope, this is a really stupid machine...
323
324 li r0,MSR_VM_OFF|MASK(MSR_FP) ; Enable for floating point
325 mtmsr r0 /* Set the standard MSR values */
326 isync
327
328 lis r5,HIGH_ADDR(EXT(FloatInit)) /* Get top of floating point init value */
329 ori r5,r5,LOW_ADDR(EXT(FloatInit)) /* Slam bottom */
330 lfd f0,0(r5) /* Initialize FP0 */
331 fmr f1,f0 /* Ours in not */
332 fmr f2,f0 /* to wonder why, */
333 fmr f3,f0 /* ours is but to */
334 fmr f4,f0 /* do or die! */
335 fmr f5,f0
336 fmr f6,f0
337 fmr f7,f0
338 fmr f8,f0
339 fmr f9,f0
340 fmr f10,f0
341 fmr f11,f0
342 fmr f12,f0
343 fmr f13,f0
344 fmr f14,f0
345 fmr f15,f0
346 fmr f16,f0
347 fmr f17,f0
348 fmr f18,f0
349 fmr f19,f0
350 fmr f20,f0
351 fmr f21,f0
352 fmr f22,f0
353 fmr f23,f0
354 fmr f24,f0
355 fmr f25,f0
356 fmr f26,f0
357 fmr f27,f0
358 fmr f28,f0
359 fmr f29,f0
360 fmr f30,f0
361 fmr f31,f0
362
363 li r0, MSR_VM_OFF ; Turn off floating point
364 mtmsr r0
365 isync
366
367 noFloat: rlwinm. r0,r17,0,pfAltivecb,pfAltivecb ; See if there is Altivec
368 beq- noVector ; Nope...
369
370 li r0,0 ; Clear out a register
371
372 lis r7,hi16(MSR_VEC_ON) ; Get real mode MSR + Altivec
373 ori r7,r7,lo16(MSR_VM_OFF) ; Get real mode MSR + Altivec
374 mtmsr r7 ; Set the real mode SRR */
375 isync ; Make sure it has happened
376
377 lis r5,hi16(EXT(QNaNbarbarian)) ; Altivec initializer
378 ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Altivec initializer
379
380 mtspr vrsave,r0 ; Set that no VRs are used yet */
381
382 vspltish v1,1 ; Turn on the non-Java bit and saturate
383 vspltisw v0,1 ; Turn on the saturate bit
384 vxor v1,v1,v0 ; Turn off saturate and leave non-Java set
385 lvx v0,br0,r5 ; Initialize VR0
386 mtvscr v1 ; Clear the vector status register
387 vor v2,v0,v0 ; Copy into the next register
388 vor v1,v0,v0 ; Copy into the next register
389 vor v3,v0,v0 ; Copy into the next register
390 vor v4,v0,v0 ; Copy into the next register
391 vor v5,v0,v0 ; Copy into the next register
392 vor v6,v0,v0 ; Copy into the next register
393 vor v7,v0,v0 ; Copy into the next register
394 vor v8,v0,v0 ; Copy into the next register
395 vor v9,v0,v0 ; Copy into the next register
396 vor v10,v0,v0 ; Copy into the next register
397 vor v11,v0,v0 ; Copy into the next register
398 vor v12,v0,v0 ; Copy into the next register
399 vor v13,v0,v0 ; Copy into the next register
400 vor v14,v0,v0 ; Copy into the next register
401 vor v15,v0,v0 ; Copy into the next register
402 vor v16,v0,v0 ; Copy into the next register
403 vor v17,v0,v0 ; Copy into the next register
404 vor v18,v0,v0 ; Copy into the next register
405 vor v19,v0,v0 ; Copy into the next register
406 vor v20,v0,v0 ; Copy into the next register
407 vor v21,v0,v0 ; Copy into the next register
408 vor v22,v0,v0 ; Copy into the next register
409 vor v23,v0,v0 ; Copy into the next register
410 vor v24,v0,v0 ; Copy into the next register
411 vor v25,v0,v0 ; Copy into the next register
412 vor v26,v0,v0 ; Copy into the next register
413 vor v27,v0,v0 ; Copy into the next register
414 vor v28,v0,v0 ; Copy into the next register
415 vor v29,v0,v0 ; Copy into the next register
416 vor v30,v0,v0 ; Copy into the next register
417 vor v31,v0,v0 ; Copy into the next register
418
419 li r0, MSR_VM_OFF ; Turn off vectors
420 mtmsr r0
421 isync
422
423 noVector:
424 bl EXT(cacheInit) ; Initializes all caches (including the TLB)
425
426 bt bootCPU,run32
427
428 mfsprg r30,0 ; Phys per proc
429 lwz r29,PP_HIBERNATE(r30)
430 andi. r29, r29, 1
431 beq noHashTableInit ; Skip following if not waking from from hibernate
432 bl EXT(hw_clear_maps) ; Mark all maps as absent from hash table
433 bl EXT(hw_hash_init) ; Clear hash table
434 bl EXT(save_snapshot_restore) ; Reset save area chains
435 noHashTableInit:
436 bl EXT(hw_setup_trans) ; Set up hardware needed for translation
437 bl EXT(hw_start_trans) ; Start translating
438
439 run32:
440 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
441 beq++ isnot64 ; Skip following if not 64-bit...
442
443 mfmsr r29 ; Get the MSR
444 rldicl r29,r29,0,MSR_SF_BIT+1 ; turn 64-bit mode off
445 mtmsrd r29 ; Set it
446 isync ; Make sure
447
448 isnot64: bf bootCPU,callcpu
449
450 lis r29,HIGH_ADDR(EXT(intstack)) ; move onto interrupt stack
451 ori r29,r29,LOW_ADDR(EXT(intstack))
452 addi r29,r29,INTSTACK_SIZE-FM_SIZE
453
454 li r28,0
455 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
456
457 mr r1,r29
458 mr r3,r31 ; Restore any arguments we may have trashed
459
460 ; Note that we exit from here with translation still off
461
462 bl EXT(ppc_init) ; Jump into boot init code
463 BREAKPOINT_TRAP
464
465 callcpu:
466 mfsprg r31,1 ; Fake activation pointer
467 lwz r31,ACT_PER_PROC(r31) ; Load per_proc
468 lwz r29,PP_INTSTACK_TOP_SS(r31) ; move onto interrupt stack
469
470 li r28,0
471 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
472
473 mr r1,r29 ; move onto new stack
474 mr r3,r31 ; Restore any arguments we may have trashed
475
476 ; Note that we exit from here with translation on
477
478 bl EXT(ppc_init_cpu) ; Jump into cpu init code
479 BREAKPOINT_TRAP ; Should never return
480
481 ;
482 ; Specific processor initialization routines
483 ;
484
485 ; 750
486
487 init750:
488 bf firstBoot, init750nb ; No init for wakeup....
489
490 mfspr r13,l2cr ; Get the L2CR
491 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
492 bne+ i750hl2 ; Yes...
493 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
494
495 i750hl2:
496 lis r14,hi16(256*1024) ; Base L2 size
497 addis r15,r13,0x3000 ; Hah... Figure this one out...
498 rlwinm r15,r15,4,30,31 ; Isolate
499 rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
500 slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
501 beq- init750l2none ; Not a valid setting...
502
503 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
504 stw r13,pfl2cr(r30) ; Shadow the L2CR
505 stw r14,pfl2Size(r30) ; Set the L2 size
506 b init750l2done ; Done with L2
507
508 init750l2none:
509 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
510
511 init750l2done:
512 mfspr r11,hid0 ; Get the current HID0
513 stw r11,pfHID0(r30) ; Save the HID0 value
514 blr ; Return...
515
516 init750nb:
517 lwz r11,pfHID0(r30) ; Get HID0
518 sync
519 mtspr hid0,r11 ; Set the HID
520 isync
521 sync
522 blr
523
524 ; 750CX
525
526 init750CX:
527 bf firstBoot, init750 ; No init for wakeup....
528 mfspr r13,hid1 ; Get HID1
529 li r14,lo16(0xFD5F) ; Get valid
530 rlwinm r13,r13,4,28,31 ; Isolate
531 slw r14,r14,r13 ; Position
532 rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it
533 b init750 ; Join common...
534
535
536 ; 750FX
537
538 init750FX:
539 bf firstBoot, init750FXnb
540 mfspr r11, hid1
541 stw r11, pfHID1(r30) ; Save the HID1 value
542 b init750
543
544 init750FXnb:
545 lwz r13, pfHID0(r30) ; Get HID0
546 lwz r11, pfHID1(r30) ; Get HID1
547
548 rlwinm. r0, r11, 0, hid1ps, hid1ps ; Isolate the hid1ps bit
549 beq init750FXnb2 ; Clear BTIC if hid1ps set
550 rlwinm r13, r13, 0, btic+1, btic-1 ; Clear the BTIC bit
551
552 init750FXnb2:
553 sync
554 mtspr hid0, r13 ; Set the HID
555 isync
556 sync
557
558 rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 ; Select PLL0
559 mtspr hid1, r12 ; Restore PLL config
560 mftb r13 ; Wait 5000 ticks (> 200 us)
561
562 init750FXnbloop:
563 mftb r14
564 sub r14, r14, r13
565 cmpli cr0, r14, 5000
566 ble init750FXnbloop
567 mtspr hid1, r11 ; Select the desired PLL
568 blr
569
570 ; 750FX vers 2.0 or later
571 init750FXV2:
572 bf firstBoot, init750FXV2nb ; Wake from sleep
573
574 mfspr r11, hid2
575 stw r11, pfHID2(r30) ; Save the HID2 value
576 b init750FX ; Continue with 750FX init
577
578 init750FXV2nb:
579 lwz r13, pfHID2(r30) ; Get HID2
580 rlwinm r13, r13, 0, hid2vmin+1, hid2vmin-1 ; Clear the vmin bit
581 mtspr hid2, r13 ; Restore HID2 value
582 sync ; Wait for it to be done
583 b init750FX
584
585 ; 7400
586
587 init7400: bf firstBoot,i7400nb ; Do different if not initial boot...
588 mfspr r13,l2cr ; Get the L2CR
589 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
590 bne+ i7400hl2 ; Yes...
591 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
592
593 i7400hl2: lis r14,hi16(256*1024) ; Base L2 size
594 addis r15,r13,0x3000 ; Hah... Figure this one out...
595 rlwinm r15,r15,4,30,31
596 slw r14,r14,r15 ; Set 256KB, 512KB, 1MB, or 2MB
597
598 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
599 stw r13,pfl2cr(r30) ; Shadow the L2CR
600 stw r14,pfl2Size(r30) ; Set the L2 size
601
602 mfspr r11,hid0 ; Get the current HID0
603 oris r11,r11,hi16(emcpm|eiecm) ; ?
604 mtspr hid0,r11 ; ?
605 isync
606 stw r11,pfHID0(r30) ; Save the HID0 value
607
608 mfspr r11,msscr0 ; Get the msscr0 register
609 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
610 mfspr r11,msscr1 ; Get the msscr1 register
611 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
612 blr ; Return...
613
614 i7400nb:
615 li r11,0
616 mtspr l2cr,r11 ; Make sure L2CR is zero
617 lwz r11,pfHID0(r30) ; Get HID0
618 sync
619 mtspr hid0,r11 ; Set the HID
620 isync
621 sync
622 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
623 isync
624 sync
625 mtspr msscr0,r11 ; Set the MSSCR0
626 lwz r11,pfMSSCR1(r30) ; Get msscr1
627 isync
628 sync
629 mtspr msscr1,r11 ; Set the msscr1
630 isync
631 sync
632 blr
633
634 ; 7400 (ver 2.0 - ver 2.7)
635
636 init7400v2_7:
637 bf firstBoot, init7400
638 mfspr r13, hid0 ; Get the HID0
639 ori r13, r13, nopdstm ; ?
640 mtspr hid0, r13 ; Set the HID0
641 isync
642 sync
643 b init7400
644
645 ; 7410
646 ; Note that this is the same as 7400 except we initialize the l2cr2 register
647
648 init7410: li r13,0 ; Clear
649 mtspr 1016,r13 ; Turn off direct cache
650 b init7400 ; Join up with common....
651
652
653 ; 745X - Any 7450 family processor
654
655 init745X:
656 bf firstBoot,init745Xnb ; Do different if not initial boot...
657
658 mfspr r13,l2cr ; Get the L2CR
659 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
660 bne+ init745Xhl2 ; Yes...
661 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
662
663 init745Xhl2:
664 mfpvr r14 ; Get processor version
665 rlwinm r14,r14,16,16,31 ; Isolate processor version
666 cmpli cr0, r14, PROCESSOR_VERSION_7457 ; Test for 7457 or
667 cmpli cr1, r14, PROCESSOR_VERSION_7447A ; 7447A
668 cror cr0_eq, cr1_eq, cr0_eq
669 lis r14,hi16(512*1024) ; 512KB L2
670 beq init745Xhl2_2
671
672 lis r14,hi16(256*1024) ; Base L2 size
673 rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k
674 add r14,r14,r15 ; Add in minimum
675
676 init745Xhl2_2:
677 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
678 stw r13,pfl2cr(r30) ; Shadow the L2CR
679 stw r14,pfl2Size(r30) ; Set the L2 size
680
681 ; Take care of level 3 cache
682
683 mfspr r13,l3cr ; Get the L3CR
684 rlwinm. r0,r13,0,l3e,l3e ; Any L3?
685 bne+ init745Xhl3 ; Yes...
686 rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L3, turn off feature
687
688 init745Xhl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero
689 beq- init745Xnone ; Go turn off the features...
690 lis r14,hi16(1024*1024) ; Base L3 size
691 rlwinm r15,r13,4,31,31 ; Get size multiplier
692 slw r14,r14,r15 ; Set 1 or 2MB
693
694 stw r13,pfl3crOriginal(r30) ; Shadow the L3CR
695 stw r13,pfl3cr(r30) ; Shadow the L3CR
696 stw r14,pfl3Size(r30) ; Set the L3 size
697 b init745Xfin ; Return....
698
699 init745Xnone:
700 rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
701 rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set
702 or r17,r17,r11
703
704 init745Xfin:
705 rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set
706
707 mfspr r11,hid0 ; Get the current HID0
708 stw r11,pfHID0(r30) ; Save the HID0 value
709 mfspr r11,hid1 ; Get the current HID1
710 stw r11,pfHID1(r30) ; Save the HID1 value
711 mfspr r11,msscr0 ; Get the msscr0 register
712 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
713 mfspr r11,msscr1 ; Get the msscr1 register
714 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
715 mfspr r11,ictrl ; Get the ictrl register
716 stw r11,pfICTRL(r30) ; Save the ICTRL value
717 mfspr r11,ldstcr ; Get the ldstcr register
718 stw r11,pfLDSTCR(r30) ; Save the LDSTCR value
719 mfspr r11,ldstdb ; Get the ldstdb register
720 stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
721 mfspr r11,pir ; Get the pir register
722 stw r11,pfBootConfig(r30) ; Save the BootConfig value
723 blr ; Return....
724
725
726 init745Xnb: lwz r11,pfHID0(r30) ; Get HID0
727 sync
728 mtspr hid0,r11 ; Set the HID
729 isync
730 lwz r11,pfHID1(r30) ; Get HID1
731 sync
732 mtspr hid1,r11 ; Set the HID
733 isync
734 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
735 sync
736 mtspr msscr0,r11 ; Set the MSSCR0
737 isync
738 sync
739 lwz r11,pfICTRL(r30) ; Get ICTRL
740 sync
741 mtspr ictrl,r11 ; Set the ICTRL
742 isync
743 sync
744 lwz r11,pfLDSTCR(r30) ; Get LDSTCR
745 sync
746 mtspr ldstcr,r11 ; Set the LDSTCR
747 isync
748 sync
749 lwz r11,pfLDSTDB(r30) ; Get LDSTDB
750 sync
751 mtspr ldstdb,r11 ; Set the LDSTDB
752 isync
753 sync
754 blr
755
756 ; 7450 - Specific
757
758 init7450:
759 bf firstBoot, init745X ; Not boot, use standard init
760
761 mfspr r13, pir ; Get BootConfig from PIR
762 rlwinm. r14, r13, 0, 20, 23 ; Is the pdet value zero
763 bne init7450done ; No, done for now
764
765 ori r13, r13, 0x0400 ; Force pdet value to 4
766 mtspr pir, r13 ; Write back the BootConfig
767
768 init7450done:
769 b init745X ; Continue with standard init
770
771
772 init970:
773 lis r20,8 ; Set up for 512K L2
774 init970x:
775 li r0,0 ; Clear this
776 mtspr hior,r0 ; Make sure that 0 is interrupt prefix
777 bf firstBoot,init970nb ; No init for wakeup or second processor....
778
779
780 ;
781 ; We can not query or change the L2 size. We will just
782 ; phoney up a L2CR to make sysctl "happy" and set the
783 ; L2 size to 512K.
784 ;
785
786 lis r0,0x8000 ; Synthesize a "valid" but non-existant L2CR
787 stw r0,pfl2crOriginal(r30) ; Set a dummy L2CR
788 stw r0,pfl2cr(r30) ; Set a dummy L2CR
789 stw r20,pfl2Size(r30) ; Set the L2 size
790
791 mfspr r11,hid0 ; Get original hid0
792 std r11,pfHID0(r30) ; Save original
793 mfspr r11,hid1 ; Get original hid1
794 std r11,pfHID1(r30) ; Save original
795 mfspr r11,hid4 ; Get original hid4
796 std r11,pfHID4(r30) ; Save original
797 mfspr r11,hid5 ; Get original hid5
798 std r11,pfHID5(r30) ; Save original
799
800 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
801 sldi r0, r0, 32 ; Shift to the top half
802 ld r11,pfHID0(r30) ; Load the hid0 value
803 andc r11, r11, r0 ; Clear the dnap bit
804 isync
805 mtspr hid0,r11 ; Stuff it
806 mfspr r11,hid0 ; Get it
807 mfspr r11,hid0 ; Get it
808 mfspr r11,hid0 ; Get it
809 mfspr r11,hid0 ; Get it
810 mfspr r11,hid0 ; Get it
811 mfspr r11,hid0 ; Get it
812 isync
813
814 lis r0,(pcfValid|pcfLarge|pcfDedSeg)<<8 ; Set the valid bit, dedicated segment, and large page flags
815 ori r0,r0,(24<<8)|24 ; Add in the 16M page size
816 stw r0,lgpPcfg+(pcfSize*pcfLargePcfg)(0) ; Set the 16M primary large page configuration entry
817
818 blr
819
820 ;
821 ; Start up code for second processor or wake up from sleep
822 ;
823
824 init970nb:
825 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
826 sldi r0, r0, 32 ; Shift to the top half
827 ld r11,pfHID0(r30) ; Load the hid0 value
828 andc r11, r11, r0 ; Clear the dnap bit
829 isync
830 mtspr hid0,r11 ; Stuff it
831 mfspr r11,hid0 ; Get it
832 mfspr r11,hid0 ; Get it
833 mfspr r11,hid0 ; Get it
834 mfspr r11,hid0 ; Get it
835 mfspr r11,hid0 ; Get it
836 mfspr r11,hid0 ; Get it
837 isync
838
839 ld r20,pfHID1(r30) ; Get it
840 isync
841 mtspr hid1,r20 ; Stick it
842 mtspr hid1,r20 ; Stick it again
843 isync
844
845 ld r11,pfHID4(r30) ; Get it
846 sync
847 mtspr hid4,r11 ; Stick it
848 isync
849
850 lis r11,0xE000 ; Get the unlikeliest ESID possible
851 srdi r11,r11,1 ; Make 0x7FFFFFFFF0000000
852 slbie r11 ; Make sure the ERAT is cleared
853
854 ld r11,pfHID5(r30) ; Get it
855 mtspr hid5,r11 ; Set it
856 isync
857 ;
858 ; May have changed dcbz mode so kill icache
859 ;
860
861 eqv r13,r13,r13 ; Get a constant -1
862 mr r14,r20 ; Save HID1
863 rldimi r14,r13,54,9 ; Set force icbi match mode
864
865 li r11,0 ; Set start if ICBI range
866 isync
867 mtspr hid1,r14 ; Stick it
868 mtspr hid1,r14 ; Stick it again
869 isync
870
871 inin970ki: icbi 0,r11 ; Kill I$
872 addi r11,r11,128 ; Next line
873 andis. r0,r11,1 ; Have we done them all?
874 beq++ inin970ki ; Not yet...
875
876 isync
877 mtspr hid1,r20 ; Stick it
878 mtspr hid1,r20 ; Stick it again
879 isync
880
881 blr ; Leave...
882
883
884
885 ; Unsupported Processors
886 initUnsupported:
887 mtlr r2 ; Restore the return address
888 blr ; Return to the booter
889
890
891 ;
892 ; Processor to feature table
893
894 ; .align 2 - Always on word boundary
895 ; .long ptFilter - Mask of significant bits in the Version/Revision code
896 ; - NOTE: Always order from most restrictive to least restrictive matching
897 ; .short ptVersion - Version code from PVR. Always start with 0 which is default
898 ; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific
899 ; .long ptFeatures - Available features
900 ; .long ptCPUCap - Default value for _cpu_capabilities
901 ; .long ptPwrModes - Available power management features
902 ; .long ptPatch - Patch features
903 ; .long ptInitRout - Initilization routine. Can modify any of the other attributes.
904 ; .long ptRptdProc - Processor type reported
905 ; .long ptLineSize - Level 1 cache line size
906 ; .long ptl1iSize - Level 1 instruction cache size
907 ; .long ptl1dSize - Level 1 data cache size
908 ; .long ptPTEG - Size of PTEG
909 ; .long ptMaxVAddr - Maximum effective address
910 ; .long ptMaxPAddr - Maximum physical address
911 ;
912
913 .align 2
914 processor_types:
915
916 ; 750CX (ver 2.x)
917
918 .align 2
919 .long 0xFFFF0F00 ; 2.x vers
920 .short PROCESSOR_VERSION_750
921 .short 0x0200
922 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
923 .long kCache32 | kHasGraphicsOps | kHasStfiwx
924 .long 0
925 .long PatchExt32
926 .long init750CX
927 .long CPU_SUBTYPE_POWERPC_750
928 .long 32
929 .long 32*1024
930 .long 32*1024
931 .long 64
932 .long 52
933 .long 32
934
935 ; 750 (generic)
936
937 .align 2
938 .long 0xFFFF0000 ; All revisions
939 .short PROCESSOR_VERSION_750
940 .short 0
941 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
942 .long kCache32 | kHasGraphicsOps | kHasStfiwx
943 .long 0
944 .long PatchExt32
945 .long init750
946 .long CPU_SUBTYPE_POWERPC_750
947 .long 32
948 .long 32*1024
949 .long 32*1024
950 .long 64
951 .long 52
952 .long 32
953
954 ; 750FX (ver 1.x)
955
956 .align 2
957 .long 0xFFFF0F00 ; 1.x vers
958 .short PROCESSOR_VERSION_750FX
959 .short 0x0100
960 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
961 .long kCache32 | kHasGraphicsOps | kHasStfiwx
962 .long pmDualPLL
963 .long PatchExt32
964 .long init750FX
965 .long CPU_SUBTYPE_POWERPC_750
966 .long 32
967 .long 32*1024
968 .long 32*1024
969 .long 64
970 .long 52
971 .long 32
972
973 ; 750FX (generic)
974
975 .align 2
976 .long 0xFFFF0000 ; All revisions
977 .short PROCESSOR_VERSION_750FX
978 .short 0
979 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
980 .long kCache32 | kHasGraphicsOps | kHasStfiwx
981 .long pmDualPLL | pmDPLLVmin
982 .long PatchExt32
983 .long init750FXV2
984 .long CPU_SUBTYPE_POWERPC_750
985 .long 32
986 .long 32*1024
987 .long 32*1024
988 .long 64
989 .long 52
990 .long 32
991
992 ; 7400 (ver 2.0 - ver 2.7)
993
994 .align 2
995 .long 0xFFFFFFF8 ; ver 2.0 - 2.7
996 .short PROCESSOR_VERSION_7400
997 .short 0x0200
998 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
999 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1000 .long 0
1001 .long PatchExt32
1002 .long init7400v2_7
1003 .long CPU_SUBTYPE_POWERPC_7400
1004 .long 32
1005 .long 32*1024
1006 .long 32*1024
1007 .long 64
1008 .long 52
1009 .long 32
1010
1011 ; 7400 (generic)
1012
1013 .align 2
1014 .long 0xFFFF0000 ; All revisions
1015 .short PROCESSOR_VERSION_7400
1016 .short 0
1017 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1018 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1019 .long 0
1020 .long PatchExt32
1021 .long init7400
1022 .long CPU_SUBTYPE_POWERPC_7400
1023 .long 32
1024 .long 32*1024
1025 .long 32*1024
1026 .long 64
1027 .long 52
1028 .long 36
1029
1030 ; 7410 (ver 1.1)
1031
1032 .align 2
1033 .long 0xFFFFFFFF ; Exact match
1034 .short PROCESSOR_VERSION_7400
1035 .short 0x1101
1036 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1037 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1038 .long 0
1039 .long PatchExt32
1040 .long init7410
1041 .long CPU_SUBTYPE_POWERPC_7400
1042 .long 32
1043 .long 32*1024
1044 .long 32*1024
1045 .long 64
1046 .long 52
1047 .long 36
1048
1049 ; 7410 (generic)
1050
1051 .align 2
1052 .long 0xFFFF0000 ; All other revisions
1053 .short PROCESSOR_VERSION_7410
1054 .short 0
1055 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1056 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1057 .long 0
1058 .long PatchExt32
1059 .long init7410
1060 .long CPU_SUBTYPE_POWERPC_7400
1061 .long 32
1062 .long 32*1024
1063 .long 32*1024
1064 .long 64
1065 .long 52
1066 .long 36
1067
1068 ; 7450 (ver 1.xx)
1069
1070 .align 2
1071 .long 0xFFFFFF00 ; Just revisions 1.xx
1072 .short PROCESSOR_VERSION_7450
1073 .short 0x0100
1074 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1075 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1076 .long 0
1077 .long PatchExt32
1078 .long init7450
1079 .long CPU_SUBTYPE_POWERPC_7450
1080 .long 32
1081 .long 32*1024
1082 .long 32*1024
1083 .long 64
1084 .long 52
1085 .long 36
1086
1087 ; 7450 (2.0)
1088
1089 .align 2
1090 .long 0xFFFFFFFF ; Just revision 2.0
1091 .short PROCESSOR_VERSION_7450
1092 .short 0x0200
1093 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1094 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1095 .long 0
1096 .long PatchExt32
1097 .long init7450
1098 .long CPU_SUBTYPE_POWERPC_7450
1099 .long 32
1100 .long 32*1024
1101 .long 32*1024
1102 .long 64
1103 .long 52
1104 .long 36
1105
1106 ; 7450 (2.1)
1107
1108 .align 2
1109 .long 0xFFFF0000 ; All other revisions
1110 .short PROCESSOR_VERSION_7450
1111 .short 0
1112 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1113 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1114 .long 0
1115 .long PatchExt32
1116 .long init7450
1117 .long CPU_SUBTYPE_POWERPC_7450
1118 .long 32
1119 .long 32*1024
1120 .long 32*1024
1121 .long 64
1122 .long 52
1123 .long 36
1124
1125 ; 7455 (1.xx) Just like 7450 2.0
1126
1127 .align 2
1128 .long 0xFFFFFF00 ; Just revisions 1.xx
1129 .short PROCESSOR_VERSION_7455
1130 .short 0x0100
1131 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1132 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1133 .long 0
1134 .long PatchExt32
1135 .long init745X
1136 .long CPU_SUBTYPE_POWERPC_7450
1137 .long 32
1138 .long 32*1024
1139 .long 32*1024
1140 .long 64
1141 .long 52
1142 .long 36
1143
1144 ; 7455 (2.0)
1145
1146 .align 2
1147 .long 0xFFFFFFFF ; Just revision 2.0
1148 .short PROCESSOR_VERSION_7455
1149 .short 0x0200
1150 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1151 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1152 .long 0
1153 .long PatchExt32
1154 .long init745X
1155 .long CPU_SUBTYPE_POWERPC_7450
1156 .long 32
1157 .long 32*1024
1158 .long 32*1024
1159 .long 64
1160 .long 52
1161 .long 36
1162
1163 ; 7455 (2.1)
1164
1165 .align 2
1166 .long 0xFFFF0000 ; All other revisions
1167 .short PROCESSOR_VERSION_7455
1168 .short 0
1169 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1170 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1171 .long 0
1172 .long PatchExt32
1173 .long init745X
1174 .long CPU_SUBTYPE_POWERPC_7450
1175 .long 32
1176 .long 32*1024
1177 .long 32*1024
1178 .long 64
1179 .long 52
1180 .long 36
1181
1182 ; 7457
1183
1184 .align 2
1185 .long 0xFFFF0000 ; All revisions
1186 .short PROCESSOR_VERSION_7457
1187 .short 0
1188 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1189 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1190 .long 0
1191 .long PatchExt32
1192 .long init745X
1193 .long CPU_SUBTYPE_POWERPC_7450
1194 .long 32
1195 .long 32*1024
1196 .long 32*1024
1197 .long 64
1198 .long 52
1199 .long 36
1200
1201 ; 7447A
1202
1203 .align 2
1204 .long 0xFFFF0000 ; All revisions
1205 .short PROCESSOR_VERSION_7447A
1206 .short 0
1207 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1208 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1209 .long pmDFS
1210 .long PatchExt32
1211 .long init745X
1212 .long CPU_SUBTYPE_POWERPC_7450
1213 .long 32
1214 .long 32*1024
1215 .long 32*1024
1216 .long 64
1217 .long 52
1218 .long 36
1219
1220 ; 970
1221
1222 .align 2
1223 .long 0xFFFF0000 ; All versions so far
1224 .short PROCESSOR_VERSION_970
1225 .short 0
1226 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2 | pfSCOMFixUp
1227 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1228 .long 0
1229 .long PatchLwsync
1230 .long init970
1231 .long CPU_SUBTYPE_POWERPC_970
1232 .long 128
1233 .long 64*1024
1234 .long 32*1024
1235 .long 128
1236 .long 65
1237 .long 42
1238
1239 ; 970FX
1240
1241 .align 2
1242 .long 0xFFFF0000 ; All versions so far
1243 .short PROCESSOR_VERSION_970FX
1244 .short 0
1245 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2
1246 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1247 .long pmPowerTune
1248 .long PatchLwsync
1249 .long init970
1250 .long CPU_SUBTYPE_POWERPC_970
1251 .long 128
1252 .long 64*1024
1253 .long 32*1024
1254 .long 128
1255 .long 65
1256 .long 42
1257
1258
1259 ; All other processors are not supported
1260
1261 .align 2
1262 .long 0x00000000 ; Matches everything
1263 .short 0
1264 .short 0
1265 .long pfFloat | pf32Byte
1266 .long kCache32 | kHasGraphicsOps | kHasStfiwx
1267 .long 0
1268 .long PatchExt32
1269 .long initUnsupported
1270 .long CPU_SUBTYPE_POWERPC_ALL
1271 .long 32
1272 .long 32*1024
1273 .long 32*1024
1274 .long 64
1275 .long 52
1276 .long 32
1277
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