osfmk/ppc/commpage/cacheflush.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. Please obtain a copy of the License at
  10  * http://www.opensource.apple.com/apsl/ and read it before using this
  11  * file.
  12  *
  13  * The Original Code and all software distributed under the License are
  14  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  15  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  16  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  18  * Please see the License for the specific language governing rights and
  19  * limitations under the License.
  20  *
  21  * @APPLE_LICENSE_HEADER_END@
  22  */
  23
  24 #define ASSEMBLER
  25 #include <sys/appleapiopts.h>
  26 #include <ppc/asm.h>                                    // EXT, LEXT
  27 #include <machine/cpu_capabilities.h>
  28 #include <machine/commpage.h>
  29
  30         .text
  31         .align  2
  32
  33
  34 // *********************************************
  35 // * C O M M P A G E _ F L U S H _ D C A C H E *
  36 // *********************************************
  37 //
  38 // Note that this routine is called both in 32 and 64-bit mode.
  39 //
  40 //      r3 = ptr to 1st byte to flush
  41 //      r4 = length to flush (may be 0)
  42
  43 commpage_flush_dcache:
  44         mr.     r4,r4           // test length for 0 in mode-independent way
  45         lhz             r5,_COMM_PAGE_CACHE_LINESIZE(0)
  46         subi    r9,r5,1                 // get (linesize-1)
  47         and             r0,r3,r9                // get offset within line of 1st byte
  48         add             r4,r4,r0                // adjust length so we flush them all
  49         add             r4,r4,r9                // round length up...
  50         andc    r4,r4,r9                // ...to multiple of cache lines
  51         beqlr--                                 // length was 0, so exit
  52 1:
  53         sub.    r4,r4,r5                // more to go?
  54         dcbf    0,r3                    // flush another line
  55         add             r3,r3,r5
  56         bne             1b
  57         sync                                    // make sure lines are flushed before we return
  58         blr
  59
  60         COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,kCommPageBoth)
  61
  62
  63 // *********************************************
  64 // * C O M M P A G E _ F L U S H _ I C A C H E *
  65 // *********************************************
  66 //
  67 // Note that this routine is called both in 32 and 64-bit mode.
  68 //
  69 //      r3 = ptr to 1st byte to flush
  70 //      r4 = length to flush (may be 0)
  71
  72 commpage_flush_icache:
  73         mr.     r4,r4           // test length for 0 in mode-independent way
  74         lhz             r5,_COMM_PAGE_CACHE_LINESIZE(0)
  75         subi    r9,r5,1                 // get (linesize-1)
  76         and             r0,r3,r9                // get offset within line of 1st byte
  77         add             r4,r4,r0                // adjust length so we flush them all
  78         mr              r7,r3                   // copy ptr
  79         add             r4,r4,r9                // round length up...
  80         andc    r4,r4,r9                // ...to multiple of cache lines
  81         mr              r6,r4                   // copy length
  82         beqlr--                                 // length was 0, so exit
  83 1:
  84         sub.    r4,r4,r5                // more to go?
  85         dcbf    0,r3                    // flush another line
  86         add             r3,r3,r5
  87         bne             1b
  88         sync                                    // make sure lines are flushed
  89 2:
  90         sub.    r6,r6,r5                // more to go?
  91         icbi    0,r7
  92         add             r7,r7,r5
  93         bne             2b
  94
  95         // The following sync is only needed on MP machines, probably only on
  96         // 7400-family MP machines.  But because we're not certain of this, and
  97         // this isn't a speed critical routine, we are conservative and always sync.
  98
  99         sync                                    // wait until other processors see the icbi's
 100         isync                                   // make sure we haven't prefetched old instructions
 101
 102         blr
 103
 104         COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,kCommPageBoth)
 105
 106