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1 /*
2 * Copyright (c) 2002 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23
24 /* Emulate64.s
25 *
26 * Software emulation of instructions not handled in hw, on 64-bit machines.
27 */
28
29 #include <sys/appleapiopts.h>
30 #include <ppc/asm.h>
31 #include <ppc/proc_reg.h>
32 #include <ppc/exception.h>
33 #include <mach/machine/vm_param.h>
34 #include <ppc/cpu_capabilities.h>
35 #include <assym.s>
36
37 // CR bit set if the instruction is an "update" form (LFDU, STWU, etc):
38 #define kUpdate 25
39
40 // CR bit set if interrupt occured in trace mode (ie, MSR_SE_BIT):
41 #define kTrace 8
42
43 // CR bit set if notification on alignment interrupts is requested (notifyUnalignbit in spcFlags):
44 #define kNotify 9
45
46 // CR bit distinguishes between alignment and program exceptions:
47 #define kAlignment 10
48
49
50
51 // *************************************
52 // * P R O G R A M I N T E R R U P T *
53 // *************************************
54 //
55 // These are floating pt exceptions, illegal instructions, privileged mode violations,
56 // and traps. All we're interested in at this low level is illegal instructions.
57 // The ones we "emulate" are:
58 // DCBA, which is not implemented in the IBM 970. The emulation is to ignore it,
59 // as it is just a hint.
60 // MCRXR, which is not implemented on the IBM 970, but is in the PPC ISA.
61 //
62 // Additionally, to facilitate debugging the alignment handler, we recognize a special
63 // diagnostic mode that is used to simulate alignment exceptions. When in this mode,
64 // if the instruction has opcode==0 and the extended opcode is one of the X-form
65 // instructions that can take an alignment interrupt, then we change the opcode to
66 // 31 and pretend it got an alignment interrupt. This exercises paths that
67 // are hard to drive or perhaps never driven on this particular CPU.
68
69 .text
70 .globl EXT(Emulate64)
71 .align 5
72 LEXT(Emulate64)
73 crclr kAlignment // not an alignment exception
74 b a64AlignAssistJoin // join alignment handler
75
76
77 // Return from alignment handler with all the regs loaded for opcode emulation.
78
79 a64HandleProgramInt:
80 rlwinm. r0,r29,0,SRR1_PRG_ILL_INS_BIT,SRR1_PRG_ILL_INS_BIT // illegal opcode?
81 beq a64PassAlong // No, must have been trap or priv violation etc
82 rlwinm r3,r20,6,26,31 // right justify opcode field (bits 0-5)
83 rlwinm r4,r20,31,22,31 // right justify extended opcode field (bits 21-30)
84 cmpwi cr0,r3,31 // X-form?
85 cmpwi cr1,r4,758 // DCBA?
86 cmpwi cr4,r4,512 // MCRXR?
87 crand cr1_eq,cr0_eq,cr1_eq // merge the two tests for DCBA
88 crand cr4_eq,cr0_eq,cr4_eq // and for MCRXR
89 beq++ cr1_eq,a64ExitEm // was DCBA, so ignore
90 bne-- cr4_eq,a64NotEmulated // skip if not MCRXR
91
92 // Was MCRXR, so emulate.
93
94 ld r3,savexer(r13) // get the XER
95 lwz r4,savecr(r13) // and the CR
96 rlwinm r5,r20,11,27,29 // get (CR# * 4) from instruction
97 rlwinm r6,r3,0,4,31 // zero XER[32-35] (also XER[0-31])
98 sld r4,r4,r5 // move target CR field to bits 32-35
99 rlwimi r4,r3,0,0,3 // move XER[32-35] into CR field
100 stw r6,savexer+4(r13) // update XER
101 srd r4,r4,r5 // re-position CR
102 stw r4,savecr(r13) // update CR
103 b a64ExitEm // done
104
105 // Not an opcode we normally emulate. If in special diagnostic mode and opcode=0,
106 // emulate as an alignment exception. This special case is for test software.
107
108 a64NotEmulated:
109 lwz r30,dgFlags(0) // Get the flags
110 rlwinm. r0,r30,0,enaDiagEMb,enaDiagEMb // Do we want to try to emulate something?
111 beq++ a64PassAlong // No emulation allowed
112 cmpwi r3,0 // opcode==0 ?
113 bne a64PassAlong // not the special case
114 oris r20,r20,0x7C00 // change opcode to 31
115 crset kAlignment // say we took alignment exception
116 rlwinm r5,r4,0,26+1,26-1 // mask Update bit (32) out of extended opcode
117 rlwinm r5,r5,0,0,31 // Clean out leftover junk from rlwinm
118
119 cmpwi r4,1014 // dcbz/dcbz128 ?
120 crmove cr1_eq,cr0_eq
121 cmpwi r5,21 // ldx/ldux ?
122 cror cr1_eq,cr0_eq,cr1_eq
123 cmpwi r5,599 // lfdx/lfdux ?
124 cror cr1_eq,cr0_eq,cr1_eq
125 cmpwi r5,535 // lfsx/lfsux ?
126 cror cr1_eq,cr0_eq,cr1_eq
127 cmpwi r5,343 // lhax/lhaux ?
128 cror cr1_eq,cr0_eq,cr1_eq
129 cmpwi r4,790 // lhbrx ?
130 cror cr1_eq,cr0_eq,cr1_eq
131 cmpwi r5,279 // lhzx/lhzux ?
132 cror cr1_eq,cr0_eq,cr1_eq
133 cmpwi r4,597 // lswi ?
134 cror cr1_eq,cr0_eq,cr1_eq
135 cmpwi r4,533 // lswx ?
136 cror cr1_eq,cr0_eq,cr1_eq
137 cmpwi r5,341 // lwax/lwaux ?
138 cror cr1_eq,cr0_eq,cr1_eq
139 cmpwi r4,534 // lwbrx ?
140 cror cr1_eq,cr0_eq,cr1_eq
141 cmpwi r5,23 // lwz/lwzx ?
142 cror cr1_eq,cr0_eq,cr1_eq
143 cmpwi r5,149 // stdx/stdux ?
144 cror cr1_eq,cr0_eq,cr1_eq
145 cmpwi r5,727 // stfdx/stfdux ?
146 cror cr1_eq,cr0_eq,cr1_eq
147 cmpwi r4,983 // stfiwx ?
148 cror cr1_eq,cr0_eq,cr1_eq
149 cmpwi r5,663 // stfsx/stfsux ?
150 cror cr1_eq,cr0_eq,cr1_eq
151 cmpwi r4,918 // sthbrx ?
152 cror cr1_eq,cr0_eq,cr1_eq
153 cmpwi r5,407 // sthx/sthux ?
154 cror cr1_eq,cr0_eq,cr1_eq
155 cmpwi r4,725 // stswi ?
156 cror cr1_eq,cr0_eq,cr1_eq
157 cmpwi r4,661 // stswx ?
158 cror cr1_eq,cr0_eq,cr1_eq
159 cmpwi r4,662 // stwbrx ?
160 cror cr1_eq,cr0_eq,cr1_eq
161 cmpwi r5,151 // stwx/stwux ?
162 cror cr1_eq,cr0_eq,cr1_eq
163
164 beq++ cr1,a64GotInstruction // it was one of the X-forms we handle
165 crclr kAlignment // revert to program interrupt
166 b a64PassAlong // not recognized extended opcode
167
168
169 // *****************************************
170 // * A L I G N M E N T I N T E R R U P T *
171 // *****************************************
172 //
173 // We get here in exception context, ie with interrupts disabled, translation off, and
174 // in 64-bit mode, with:
175 // r13 = save-area pointer, with general context already saved in it
176 // cr6 = feature flags
177 // We preserve r13 and cr6. Other GPRs and CRs, the LR and CTR are used.
178 //
179 // Current 64-bit processors (GPUL) handle almost all misaligned operations in hardware,
180 // so this routine usually isn't called very often. Only floating pt ops that cross a page
181 // boundary and are not word aligned, and LMW/STMW can take exceptions to cacheable memory.
182 // However, in contrast to G3 and G4, any misaligned load/store will get an alignment
183 // interrupt on uncached memory.
184 //
185 // We always emulate scalar ops with a series of byte load/stores. Doing so is no slower
186 // than LWZ/STW in cases where a scalar op gets an alignment exception.
187 //
188 // This routine supports all legal permutations of alignment interrupts occuring in user or
189 // supervisor mode, 32 or 64-bit addressing, and translation on or off. We do not emulate
190 // instructions that go past the end of an address space, such as "LHZ -1(0)"; we just pass
191 // along the alignment exception rather than wrap around to byte 0.
192 //
193 // First, check for a few special cases such as virtual machines, etc.
194
195 .globl EXT(AlignAssist64)
196 .align 5
197 LEXT(AlignAssist64)
198 crset kAlignment // mark as alignment interrupt
199
200 a64AlignAssistJoin: // join here from program interrupt handler
201 li r0,0 // Get a 0
202 mfsprg r31,0 // get the per_proc data ptr
203 mcrf cr3,cr6 // save feature flags here...
204 lwz r21,spcFlags(r31) // grab the special flags
205 ld r29,savesrr1(r13) // get the MSR etc at the fault
206 ld r28,savesrr0(r13) // get the EA of faulting instruction
207 stw r0,savemisc3(r13) // Assume we will handle this ok
208 mfmsr r26 // save MSR at entry
209 rlwinm. r0,r21,0,runningVMbit,runningVMbit // Are we running a VM?
210 lwz r19,dgFlags(0) // Get the diagnostics flags
211 bne-- a64PassAlong // yes, let the virtual machine monitor handle
212
213
214 // Set up the MSR shadow regs. We turn on FP in this routine, and usually set DR and RI
215 // when accessing user space (the SLB is still set up with all the user space translations.)
216 // However, if the interrupt occured in the kernel with DR off, we keep it off while
217 // accessing the "target" address space. If we set DR to access the target space, we also
218 // set RI. The RI bit tells the exception handlers to clear cr0 beq and return if we get an
219 // exception accessing the user address space. We are careful to test cr0 beq after every such
220 // access. We keep the following "shadows" of the MSR in global regs across this code:
221 // r25 = MSR at entry, plus FP and probably DR and RI (used to access target space)
222 // r26 = MSR at entry
223 // r27 = free
224 // r29 = SRR1 (ie, MSR at interrupt)
225 // Note that EE and IR are always off, and SF is always on in this code.
226
227 rlwinm r3,r29,0,MSR_DR_BIT,MSR_DR_BIT // was translation on at fault?
228 rlwimi r3,r3,32-MSR_RI_BIT+MSR_DR_BIT,MSR_RI_BIT,MSR_RI_BIT // if DR was set, set RI too
229 or r25,r26,r3 // assemble MSR to use accessing target space
230
231
232 // Because the DSISR and DAR are either not set or are not to be trusted on some 64-bit
233 // processors on an alignment interrupt, we must fetch the faulting instruction ourselves,
234 // then decode/hash the opcode and reconstruct the EA manually.
235
236 mtmsr r25 // turn on FP and (if it was on at fault) DR and RI
237 isync // wait for it to happen
238 cmpw r0,r0 // turn on beq so we can check for DSIs
239 lwz r20,0(r28) // fetch faulting instruction, probably with DR on
240 bne-- a64RedriveAsISI // got a DSI trying to fetch it, pretend it was an ISI
241 mtmsr r26 // turn DR back off
242 isync // wait for it to happen
243
244
245 // Set a few flags while we wait for the faulting instruction to arrive from cache.
246
247 rlwinm. r0,r29,0,MSR_SE_BIT,MSR_SE_BIT // Were we single stepping?
248 stw r20,savemisc2(r13) // Save the instruction image in case we notify
249 crnot kTrace,cr0_eq
250 rlwinm. r0,r19,0,enaNotifyEMb,enaNotifyEMb // Should we notify?
251 crnot kNotify,cr0_eq
252
253
254 // Hash the intruction into a 5-bit value "AAAAB" used to index the branch table, and a
255 // 1-bit kUpdate flag, as follows:
256 // ¥ for X-form instructions (with primary opcode 31):
257 // the "AAAA" bits are bits 21-24 of the instruction
258 // the "B" bit is the XOR of bits 29 and 30
259 // the update bit is instruction bit 25
260 // ¥ for D and DS-form instructions (actually, any primary opcode except 31):
261 // the "AAAA" bits are bits 1-4 of the instruction
262 // the "B" bit is 0
263 // the update bit is instruction bit 5
264 //
265 // Just for fun (and perhaps a little speed on deep-pipe machines), we compute the hash,
266 // update flag, and EA without branches and with ipc >= 2.
267 //
268 // When we "bctr" to the opcode-specific reoutine, the following are all set up:
269 // MSR = EE and IR off, SF and FP on
270 // r12 = full 64-bit EA (r17 is clamped EA)
271 // r13 = save-area pointer (physical)
272 // r14 = ptr to saver0 in save-area (ie, to base of GPRs)
273 // r15 = 0x00000000FFFFFFFF if 32-bit mode fault, 0xFFFFFFFFFFFFFFFF if 64
274 // r16 = RA * 8 (ie, reg# not reg value)
275 // r17 = EA, clamped to 32 bits if 32-bit mode fault (see also r12)
276 // r18 = (RA|0) (reg value)
277 // r19 = -1 if X-form, 0 if D-form
278 // r20 = faulting instruction
279 // r21 = RT * 8 (ie, reg# not reg value)
280 // r22 = addr(aaFPopTable)+(RT*32), ie ptr to floating pt table for target register
281 // r25 = MSR at entrance, probably with DR and RI set (for access to target space)
282 // r26 = MSR at entrance
283 // r27 = free
284 // r28 = SRR0 (ie, EA of faulting instruction)
285 // r29 = SRR1 (ie, MSR at fault)
286 // r30 = scratch, usually user data
287 // r31 = per-proc pointer
288 // cr2 = kTrace, kNotify, and kAlignment flags
289 // cr3 = saved copy of feature flags used in lowmem vector code
290 // cr6 = bits 24-27 of CR are bits 24-27 of opcode if X-form, or bits 4-5 and 00 if D-form
291 // bit 25 is the kUpdate flag, set for update form instructions
292 // cr7 = bits 28-31 of CR are bits 28-31 of opcode if X-form, or 0 if D-form
293
294 a64GotInstruction: // here from program interrupt with instruction in r20
295 rlwinm r21,r20,6+6,20,25 // move the primary opcode (bits 0-6) to bits 20-25
296 la r14,saver0(r13) // r14 <- base address of GPR registers
297 xori r19,r21,0x07C0 // iff primary opcode is 31, set r19 to 0
298 rlwinm r16,r20,16+3,24,28 // r16 <- RA*8
299 subi r19,r19,1 // set bit 0 iff X-form (ie, if primary opcode is 31)
300 rlwinm r17,r20,21+3,24,28 // r17 <- RB*8 (if X-form)
301 sradi r19,r19,63 // r19 <- -1 if X-form, 0 if D-form
302 extsh r22,r20 // r22 <- displacement (if D-form)
303
304 ldx r23,r14,r17 // get (RB), if any
305 and r15,r20,r19 // instruction if X, 0 if D
306 andc r17,r21,r19 // primary opcode in bits 20-25 if D, 0 if X
307 ldx r18,r14,r16 // get (RA)
308 subi r24,r16,1 // set bit 0 iff RA==0
309 or r21,r15,r17 // r21 <- instruction if X, or bits 0-5 in bits 20-25 if D
310 sradi r24,r24,63 // r24 <- -1 if RA==0, 0 otherwise
311 rlwinm r17,r21,32-4,25,28 // shift opcode bits 21-24 to 25-28 (hash "AAAA" bits)
312 lis r10,ha16(a64BranchTable) // start to build up branch table address
313 rlwimi r17,r21,0,29,29 // move opcode bit 29 into hash as start of "B" bit
314 rlwinm r30,r21,1,29,29 // position opcode bit 30 in position 29
315 and r12,r23,r19 // RB if X-form, 0 if D-form
316 andc r11,r22,r19 // 0 if X-form, sign extended displacement if D-form
317 xor r17,r17,r30 // bit 29 ("B") of hash is xor(bit29,bit30)
318 addi r10,r10,lo16(a64BranchTable)
319 or r12,r12,r11 // r12 <- (RB) or displacement, as appropriate
320 lwzx r30,r10,r17 // get address from branch table
321 mtcrf 0x01,r21 // move opcode bits 28-31 to CR7
322 sradi r15,r29,32 // propogate SF bit from SRR1 (MSR_SF, which is bit 0)
323 andc r18,r18,r24 // r18 <- (RA|0)
324 mtcrf 0x02,r21 // move opcode bits 24-27 to CR6 (kUpdate is bit 25)
325 add r12,r18,r12 // r12 <- 64-bit EA
326 mtctr r30 // set up branch address
327
328 oris r15,r15,0xFFFF // start to fill low word of r15 with 1s
329 rlwinm r21,r20,11+3,24,28 // r21 <- RT * 8
330 lis r22,ha16(EXT(aaFPopTable)) // start to compute address of floating pt table
331 ori r15,r15,0xFFFF // now bits 32-63 of r15 are 1s
332 addi r22,r22,lo16(EXT(aaFPopTable))
333 and r17,r12,r15 // clamp EA to 32 bits if fault occured in 32-bit mode
334 rlwimi r22,r21,2,22,26 // move RT into aaFPopTable address (which is 1KB aligned)
335
336 bf-- kAlignment,a64HandleProgramInt // return to Program Interrupt handler
337 bctr // if alignment interrupt, jump to opcode-specific routine
338
339
340 // Floating-pt load single (lfs[u], lfsx[u])
341
342 a64LfsLfsx:
343 bl a64Load4Bytes // get data in r30
344 mtctr r22 // set up address of "lfs fRT,emfp0(r31)"
345 stw r30,emfp0(r31) // put word here for aaFPopTable routine
346 bctrl // do the lfs
347 b a64UpdateCheck // update RA if necessary and exit
348
349
350 // Floating-pt store single (stfs[u], stfsx[u])
351
352 a64StfsStfsx:
353 ori r22,r22,8 // set dir==1 (ie, single store) in aaFPopTable
354 mtctr r22 // set up address of "stfs fRT,emfp0(r31)"
355 bctrl // execute the store into emfp0
356 lwz r30,emfp0(r31) // get the word
357 bl a64Store4Bytes // store r30 into user space
358 b a64UpdateCheck // update RA if necessary and exit
359
360
361 // Floating-pt store as integer word (stfiwx)
362
363 a64Stfiwx:
364 ori r22,r22,16+8 // set size=1, dir==1 (ie, double store) in aaFPopTable
365 mtctr r22 // set up FP register table address
366 bctrl // double precision store into emfp0
367 lwz r30,emfp0+4(r31) // get the low-order word
368 bl a64Store4Bytes // store r30 into user space
369 b a64Exit // successfully emulated
370
371
372 // Floating-pt load double (lfd[u], lfdx[u])
373
374 a64LfdLfdx:
375 ori r22,r22,16 // set Double bit in aaFPopTable address
376 bl a64Load8Bytes // get data in r30
377 mtctr r22 // set up address of "lfd fRT,emfp0(r31)"
378 std r30,emfp0(r31) // put doubleword here for aaFPopTable routine
379 bctrl // execute the load
380 b a64UpdateCheck // update RA if necessary and exit
381
382
383 // Floating-pt store double (stfd[u], stfdx[u])
384
385 a64StfdStfdx:
386 ori r22,r22,16+8 // set size=1, dir==1 (ie, double store) in aaFPopTable address
387 mtctr r22 // address of routine to stfd RT
388 bctrl // store into emfp0
389 ld r30,emfp0(r31) // get the doubleword
390 bl a64Store8Bytes // store r30 into user space
391 b a64UpdateCheck // update RA if necessary and exit
392
393
394 // Load halfword w 0-fill (lhz[u], lhzx[u])
395
396 a64LhzLhzx:
397 bl a64Load2Bytes // load into r30 from user space (w 0-fill)
398 stdx r30,r14,r21 // store into RT slot in register file
399 b a64UpdateCheck // update RA if necessary and exit
400
401
402 // Load halfword w sign fill (lha[u], lhax[u])
403
404 a64LhaLhax:
405 bl a64Load2Bytes // load into r30 from user space (w 0-fill)
406 extsh r30,r30 // sign-extend
407 stdx r30,r14,r21 // store into RT slot in register file
408 b a64UpdateCheck // update RA if necessary and exit
409
410
411 // Load halfword byte reversed (lhbrx)
412
413 a64Lhbrx:
414 bl a64Load2Bytes // load into r30 from user space (w 0-fill)
415 rlwinm r3,r30,8,16,23 // reverse bytes into r3
416 rlwimi r3,r30,24,24,31
417 stdx r3,r14,r21 // store into RT slot in register file
418 b a64Exit // successfully emulated
419
420
421 // Store halfword (sth[u], sthx[u])
422
423 a64SthSthx:
424 ldx r30,r14,r21 // get RT
425 bl a64Store2Bytes // store r30 into user space
426 b a64UpdateCheck // update RA if necessary and exit
427
428
429 // Store halfword byte reversed (sthbrx)
430
431 a64Sthbrx:
432 addi r21,r21,6 // point to low two bytes of RT
433 lhbrx r30,r14,r21 // load and reverse
434 bl a64Store2Bytes // store r30 into user space
435 b a64Exit // successfully emulated
436
437
438 // Load word w 0-fill (lwz[u], lwzx[u]), also lwarx.
439
440 a64LwzLwzxLwarx:
441 andc r3,r19,r20 // light bit 30 of r3 iff lwarx
442 andi. r0,r3,2 // is it lwarx?
443 bne-- a64PassAlong // yes, never try to emulate a lwarx
444 bl a64Load4Bytes // load 4 bytes from user space into r30 (0-filled)
445 stdx r30,r14,r21 // update register file
446 b a64UpdateCheck // update RA if necessary and exit
447
448
449 // Load word w sign fill (lwa, lwax[u])
450
451 a64Lwa:
452 crclr kUpdate // no update form of lwa (its a reserved encoding)
453 a64Lwax:
454 bl a64Load4Bytes // load 4 bytes from user space into r30 (0-filled)
455 extsw r30,r30 // sign extend
456 stdx r30,r14,r21 // update register file
457 b a64UpdateCheck // update RA if necessary and exit
458
459
460 // Load word byte reversed (lwbrx)
461
462 a64Lwbrx:
463 bl a64Load4Bytes // load 4 bytes from user space into r30 (0-filled)
464 rlwinm r3,r30,24,0,31 // flip bytes 1234 to 4123
465 rlwimi r3,r30,8,8,15 // r3 is now 4323
466 rlwimi r3,r30,8,24,31 // r3 is now 4321
467 stdx r3,r14,r21 // update register file
468 b a64Exit // successfully emulated
469
470
471 // Store word (stw[u], stwx[u])
472
473 a64StwStwx:
474 ldx r30,r14,r21 // get RT
475 bl a64Store4Bytes // store r30 into user space
476 b a64UpdateCheck // update RA if necessary and exit
477
478
479 // Store word byte reversed (stwbrx)
480
481 a64Stwbrx:
482 addi r21,r21,4 // point to low word of RT
483 lwbrx r30,r14,r21 // load and reverse
484 bl a64Store4Bytes // store r30 into user space
485 b a64Exit // successfully emulated
486
487
488 // Load doubleword (ld[u], ldx[u]), also lwa.
489
490 a64LdLwa: // these are DS form: ld=0, ldu=1, and lwa=2
491 mtcrf 0x01,r20 // move DS field to cr7
492 rlwinm r3,r20,0,30,31 // must adjust EA by subtracting DS field
493 sub r12,r12,r3 // subtract from full 64-bit EA
494 and r17,r12,r15 // then re-clamp to 32 bits if necessary
495 bt 30,a64Lwa // handle lwa
496 crmove kUpdate,31 // if opcode bit 31 is set, it is ldu so set update flag
497 a64Ldx:
498 bl a64Load8Bytes // load 8 bytes from user space into r30
499 stdx r30,r14,r21 // update register file
500 b a64UpdateCheck // update RA if necessary and exit
501
502
503 // Store doubleword (stdx[u], std[u], stwcx)
504
505 a64StdxStwcx:
506 bf-- 30,a64PassAlong // stwcx, so pass along alignment exception
507 b a64Stdx // was stdx
508 a64StdStfiwx: // if DS form: 0=std, 1=stdu, 2-3=undefined
509 bt 30,a64Stfiwx // handle stfiwx
510 rlwinm r3,r20,0,30,31 // must adjust EA by subtracting DS field
511 mtcrf 0x01,r20 // move DS field to cr7
512 sub r12,r12,r3 // subtract from full 64-bit EA
513 and r17,r12,r15 // then re-clamp to 32 bits if necessary
514 crmove kUpdate,31 // if DS==1, then it is update form
515 a64Stdx:
516 ldx r30,r14,r21 // get RT
517 bl a64Store8Bytes // store RT into user space
518 b a64UpdateCheck // update RA if necessary and exit
519
520
521 // Dcbz and Dcbz128 (bit 10 distinguishes the two forms)
522
523 a64DcbzDcbz128:
524 andis. r0,r20,0x0020 // bit 10 set?
525 li r3,0 // get a 0 to store
526 li r0,4 // assume 32-bit version, store 8 bytes 4x
527 rldicr r17,r17,0,63-5 // 32-byte align EA
528 li r4,_COMM_PAGE_BASE_ADDRESS
529 beq a64DcbzSetup // it was the 32-byte version
530 rldicr r17,r17,0,63-7 // zero low 7 bits of EA
531 li r0,16 // store 8 bytes 16x
532 a64DcbzSetup:
533 sub r4,r28,r4 // get instruction offset from start of commpage
534 and r4,r4,r15 // mask off high-order bits if 32-bit mode
535 cmpldi r4,_COMM_PAGE_AREA_USED // did fault occur in commpage area?
536 bge a64NotCommpage // not in commpage
537 rlwinm. r4,r29,0,MSR_PR_BIT,MSR_PR_BIT // did fault occur in user mode?
538 beq-- a64NotCommpage // do not zero cr7 if kernel got alignment exception
539 lwz r4,savecr(r13) // if we take a dcbz{128} in the commpage...
540 rlwinm r4,r4,0,0,27 // ...clear user's cr7...
541 stw r4,savecr(r13) // ...as a flag for commpage code
542 a64NotCommpage:
543 mtctr r0
544 cmpw r0,r0 // turn cr0 beq on so we can check for DSIs
545 mtmsr r25 // turn on DR and RI so we can address user space
546 isync // wait for it to happen
547 a64DcbzLoop:
548 std r3,0(r17) // store into user space
549 bne-- a64RedriveAsDSI
550 addi r17,r17,8
551 bdnz a64DcbzLoop
552
553 mtmsr r26 // restore MSR
554 isync // wait for it to happen
555 b a64Exit
556
557
558 // Load and store multiple (lmw, stmw), distinguished by bit 25
559
560 a64LmwStmw:
561 subfic r22,r21,32*8 // how many regs to load or store?
562 srwi r22,r22,1 // get bytes to load/store
563 bf 25,a64LoadMultiple // handle lmw
564 b a64StoreMultiple // it was stmw
565
566
567 // Load string word immediate (lswi)
568
569 a64Lswi:
570 rlwinm r22,r20,21,27,31 // get #bytes in r22
571 and r17,r18,r15 // recompute EA as (RA|0), and clamp
572 subi r3,r22,1 // r22==0?
573 rlwimi r22,r3,6,26,26 // map count of 0 to 32
574 b a64LoadMultiple
575
576
577 // Store string word immediate (stswi)
578
579 a64Stswi:
580 rlwinm r22,r20,21,27,31 // get #bytes in r22
581 and r17,r18,r15 // recompute EA as (RA|0), and clamp
582 subi r3,r22,1 // r22==0?
583 rlwimi r22,r3,6,26,26 // map count of 0 to 32
584 b a64StoreMultiple
585
586
587 // Load string word indexed (lswx), also lwbrx
588
589 a64LswxLwbrx:
590 bf 30,a64Lwbrx // was lwbrx
591 ld r22,savexer(r13) // get the xer
592 rlwinm r22,r22,0,25,31 // isolate the byte count
593 b a64LoadMultiple // join common code
594
595
596 // Store string word indexed (stswx), also stwbrx
597
598 a64StswxStwbrx:
599 bf 30,a64Stwbrx // was stwbrx
600 ld r22,savexer(r13) // get the xer
601 rlwinm r22,r22,0,25,31 // isolate the byte count
602 b a64StoreMultiple // join common code
603
604
605 // Load multiple words. This handles lmw, lswi, and lswx.
606
607 a64LoadMultiple: // r22 = byte count, may be 0
608 subic. r3,r22,1 // get (#bytes-1)
609 blt a64Exit // done if 0
610 add r4,r17,r3 // get EA of last operand byte
611 and r4,r4,r15 // clamp
612 cmpld r4,r17 // address space wrap?
613 blt-- a64PassAlong // pass along exception if so
614 srwi. r4,r22,2 // get # full words to load
615 rlwinm r22,r22,0,30,31 // r22 <- leftover byte count
616 cmpwi cr1,r22,0 // leftover bytes?
617 beq a64Lm3 // no words
618 mtctr r4 // set up word count
619 cmpw r0,r0 // set beq for DSI test
620 a64Lm2:
621 mtmsr r25 // turn on DR and RI
622 isync // wait for it to happen
623 lbz r3,0(r17)
624 bne-- a64RedriveAsDSI // got a DSI
625 lbz r4,1(r17)
626 bne-- a64RedriveAsDSI // got a DSI
627 lbz r5,2(r17)
628 bne-- a64RedriveAsDSI // got a DSI
629 lbz r6,3(r17)
630 bne-- a64RedriveAsDSI // got a DSI
631 rlwinm r30,r3,24,0,7 // pack bytes into r30
632 rldimi r30,r4,16,40
633 rldimi r30,r5,8,48
634 rldimi r30,r6,0,56
635 mtmsr r26 // turn DR back off so we can store into register file
636 isync
637 addi r17,r17,4 // bump EA
638 stdx r30,r14,r21 // pack into register file
639 addi r21,r21,8 // bump register file offset
640 rlwinm r21,r21,0,24,28 // wrap around to 0
641 bdnz a64Lm2
642 a64Lm3: // cr1/r22 = leftover bytes (0-3), cr0 beq set
643 beq cr1,a64Exit // no leftover bytes
644 mtctr r22
645 mtmsr r25 // turn on DR so we can access user space
646 isync
647 lbz r3,0(r17) // get 1st leftover byte
648 bne-- a64RedriveAsDSI // got a DSI
649 rlwinm r30,r3,24,0,7 // position in byte 4 of r30 (and clear rest of r30)
650 bdz a64Lm4 // only 1 byte leftover
651 lbz r3,1(r17) // get 2nd byte
652 bne-- a64RedriveAsDSI // got a DSI
653 rldimi r30,r3,16,40 // insert into byte 5 of r30
654 bdz a64Lm4 // only 2 bytes leftover
655 lbz r3,2(r17) // get 3rd byte
656 bne-- a64RedriveAsDSI // got a DSI
657 rldimi r30,r3,8,48 // insert into byte 6
658 a64Lm4:
659 mtmsr r26 // turn DR back off so we can store into register file
660 isync
661 stdx r30,r14,r21 // pack partially-filled word into register file
662 b a64Exit
663
664
665 // Store multiple words. This handles stmw, stswi, and stswx.
666
667 a64StoreMultiple: // r22 = byte count, may be 0
668 subic. r3,r22,1 // get (#bytes-1)
669 blt a64Exit // done if 0
670 add r4,r17,r3 // get EA of last operand byte
671 and r4,r4,r15 // clamp
672 cmpld r4,r17 // address space wrap?
673 blt-- a64PassAlong // pass along exception if so
674 srwi. r4,r22,2 // get # full words to load
675 rlwinm r22,r22,0,30,31 // r22 <- leftover byte count
676 cmpwi cr1,r22,0 // leftover bytes?
677 beq a64Sm3 // no words
678 mtctr r4 // set up word count
679 cmpw r0,r0 // turn on beq so we can check for DSIs
680 a64Sm2:
681 ldx r30,r14,r21 // get next register
682 addi r21,r21,8 // bump register file offset
683 rlwinm r21,r21,0,24,28 // wrap around to 0
684 srwi r3,r30,24 // shift the four bytes into position
685 srwi r4,r30,16
686 srwi r5,r30,8
687 mtmsr r25 // turn on DR so we can access user space
688 isync // wait for it to happen
689 stb r3,0(r17)
690 bne-- a64RedriveAsDSI // got a DSI
691 stb r4,1(r17)
692 bne-- a64RedriveAsDSI // got a DSI
693 stb r5,2(r17)
694 bne-- a64RedriveAsDSI // got a DSI
695 stb r30,3(r17)
696 bne-- a64RedriveAsDSI // got a DSI
697 mtmsr r26 // turn DR back off
698 isync
699 addi r17,r17,4 // bump EA
700 bdnz a64Sm2
701 a64Sm3: // r22 = 0-3, cr1 set on r22, cr0 beq set
702 beq cr1,a64Exit // no leftover bytes
703 ldx r30,r14,r21 // get last register
704 mtctr r22
705 mtmsr r25 // turn on DR so we can access user space
706 isync // wait for it to happen
707 a64Sm4:
708 rlwinm r30,r30,8,0,31 // position next byte
709 stb r30,0(r17) // pack into user space
710 addi r17,r17,1 // bump user space ptr
711 bne-- a64RedriveAsDSI // got a DSI
712 bdnz a64Sm4
713 mtmsr r26 // turn DR back off
714 isync
715 b a64Exit
716
717
718 // Subroutines to load bytes from user space.
719
720 a64Load2Bytes: // load 2 bytes right-justified into r30
721 addi r7,r17,1 // get EA of last byte
722 and r7,r7,r15 // clamp
723 cmpld r7,r17 // address wrap?
724 blt-- a64PassAlong // yes
725 mtmsr r25 // turn on DR so we can access user space
726 isync // wait for it to happen
727 sub. r30,r30,r30 // 0-fill dest and set beq
728 b a64Load2 // jump into routine
729 a64Load4Bytes: // load 4 bytes right-justified into r30 (ie, low order word)
730 addi r7,r17,3 // get EA of last byte
731 and r7,r7,r15 // clamp
732 cmpld r7,r17 // address wrap?
733 blt-- a64PassAlong // yes
734 mtmsr r25 // turn on DR so we can access user space
735 isync // wait for it to happen
736 sub. r30,r30,r30 // 0-fill dest and set beq
737 b a64Load4 // jump into routine
738 a64Load8Bytes: // load 8 bytes into r30
739 addi r7,r17,7 // get EA of last byte
740 and r7,r7,r15 // clamp
741 cmpld r7,r17 // address wrap?
742 blt-- a64PassAlong // yes
743 mtmsr r25 // turn on DR so we can access user space
744 isync // wait for it to happen
745 sub. r30,r30,r30 // 0-fill dest and set beq
746 lbz r3,-7(r7) // get byte 0
747 bne-- a64RedriveAsDSI // got a DSI
748 lbz r4,-6(r7) // and byte 1, etc
749 bne-- a64RedriveAsDSI // got a DSI
750 lbz r5,-5(r7)
751 bne-- a64RedriveAsDSI // got a DSI
752 lbz r6,-4(r7)
753 bne-- a64RedriveAsDSI // got a DSI
754 rldimi r30,r3,56,0 // position bytes in upper word
755 rldimi r30,r4,48,8
756 rldimi r30,r5,40,16
757 rldimi r30,r6,32,24
758 a64Load4:
759 lbz r3,-3(r7)
760 bne-- a64RedriveAsDSI // got a DSI
761 lbz r4,-2(r7)
762 bne-- a64RedriveAsDSI // got a DSI
763 rldimi r30,r3,24,32 // insert bytes 4 and 5 into r30
764 rldimi r30,r4,16,40
765 a64Load2:
766 lbz r3,-1(r7)
767 bne-- a64RedriveAsDSI // got a DSI
768 lbz r4,0(r7)
769 bne-- a64RedriveAsDSI // got a DSI
770 mtmsr r26 // turn DR back off
771 isync
772 rldimi r30,r3,8,48 // insert bytes 6 and 7 into r30
773 rldimi r30,r4,0,56
774 blr
775
776
777 // Subroutines to store bytes into user space.
778
779 a64Store2Bytes: // store bytes 6 and 7 of r30
780 addi r7,r17,1 // get EA of last byte
781 and r7,r7,r15 // clamp
782 cmpld r7,r17 // address wrap?
783 blt-- a64PassAlong // yes
784 mtmsr r25 // turn on DR so we can access user space
785 isync // wait for it to happen
786 cmpw r0,r0 // set beq so we can check for DSI
787 b a64Store2 // jump into routine
788 a64Store4Bytes: // store bytes 4-7 of r30 (ie, low order word)
789 addi r7,r17,3 // get EA of last byte
790 and r7,r7,r15 // clamp
791 cmpld r7,r17 // address wrap?
792 blt-- a64PassAlong // yes
793 mtmsr r25 // turn on DR so we can access user space
794 isync // wait for it to happen
795 cmpw r0,r0 // set beq so we can check for DSI
796 b a64Store4 // jump into routine
797 a64Store8Bytes: // r30 = bytes
798 addi r7,r17,7 // get EA of last byte
799 and r7,r7,r15 // clamp
800 cmpld r7,r17 // address wrap?
801 blt-- a64PassAlong // yes
802 mtmsr r25 // turn on DR so we can access user space
803 isync // wait for it to happen
804 cmpw r0,r0 // set beq so we can check for DSI
805 rotldi r3,r30,8 // shift byte 0 into position
806 rotldi r4,r30,16 // and byte 1
807 rotldi r5,r30,24 // and byte 2
808 rotldi r6,r30,32 // and byte 3
809 stb r3,-7(r7) // store byte 0
810 bne-- a64RedriveAsDSI // got a DSI
811 stb r4,-6(r7) // and byte 1 etc...
812 bne-- a64RedriveAsDSI // got a DSI
813 stb r5,-5(r7)
814 bne-- a64RedriveAsDSI // got a DSI
815 stb r6,-4(r7)
816 bne-- a64RedriveAsDSI // got a DSI
817 a64Store4:
818 rotldi r3,r30,40 // shift byte 4 into position
819 rotldi r4,r30,48 // and byte 5
820 stb r3,-3(r7)
821 bne-- a64RedriveAsDSI // got a DSI
822 stb r4,-2(r7)
823 bne-- a64RedriveAsDSI // got a DSI
824 a64Store2:
825 rotldi r3,r30,56 // shift byte 6 into position
826 stb r3,-1(r7) // store byte 6
827 bne-- a64RedriveAsDSI // got a DSI
828 stb r30,0(r7) // store byte 7, which is already positioned
829 bne-- a64RedriveAsDSI // got a DSI
830 mtmsr r26 // turn off DR
831 isync
832 blr
833
834
835 // Exit routines.
836
837 a64ExitEm:
838 li r30,T_EMULATE // Change exception code to emulate
839 stw r30,saveexception(r13) // Save it
840 b a64Exit // Join standard exit routine...
841
842 a64PassAlong: // unhandled exception, just pass it along
843 li r0,1 // Set that the alignment/program exception was not emulated
844 crset kNotify // return T_ALIGNMENT or T_PROGRAM
845 stw r0,savemisc3(r13) // Set that emulation was not done
846 crclr kTrace // not a trace interrupt
847 b a64Exit1
848 a64UpdateCheck: // successfully emulated, may be update form
849 bf kUpdate,a64Exit // update?
850 stdx r12,r14,r16 // yes, store 64-bit EA into RA
851 a64Exit: // instruction successfully emulated
852 addi r28,r28,4 // bump SRR0 past the emulated instruction
853 li r30,T_IN_VAIN // eat the interrupt since we emulated it
854 and r28,r28,r15 // clamp to address space size (32 vs 64)
855 std r28,savesrr0(r13) // save, so we return to next instruction
856 a64Exit1:
857 bt-- kTrace,a64Trace // were we in single-step at fault?
858 bt-- kNotify,a64Notify // should we say T_ALIGNMENT anyway?
859 a64Exit2:
860 mcrf cr6,cr3 // restore feature flags
861 mr r11,r30 // pass back exception code (T_IN_VAIN etc) in r11
862 b EXT(EmulExit) // return to exception processing
863
864
865 // Notification requested: pass exception upstairs even though it might have been emulated.
866
867 a64Notify:
868 li r30,T_ALIGNMENT // somebody wants to know about it (but don't redrive)
869 bt kAlignment,a64Exit2 // was an alignment exception
870 li r30,T_PROGRAM // was an emulated instruction
871 b a64Exit2
872
873
874 // Emulate a trace interrupt after handling alignment interrupt.
875
876 a64Trace:
877 lwz r9,SAVflags(r13) // get the save-area flags
878 li r30,T_TRACE
879 oris r9,r9,hi16(SAVredrive) // Set the redrive bit
880 stw r30,saveexception(r13) // Set the exception code
881 stw r9,SAVflags(r13) // Set the flags
882 b a64Exit2 // Exit and do trace interrupt...
883
884
885 // Got a DSI accessing user space. Redrive. One way this can happen is if another
886 // processor removes a mapping while we are emulating.
887
888 a64RedriveAsISI: // this DSI happened fetching the opcode (r1==DSISR r4==DAR)
889 mtmsr r26 // turn DR back off
890 isync // wait for it to happen
891 li r30,T_INSTRUCTION_ACCESS
892 rlwimi r29,r1,0,0,4 // insert the fault type from DSI's DSISR
893 std r29,savesrr1(r13) // update SRR1 to look like an ISI
894 b a64Redrive
895
896 a64RedriveAsDSI: // r0==DAR r1==DSISR
897 mtmsr r26 // turn DR back off
898 isync // wait for it to happen
899 stw r1,savedsisr(r13) // Set the DSISR of failed access
900 std r0,savedar(r13) // Set the address of the failed access
901 li r30,T_DATA_ACCESS // Set failing data access code
902 a64Redrive:
903 lwz r9,SAVflags(r13) // Pick up the flags
904 stw r30,saveexception(r13) // Set the replacement code
905 oris r9,r9,hi16(SAVredrive) // Set the redrive bit
906 stw r9,SAVflags(r13) // Set redrive request
907 crclr kTrace // don't take a trace interrupt
908 crclr kNotify // don't pass alignment exception
909 b a64Exit2 // done
910
911
912 // This is the branch table, indexed by the "AAAAB" opcode hash.
913
914 a64BranchTable:
915 .long a64LwzLwzxLwarx // 00000 lwz[u], lwzx[u], lwarx
916 .long a64Ldx // 00001 ldx[u]
917 .long a64PassAlong // 00010 ldarx (never emulate these)
918 .long a64PassAlong // 00011
919 .long a64StwStwx // 00100 stw[u], stwx[u]
920 .long a64StdxStwcx // 00101 stdx[u], stwcx
921 .long a64PassAlong // 00110
922 .long a64PassAlong // 00111 stdcx (never emulate these)
923 .long a64LhzLhzx // 01000 lhz[u], lhzx[u]
924 .long a64PassAlong // 01001
925 .long a64LhaLhax // 01010 lha[u], lhax[u]
926 .long a64Lwax // 01011 lwax[u]
927 .long a64SthSthx // 01100 sth[u], sthx[u]
928 .long a64PassAlong // 01101
929 .long a64LmwStmw // 01110 lmw, stmw
930 .long a64PassAlong // 01111
931 .long a64LfsLfsx // 10000 lfs[u], lfsx[u]
932 .long a64LswxLwbrx // 10001 lswx, lwbrx
933 .long a64LfdLfdx // 10010 lfd[u], lfdx[u]
934 .long a64Lswi // 10011 lswi
935 .long a64StfsStfsx // 10100 stfs[u], stfsx[u]
936 .long a64StswxStwbrx // 10101 stswx, stwbrx
937 .long a64StfdStfdx // 10110 stfd[u], stfdx[u]
938 .long a64Stswi // 10111 stswi
939 .long a64PassAlong // 11000
940 .long a64Lhbrx // 11001 lhbrx
941 .long a64LdLwa // 11010 ld[u], lwa
942 .long a64PassAlong // 11011
943 .long a64PassAlong // 11100
944 .long a64Sthbrx // 11101 sthbrx
945 .long a64StdStfiwx // 11110 std[u], stfiwx
946 .long a64DcbzDcbz128 // 11111 dcbz, dcbz128
947
948
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