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1 /*
2 * Copyright (c) 2000-2018 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56 /*
57 */
58
59 /*
60 * Hardware trap/fault handler.
61 */
62
63 #include <mach_kdp.h>
64 #include <mach_ldebug.h>
65
66 #include <types.h>
67 #include <i386/eflags.h>
68 #include <i386/trap.h>
69 #include <i386/pmap.h>
70 #include <i386/fpu.h>
71 #include <i386/misc_protos.h> /* panic_io_port_read() */
72 #include <i386/lapic.h>
73
74 #include <mach/exception.h>
75 #include <mach/kern_return.h>
76 #include <mach/vm_param.h>
77 #include <mach/i386/thread_status.h>
78
79 #include <vm/vm_kern.h>
80 #include <vm/vm_fault.h>
81
82 #include <kern/kern_types.h>
83 #include <kern/processor.h>
84 #include <kern/thread.h>
85 #include <kern/task.h>
86 #include <kern/sched.h>
87 #include <kern/sched_prim.h>
88 #include <kern/exception.h>
89 #include <kern/spl.h>
90 #include <kern/misc_protos.h>
91 #include <kern/debug.h>
92 #if CONFIG_TELEMETRY
93 #include <kern/telemetry.h>
94 #endif
95 #include <sys/kdebug.h>
96 #include <kperf/kperf.h>
97 #include <prng/random.h>
98
99 #include <string.h>
100
101 #include <i386/postcode.h>
102 #include <i386/mp_desc.h>
103 #include <i386/proc_reg.h>
104 #if CONFIG_MCA
105 #include <i386/machine_check.h>
106 #endif
107 #include <mach/i386/syscall_sw.h>
108
109 #include <libkern/OSDebug.h>
110 #include <i386/cpu_threads.h>
111 #include <machine/pal_routines.h>
112
113 extern void throttle_lowpri_io(int);
114 extern void kprint_state(x86_saved_state64_t *saved_state);
115
116 /*
117 * Forward declarations
118 */
119 static void user_page_fault_continue(kern_return_t kret);
120 static void panic_trap(x86_saved_state64_t *saved_state, uint32_t pl, kern_return_t fault_result);
121 static void set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip);
122
123 #if CONFIG_DTRACE
124 /* See <rdar://problem/4613924> */
125 perfCallback tempDTraceTrapHook = NULL; /* Pointer to DTrace fbt trap hook routine */
126
127 extern boolean_t dtrace_tally_fault(user_addr_t);
128 #endif
129
130 extern boolean_t pmap_smep_enabled;
131 extern boolean_t pmap_smap_enabled;
132
133 __attribute__((noreturn))
134 void
135 thread_syscall_return(
136 kern_return_t ret)
137 {
138 thread_t thr_act = current_thread();
139 boolean_t is_mach;
140 int code;
141
142 pal_register_cache_state(thr_act, DIRTY);
143
144 if (thread_is_64bit_addr(thr_act)) {
145 x86_saved_state64_t *regs;
146
147 regs = USER_REGS64(thr_act);
148
149 code = (int) (regs->rax & SYSCALL_NUMBER_MASK);
150 is_mach = (regs->rax & SYSCALL_CLASS_MASK)
151 == (SYSCALL_CLASS_MACH << SYSCALL_CLASS_SHIFT);
152 if (kdebug_enable && is_mach) {
153 /* Mach trap */
154 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
155 MACHDBG_CODE(DBG_MACH_EXCP_SC,code)|DBG_FUNC_END,
156 ret, 0, 0, 0, 0);
157 }
158 regs->rax = ret;
159 #if DEBUG
160 if (is_mach)
161 DEBUG_KPRINT_SYSCALL_MACH(
162 "thread_syscall_return: 64-bit mach ret=%u\n",
163 ret);
164 else
165 DEBUG_KPRINT_SYSCALL_UNIX(
166 "thread_syscall_return: 64-bit unix ret=%u\n",
167 ret);
168 #endif
169 } else {
170 x86_saved_state32_t *regs;
171
172 regs = USER_REGS32(thr_act);
173
174 code = ((int) regs->eax);
175 is_mach = (code < 0);
176 if (kdebug_enable && is_mach) {
177 /* Mach trap */
178 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
179 MACHDBG_CODE(DBG_MACH_EXCP_SC,-code)|DBG_FUNC_END,
180 ret, 0, 0, 0, 0);
181 }
182 regs->eax = ret;
183 #if DEBUG
184 if (is_mach)
185 DEBUG_KPRINT_SYSCALL_MACH(
186 "thread_syscall_return: 32-bit mach ret=%u\n",
187 ret);
188 else
189 DEBUG_KPRINT_SYSCALL_UNIX(
190 "thread_syscall_return: 32-bit unix ret=%u\n",
191 ret);
192 #endif
193 }
194
195 #if DEBUG || DEVELOPMENT
196 kern_allocation_name_t
197 prior __assert_only = thread_get_kernel_state(thr_act)->allocation_name;
198 assertf(prior == NULL, "thread_set_allocation_name(\"%s\") not cleared", kern_allocation_get_name(prior));
199 #endif /* DEBUG || DEVELOPMENT */
200
201 throttle_lowpri_io(1);
202
203 thread_exception_return();
204 /*NOTREACHED*/
205 }
206
207
208 static inline void
209 user_page_fault_continue(
210 kern_return_t kr)
211 {
212 thread_t thread = current_thread();
213 user_addr_t vaddr;
214
215 if (thread_is_64bit_addr(thread)) {
216 x86_saved_state64_t *uregs;
217
218 uregs = USER_REGS64(thread);
219
220 vaddr = (user_addr_t)uregs->cr2;
221 } else {
222 x86_saved_state32_t *uregs;
223
224 uregs = USER_REGS32(thread);
225
226 vaddr = uregs->cr2;
227 }
228
229
230 /* PAL debug hook */
231 pal_dbg_page_fault( thread, vaddr, kr );
232
233 i386_exception(EXC_BAD_ACCESS, kr, vaddr);
234 /*NOTREACHED*/
235 }
236
237 /*
238 * Fault recovery in copyin/copyout routines.
239 */
240 struct recovery {
241 uintptr_t fault_addr;
242 uintptr_t recover_addr;
243 };
244
245 extern struct recovery recover_table[];
246 extern struct recovery recover_table_end[];
247
248 const char * trap_type[] = {TRAP_NAMES};
249 unsigned TRAP_TYPES = sizeof(trap_type)/sizeof(trap_type[0]);
250
251 extern void PE_incoming_interrupt(int interrupt);
252
253 #if defined(__x86_64__) && DEBUG
254 void
255 kprint_state(x86_saved_state64_t *saved_state)
256 {
257 kprintf("current_cpu_datap() 0x%lx\n", (uintptr_t)current_cpu_datap());
258 kprintf("Current GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_GS_BASE));
259 kprintf("Kernel GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_KERNEL_GS_BASE));
260 kprintf("state at 0x%lx:\n", (uintptr_t) saved_state);
261
262 kprintf(" rdi 0x%llx\n", saved_state->rdi);
263 kprintf(" rsi 0x%llx\n", saved_state->rsi);
264 kprintf(" rdx 0x%llx\n", saved_state->rdx);
265 kprintf(" r10 0x%llx\n", saved_state->r10);
266 kprintf(" r8 0x%llx\n", saved_state->r8);
267 kprintf(" r9 0x%llx\n", saved_state->r9);
268
269 kprintf(" cr2 0x%llx\n", saved_state->cr2);
270 kprintf("real cr2 0x%lx\n", get_cr2());
271 kprintf(" r15 0x%llx\n", saved_state->r15);
272 kprintf(" r14 0x%llx\n", saved_state->r14);
273 kprintf(" r13 0x%llx\n", saved_state->r13);
274 kprintf(" r12 0x%llx\n", saved_state->r12);
275 kprintf(" r11 0x%llx\n", saved_state->r11);
276 kprintf(" rbp 0x%llx\n", saved_state->rbp);
277 kprintf(" rbx 0x%llx\n", saved_state->rbx);
278 kprintf(" rcx 0x%llx\n", saved_state->rcx);
279 kprintf(" rax 0x%llx\n", saved_state->rax);
280
281 kprintf(" gs 0x%x\n", saved_state->gs);
282 kprintf(" fs 0x%x\n", saved_state->fs);
283
284 kprintf(" isf.trapno 0x%x\n", saved_state->isf.trapno);
285 kprintf(" isf._pad 0x%x\n", saved_state->isf._pad);
286 kprintf(" isf.trapfn 0x%llx\n", saved_state->isf.trapfn);
287 kprintf(" isf.err 0x%llx\n", saved_state->isf.err);
288 kprintf(" isf.rip 0x%llx\n", saved_state->isf.rip);
289 kprintf(" isf.cs 0x%llx\n", saved_state->isf.cs);
290 kprintf(" isf.rflags 0x%llx\n", saved_state->isf.rflags);
291 kprintf(" isf.rsp 0x%llx\n", saved_state->isf.rsp);
292 kprintf(" isf.ss 0x%llx\n", saved_state->isf.ss);
293 }
294 #endif
295
296
297 /*
298 * Non-zero indicates latency assert is enabled and capped at valued
299 * absolute time units.
300 */
301
302 uint64_t interrupt_latency_cap = 0;
303 boolean_t ilat_assert = FALSE;
304
305 void
306 interrupt_latency_tracker_setup(void) {
307 uint32_t ilat_cap_us;
308 if (PE_parse_boot_argn("interrupt_latency_cap_us", &ilat_cap_us, sizeof(ilat_cap_us))) {
309 interrupt_latency_cap = ilat_cap_us * NSEC_PER_USEC;
310 nanoseconds_to_absolutetime(interrupt_latency_cap, &interrupt_latency_cap);
311 } else {
312 interrupt_latency_cap = LockTimeOut;
313 }
314 PE_parse_boot_argn("-interrupt_latency_assert_enable", &ilat_assert, sizeof(ilat_assert));
315 }
316
317 void interrupt_reset_latency_stats(void) {
318 uint32_t i;
319 for (i = 0; i < real_ncpus; i++) {
320 cpu_data_ptr[i]->cpu_max_observed_int_latency =
321 cpu_data_ptr[i]->cpu_max_observed_int_latency_vector = 0;
322 }
323 }
324
325 void interrupt_populate_latency_stats(char *buf, unsigned bufsize) {
326 uint32_t i, tcpu = ~0;
327 uint64_t cur_max = 0;
328
329 for (i = 0; i < real_ncpus; i++) {
330 if (cur_max < cpu_data_ptr[i]->cpu_max_observed_int_latency) {
331 cur_max = cpu_data_ptr[i]->cpu_max_observed_int_latency;
332 tcpu = i;
333 }
334 }
335
336 if (tcpu < real_ncpus)
337 snprintf(buf, bufsize, "0x%x 0x%x 0x%llx", tcpu, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency_vector, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency);
338 }
339
340 uint32_t interrupt_timer_coalescing_enabled = 1;
341 uint64_t interrupt_coalesced_timers;
342
343 /*
344 * Handle interrupts:
345 * - local APIC interrupts (IPIs, timers, etc) are handled by the kernel,
346 * - device interrupts go to the platform expert.
347 */
348 void
349 interrupt(x86_saved_state_t *state)
350 {
351 uint64_t rip;
352 uint64_t rsp;
353 int interrupt_num;
354 boolean_t user_mode = FALSE;
355 int ipl;
356 int cnum = cpu_number();
357 cpu_data_t *cdp = cpu_data_ptr[cnum];
358 int itype = DBG_INTR_TYPE_UNKNOWN;
359
360 x86_saved_state64_t *state64 = saved_state64(state);
361 rip = state64->isf.rip;
362 rsp = state64->isf.rsp;
363 interrupt_num = state64->isf.trapno;
364 if(state64->isf.cs & 0x03)
365 user_mode = TRUE;
366
367 if (cpu_data_ptr[cnum]->lcpu.package->num_idle == topoParms.nLThreadsPerPackage)
368 cpu_data_ptr[cnum]->cpu_hwIntpexits[interrupt_num]++;
369
370 if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_INTERPROCESSOR_INTERRUPT))
371 itype = DBG_INTR_TYPE_IPI;
372 else if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_TIMER_INTERRUPT))
373 itype = DBG_INTR_TYPE_TIMER;
374 else
375 itype = DBG_INTR_TYPE_OTHER;
376
377 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
378 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_START,
379 interrupt_num,
380 (user_mode ? rip : VM_KERNEL_UNSLIDE(rip)),
381 user_mode, itype, 0);
382
383 SCHED_STATS_INTERRUPT(current_processor());
384
385 #if CONFIG_TELEMETRY
386 if (telemetry_needs_record) {
387 telemetry_mark_curthread(user_mode, FALSE);
388 }
389 #endif
390
391 ipl = get_preemption_level();
392
393 /*
394 * Handle local APIC interrupts
395 * else call platform expert for devices.
396 */
397 if (!lapic_interrupt(interrupt_num, state)) {
398 PE_incoming_interrupt(interrupt_num);
399 }
400
401 if (__improbable(get_preemption_level() != ipl)) {
402 panic("Preemption level altered by interrupt vector 0x%x: initial 0x%x, final: 0x%x\n", interrupt_num, ipl, get_preemption_level());
403 }
404
405
406 if (__improbable(cdp->cpu_nested_istack)) {
407 cdp->cpu_nested_istack_events++;
408 }
409 else {
410 uint64_t ctime = mach_absolute_time();
411 uint64_t int_latency = ctime - cdp->cpu_int_event_time;
412 uint64_t esdeadline, ehdeadline;
413 /* Attempt to process deferred timers in the context of
414 * this interrupt, unless interrupt time has already exceeded
415 * TCOAL_ILAT_THRESHOLD.
416 */
417 #define TCOAL_ILAT_THRESHOLD (30000ULL)
418
419 if ((int_latency < TCOAL_ILAT_THRESHOLD) &&
420 interrupt_timer_coalescing_enabled) {
421 esdeadline = cdp->rtclock_timer.queue.earliest_soft_deadline;
422 ehdeadline = cdp->rtclock_timer.deadline;
423 if ((ctime >= esdeadline) && (ctime < ehdeadline)) {
424 interrupt_coalesced_timers++;
425 TCOAL_DEBUG(0x88880000 | DBG_FUNC_START, ctime, esdeadline, ehdeadline, interrupt_coalesced_timers, 0);
426 rtclock_intr(state);
427 TCOAL_DEBUG(0x88880000 | DBG_FUNC_END, ctime, esdeadline, interrupt_coalesced_timers, 0, 0);
428 } else {
429 TCOAL_DEBUG(0x77770000, ctime, cdp->rtclock_timer.queue.earliest_soft_deadline, cdp->rtclock_timer.deadline, interrupt_coalesced_timers, 0);
430 }
431 }
432
433 if (__improbable(ilat_assert && (int_latency > interrupt_latency_cap) && !machine_timeout_suspended())) {
434 panic("Interrupt vector 0x%x exceeded interrupt latency threshold, 0x%llx absolute time delta, prior signals: 0x%x, current signals: 0x%x", interrupt_num, int_latency, cdp->cpu_prior_signals, cdp->cpu_signals);
435 }
436
437 if (__improbable(int_latency > cdp->cpu_max_observed_int_latency)) {
438 cdp->cpu_max_observed_int_latency = int_latency;
439 cdp->cpu_max_observed_int_latency_vector = interrupt_num;
440 }
441 }
442
443 /*
444 * Having serviced the interrupt first, look at the interrupted stack depth.
445 */
446 if (!user_mode) {
447 uint64_t depth = cdp->cpu_kernel_stack
448 + sizeof(struct thread_kernel_state)
449 + sizeof(struct i386_exception_link *)
450 - rsp;
451 if (__improbable(depth > kernel_stack_depth_max)) {
452 kernel_stack_depth_max = (vm_offset_t)depth;
453 KERNEL_DEBUG_CONSTANT(
454 MACHDBG_CODE(DBG_MACH_SCHED, MACH_STACK_DEPTH),
455 (long) depth, (long) VM_KERNEL_UNSLIDE(rip), 0, 0, 0);
456 }
457 }
458
459 if (cnum == master_cpu)
460 ml_entropy_collect();
461
462 #if KPERF
463 kperf_interrupt();
464 #endif /* KPERF */
465
466 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_END,
467 interrupt_num);
468
469 assert(ml_get_interrupts_enabled() == FALSE);
470 }
471
472 static inline void
473 reset_dr7(void)
474 {
475 long dr7 = 0x400; /* magic dr7 reset value; 32 bit on i386, 64 bit on x86_64 */
476 __asm__ volatile("mov %0,%%dr7" : : "r" (dr7));
477 }
478 #if MACH_KDP
479 unsigned kdp_has_active_watchpoints = 0;
480 #define NO_WATCHPOINTS (!kdp_has_active_watchpoints)
481 #else
482 #define NO_WATCHPOINTS 1
483 #endif
484 /*
485 * Trap from kernel mode. Only page-fault errors are recoverable,
486 * and then only in special circumstances. All other errors are
487 * fatal. Return value indicates if trap was handled.
488 */
489
490 void
491 kernel_trap(
492 x86_saved_state_t *state,
493 uintptr_t *lo_spp)
494 {
495 x86_saved_state64_t *saved_state;
496 int code;
497 user_addr_t vaddr;
498 int type;
499 vm_map_t map = 0; /* protected by T_PAGE_FAULT */
500 kern_return_t result = KERN_FAILURE;
501 kern_return_t fault_result = KERN_SUCCESS;
502 thread_t thread;
503 boolean_t intr;
504 vm_prot_t prot;
505 struct recovery *rp;
506 vm_offset_t kern_ip;
507 #if NCOPY_WINDOWS > 0
508 int fault_in_copy_window = -1;
509 #endif
510 int is_user;
511 int trap_pl = get_preemption_level();
512
513 thread = current_thread();
514
515 if (__improbable(is_saved_state32(state)))
516 panic("kernel_trap(%p) with 32-bit state", state);
517 saved_state = saved_state64(state);
518
519 /* Record cpu where state was captured */
520 saved_state->isf.cpu = cpu_number();
521
522 vaddr = (user_addr_t)saved_state->cr2;
523 type = saved_state->isf.trapno;
524 code = (int)(saved_state->isf.err & 0xffff);
525 intr = (saved_state->isf.rflags & EFL_IF) != 0; /* state of ints at trap */
526 kern_ip = (vm_offset_t)saved_state->isf.rip;
527
528 is_user = (vaddr < VM_MAX_USER_PAGE_ADDRESS);
529
530 #if CONFIG_DTRACE
531 /*
532 * Is there a DTrace hook?
533 */
534 if (__improbable(tempDTraceTrapHook != NULL)) {
535 if (tempDTraceTrapHook(type, state, lo_spp, 0) == KERN_SUCCESS) {
536 /*
537 * If it succeeds, we are done...
538 */
539 return;
540 }
541 }
542 #endif /* CONFIG_DTRACE */
543
544 /*
545 * we come here with interrupts off as we don't want to recurse
546 * on preemption below. but we do want to re-enable interrupts
547 * as soon we possibly can to hold latency down
548 */
549 if (__improbable(T_PREEMPT == type)) {
550 ast_taken_kernel();
551
552 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
553 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
554 0, 0, 0, VM_KERNEL_UNSLIDE(kern_ip), 0);
555 return;
556 }
557
558 user_addr_t kd_vaddr = is_user ? vaddr : VM_KERNEL_UNSLIDE(vaddr);
559 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
560 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
561 (unsigned)(kd_vaddr >> 32), (unsigned)kd_vaddr, is_user,
562 VM_KERNEL_UNSLIDE(kern_ip), 0);
563
564
565 if (T_PAGE_FAULT == type) {
566 /*
567 * assume we're faulting in the kernel map
568 */
569 map = kernel_map;
570
571 if (__probable(thread != THREAD_NULL && thread->map != kernel_map)) {
572 #if NCOPY_WINDOWS > 0
573 vm_offset_t copy_window_base;
574 vm_offset_t kvaddr;
575 int window_index;
576
577 kvaddr = (vm_offset_t)vaddr;
578 /*
579 * must determine if fault occurred in
580 * the copy window while pre-emption is
581 * disabled for this processor so that
582 * we only need to look at the window
583 * associated with this processor
584 */
585 copy_window_base = current_cpu_datap()->cpu_copywindow_base;
586
587 if (kvaddr >= copy_window_base && kvaddr < (copy_window_base + (NBPDE * NCOPY_WINDOWS)) ) {
588
589 window_index = (int)((kvaddr - copy_window_base) / NBPDE);
590
591 if (thread->machine.copy_window[window_index].user_base != (user_addr_t)-1) {
592
593 kvaddr -= (copy_window_base + (NBPDE * window_index));
594 vaddr = thread->machine.copy_window[window_index].user_base + kvaddr;
595
596 map = thread->map;
597 fault_in_copy_window = window_index;
598 }
599 }
600 #else
601 if (__probable(vaddr < VM_MAX_USER_PAGE_ADDRESS)) {
602 /* fault occurred in userspace */
603 map = thread->map;
604
605 /* Intercept a potential Supervisor Mode Execute
606 * Protection fault. These criteria identify
607 * both NX faults and SMEP faults, but both
608 * are fatal. We avoid checking PTEs (racy).
609 * (The VM could just redrive a SMEP fault, hence
610 * the intercept).
611 */
612 if (__improbable((code == (T_PF_PROT | T_PF_EXECUTE)) &&
613 (pmap_smep_enabled) && (saved_state->isf.rip == vaddr))) {
614 goto debugger_entry;
615 }
616
617 /*
618 * Additionally check for SMAP faults...
619 * which are characterized by page-present and
620 * the AC bit unset (i.e. not from copyin/out path).
621 */
622 if (__improbable(code & T_PF_PROT &&
623 pmap_smap_enabled &&
624 (saved_state->isf.rflags & EFL_AC) == 0)) {
625 goto debugger_entry;
626 }
627
628 /*
629 * If we're not sharing cr3 with the user
630 * and we faulted in copyio,
631 * then switch cr3 here and dismiss the fault.
632 */
633 if (no_shared_cr3 &&
634 (thread->machine.specFlags&CopyIOActive) &&
635 map->pmap->pm_cr3 != get_cr3_base()) {
636 pmap_assert(current_cpu_datap()->cpu_pmap_pcid_enabled == FALSE);
637 set_cr3_raw(map->pmap->pm_cr3);
638 return;
639 }
640 if (__improbable(vaddr < PAGE_SIZE) &&
641 ((thread->machine.specFlags & CopyIOActive) == 0)) {
642 goto debugger_entry;
643 }
644 }
645 #endif
646 }
647 }
648
649 (void) ml_set_interrupts_enabled(intr);
650
651 switch (type) {
652
653 case T_NO_FPU:
654 fpnoextflt();
655 return;
656
657 case T_FPU_FAULT:
658 fpextovrflt();
659 return;
660
661 case T_FLOATING_POINT_ERROR:
662 fpexterrflt();
663 return;
664
665 case T_SSE_FLOAT_ERROR:
666 fpSSEexterrflt();
667 return;
668
669 case T_INVALID_OPCODE:
670 fpUDflt(kern_ip);
671 goto debugger_entry;
672
673 case T_DEBUG:
674 if ((saved_state->isf.rflags & EFL_TF) == 0 && NO_WATCHPOINTS)
675 {
676 /* We've somehow encountered a debug
677 * register match that does not belong
678 * to the kernel debugger.
679 * This isn't supposed to happen.
680 */
681 reset_dr7();
682 return;
683 }
684 goto debugger_entry;
685 case T_INT3:
686 goto debugger_entry;
687 case T_PAGE_FAULT:
688
689 #if CONFIG_DTRACE
690 if (thread != THREAD_NULL && thread->options & TH_OPT_DTRACE) { /* Executing under dtrace_probe? */
691 if (dtrace_tally_fault(vaddr)) { /* Should a fault under dtrace be ignored? */
692 /*
693 * DTrace has "anticipated" the possibility of this fault, and has
694 * established the suitable recovery state. Drop down now into the
695 * recovery handling code in "case T_GENERAL_PROTECTION:".
696 */
697 goto FALL_THROUGH;
698 }
699 }
700 #endif /* CONFIG_DTRACE */
701
702 prot = VM_PROT_READ;
703
704 if (code & T_PF_WRITE)
705 prot |= VM_PROT_WRITE;
706 if (code & T_PF_EXECUTE)
707 prot |= VM_PROT_EXECUTE;
708
709 fault_result = result = vm_fault(map,
710 vaddr,
711 prot,
712 FALSE, VM_KERN_MEMORY_NONE,
713 THREAD_UNINT, NULL, 0);
714
715 if (result == KERN_SUCCESS) {
716 #if NCOPY_WINDOWS > 0
717 if (fault_in_copy_window != -1) {
718 ml_set_interrupts_enabled(FALSE);
719 copy_window_fault(thread, map,
720 fault_in_copy_window);
721 (void) ml_set_interrupts_enabled(intr);
722 }
723 #endif /* NCOPY_WINDOWS > 0 */
724 return;
725 }
726 /*
727 * fall through
728 */
729 #if CONFIG_DTRACE
730 FALL_THROUGH:
731 #endif /* CONFIG_DTRACE */
732
733 case T_GENERAL_PROTECTION:
734 /*
735 * If there is a failure recovery address
736 * for this fault, go there.
737 */
738 for (rp = recover_table; rp < recover_table_end; rp++) {
739 if (kern_ip == rp->fault_addr) {
740 set_recovery_ip(saved_state, rp->recover_addr);
741 return;
742 }
743 }
744
745 /*
746 * Check thread recovery address also.
747 */
748 if (thread != THREAD_NULL && thread->recover) {
749 set_recovery_ip(saved_state, thread->recover);
750 thread->recover = 0;
751 return;
752 }
753 /*
754 * Unanticipated page-fault errors in kernel
755 * should not happen.
756 *
757 * fall through...
758 */
759 default:
760 /*
761 * Exception 15 is reserved but some chips may generate it
762 * spuriously. Seen at startup on AMD Athlon-64.
763 */
764 if (type == 15) {
765 kprintf("kernel_trap() ignoring spurious trap 15\n");
766 return;
767 }
768 debugger_entry:
769 /* Ensure that the i386_kernel_state at the base of the
770 * current thread's stack (if any) is synchronized with the
771 * context at the moment of the trap, to facilitate
772 * access through the debugger.
773 */
774 sync_iss_to_iks(state);
775 #if MACH_KDP
776 if (kdp_i386_trap(type, saved_state, result, (vm_offset_t)vaddr))
777 return;
778 #endif
779 }
780 pal_cli();
781 panic_trap(saved_state, trap_pl, fault_result);
782 /*
783 * NO RETURN
784 */
785 }
786
787 static void
788 set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip)
789 {
790 saved_state->isf.rip = ip;
791 }
792
793 static void
794 panic_trap(x86_saved_state64_t *regs, uint32_t pl, kern_return_t fault_result)
795 {
796 const char *trapname = "Unknown";
797 pal_cr_t cr0, cr2, cr3, cr4;
798 boolean_t potential_smep_fault = FALSE, potential_kernel_NX_fault = FALSE;
799 boolean_t potential_smap_fault = FALSE;
800
801 pal_get_control_registers( &cr0, &cr2, &cr3, &cr4 );
802 assert(ml_get_interrupts_enabled() == FALSE);
803 current_cpu_datap()->cpu_fatal_trap_state = regs;
804 /*
805 * Issue an I/O port read if one has been requested - this is an
806 * event logic analyzers can use as a trigger point.
807 */
808 panic_io_port_read();
809
810 kprintf("CPU %d panic trap number 0x%x, rip 0x%016llx\n",
811 cpu_number(), regs->isf.trapno, regs->isf.rip);
812 kprintf("cr0 0x%016llx cr2 0x%016llx cr3 0x%016llx cr4 0x%016llx\n",
813 cr0, cr2, cr3, cr4);
814
815 if (regs->isf.trapno < TRAP_TYPES)
816 trapname = trap_type[regs->isf.trapno];
817
818 if ((regs->isf.trapno == T_PAGE_FAULT) && (regs->isf.err == (T_PF_PROT | T_PF_EXECUTE)) && (regs->isf.rip == regs->cr2)) {
819 if (pmap_smep_enabled && (regs->isf.rip < VM_MAX_USER_PAGE_ADDRESS)) {
820 potential_smep_fault = TRUE;
821 } else if (regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
822 potential_kernel_NX_fault = TRUE;
823 }
824 } else if (pmap_smap_enabled &&
825 regs->isf.trapno == T_PAGE_FAULT &&
826 regs->isf.err & T_PF_PROT &&
827 regs->cr2 < VM_MAX_USER_PAGE_ADDRESS &&
828 regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
829 potential_smap_fault = TRUE;
830 }
831
832 #undef panic
833 panic("Kernel trap at 0x%016llx, type %d=%s, registers:\n"
834 "CR0: 0x%016llx, CR2: 0x%016llx, CR3: 0x%016llx, CR4: 0x%016llx\n"
835 "RAX: 0x%016llx, RBX: 0x%016llx, RCX: 0x%016llx, RDX: 0x%016llx\n"
836 "RSP: 0x%016llx, RBP: 0x%016llx, RSI: 0x%016llx, RDI: 0x%016llx\n"
837 "R8: 0x%016llx, R9: 0x%016llx, R10: 0x%016llx, R11: 0x%016llx\n"
838 "R12: 0x%016llx, R13: 0x%016llx, R14: 0x%016llx, R15: 0x%016llx\n"
839 "RFL: 0x%016llx, RIP: 0x%016llx, CS: 0x%016llx, SS: 0x%016llx\n"
840 "Fault CR2: 0x%016llx, Error code: 0x%016llx, Fault CPU: 0x%x%s%s%s%s, PL: %d, VF: %d\n",
841 regs->isf.rip, regs->isf.trapno, trapname,
842 cr0, cr2, cr3, cr4,
843 regs->rax, regs->rbx, regs->rcx, regs->rdx,
844 regs->isf.rsp, regs->rbp, regs->rsi, regs->rdi,
845 regs->r8, regs->r9, regs->r10, regs->r11,
846 regs->r12, regs->r13, regs->r14, regs->r15,
847 regs->isf.rflags, regs->isf.rip, regs->isf.cs & 0xFFFF,
848 regs->isf.ss & 0xFFFF,regs->cr2, regs->isf.err, regs->isf.cpu,
849 virtualized ? " VMM" : "",
850 potential_kernel_NX_fault ? " Kernel NX fault" : "",
851 potential_smep_fault ? " SMEP/User NX fault" : "",
852 potential_smap_fault ? " SMAP fault" : "",
853 pl,
854 fault_result);
855 /*
856 * This next statement is not executed,
857 * but it's needed to stop the compiler using tail call optimization
858 * for the panic call - which confuses the subsequent backtrace.
859 */
860 cr0 = 0;
861 }
862
863 #if CONFIG_DTRACE
864 extern kern_return_t dtrace_user_probe(x86_saved_state_t *);
865 #endif
866
867 #if DEBUG
868 uint32_t fsigs[2];
869 uint32_t fsigns, fsigcs;
870 #endif
871
872 /*
873 * Trap from user mode.
874 */
875 void
876 user_trap(
877 x86_saved_state_t *saved_state)
878 {
879 int exc;
880 int err;
881 mach_exception_code_t code;
882 mach_exception_subcode_t subcode;
883 int type;
884 user_addr_t vaddr;
885 vm_prot_t prot;
886 thread_t thread = current_thread();
887 kern_return_t kret;
888 user_addr_t rip;
889 unsigned long dr6 = 0; /* 32 bit for i386, 64 bit for x86_64 */
890
891 assert((is_saved_state32(saved_state) && !thread_is_64bit_addr(thread)) ||
892 (is_saved_state64(saved_state) && thread_is_64bit_addr(thread)));
893
894 if (is_saved_state64(saved_state)) {
895 x86_saved_state64_t *regs;
896
897 regs = saved_state64(saved_state);
898
899 /* Record cpu where state was captured */
900 regs->isf.cpu = cpu_number();
901
902 type = regs->isf.trapno;
903 err = (int)regs->isf.err & 0xffff;
904 vaddr = (user_addr_t)regs->cr2;
905 rip = (user_addr_t)regs->isf.rip;
906 } else {
907 x86_saved_state32_t *regs;
908
909 regs = saved_state32(saved_state);
910
911 /* Record cpu where state was captured */
912 regs->cpu = cpu_number();
913
914 type = regs->trapno;
915 err = regs->err & 0xffff;
916 vaddr = (user_addr_t)regs->cr2;
917 rip = (user_addr_t)regs->eip;
918 }
919
920 if ((type == T_DEBUG) && thread->machine.ids) {
921 unsigned long clear = 0;
922 /* Stash and clear this processor's DR6 value, in the event
923 * this was a debug register match
924 */
925 __asm__ volatile ("mov %%db6, %0" : "=r" (dr6));
926 __asm__ volatile ("mov %0, %%db6" : : "r" (clear));
927 }
928
929 pal_sti();
930
931 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
932 (MACHDBG_CODE(DBG_MACH_EXCP_UTRAP_x86, type)) | DBG_FUNC_NONE,
933 (unsigned)(vaddr>>32), (unsigned)vaddr,
934 (unsigned)(rip>>32), (unsigned)rip, 0);
935
936 code = 0;
937 subcode = 0;
938 exc = 0;
939
940 #if CONFIG_DTRACE
941 /*
942 * DTrace does not consume all user traps, only INT_3's for now.
943 * Avoid needlessly calling tempDTraceTrapHook here, and let the
944 * INT_3 case handle them.
945 */
946 #endif
947
948 DEBUG_KPRINT_SYSCALL_MASK(1,
949 "user_trap: type=0x%x(%s) err=0x%x cr2=%p rip=%p\n",
950 type, trap_type[type], err, (void *)(long) vaddr, (void *)(long) rip);
951
952 switch (type) {
953
954 case T_DIVIDE_ERROR:
955 exc = EXC_ARITHMETIC;
956 code = EXC_I386_DIV;
957 break;
958
959 case T_DEBUG:
960 {
961 pcb_t pcb;
962 /*
963 * Update the PCB with this processor's DR6 value
964 * in the event this was a debug register match.
965 */
966 pcb = THREAD_TO_PCB(thread);
967 if (pcb->ids) {
968 /*
969 * We can get and set the status register
970 * in 32-bit mode even on a 64-bit thread
971 * because the high order bits are not
972 * used on x86_64
973 */
974 if (thread_is_64bit_addr(thread)) {
975 x86_debug_state64_t *ids = pcb->ids;
976 ids->dr6 = dr6;
977 } else { /* 32 bit thread */
978 x86_debug_state32_t *ids = pcb->ids;
979 ids->dr6 = (uint32_t) dr6;
980 }
981 }
982 exc = EXC_BREAKPOINT;
983 code = EXC_I386_SGL;
984 break;
985 }
986 case T_INT3:
987 #if CONFIG_DTRACE
988 if (dtrace_user_probe(saved_state) == KERN_SUCCESS)
989 return; /* If it succeeds, we are done... */
990 #endif
991 exc = EXC_BREAKPOINT;
992 code = EXC_I386_BPT;
993 break;
994
995 case T_OVERFLOW:
996 exc = EXC_ARITHMETIC;
997 code = EXC_I386_INTO;
998 break;
999
1000 case T_OUT_OF_BOUNDS:
1001 exc = EXC_SOFTWARE;
1002 code = EXC_I386_BOUND;
1003 break;
1004
1005 case T_INVALID_OPCODE:
1006 #if !defined(RC_HIDE_XNU_J137)
1007 fpUDflt(rip); /* May return from exception directly */
1008 #endif
1009 exc = EXC_BAD_INSTRUCTION;
1010 code = EXC_I386_INVOP;
1011 break;
1012
1013 case T_NO_FPU:
1014 fpnoextflt();
1015 return;
1016
1017 case T_FPU_FAULT:
1018 fpextovrflt(); /* Propagates exception directly, doesn't return */
1019 return;
1020
1021 case T_INVALID_TSS: /* invalid TSS == iret with NT flag set */
1022 exc = EXC_BAD_INSTRUCTION;
1023 code = EXC_I386_INVTSSFLT;
1024 subcode = err;
1025 break;
1026
1027 case T_SEGMENT_NOT_PRESENT:
1028 exc = EXC_BAD_INSTRUCTION;
1029 code = EXC_I386_SEGNPFLT;
1030 subcode = err;
1031 break;
1032
1033 case T_STACK_FAULT:
1034 exc = EXC_BAD_INSTRUCTION;
1035 code = EXC_I386_STKFLT;
1036 subcode = err;
1037 break;
1038
1039 case T_GENERAL_PROTECTION:
1040 /*
1041 * There's a wide range of circumstances which generate this
1042 * class of exception. From user-space, many involve bad
1043 * addresses (such as a non-canonical 64-bit address).
1044 * So we map this to EXC_BAD_ACCESS (and thereby SIGSEGV).
1045 * The trouble is cr2 doesn't contain the faulting address;
1046 * we'd need to decode the faulting instruction to really
1047 * determine this. We'll leave that to debuggers.
1048 * However, attempted execution of privileged instructions
1049 * (e.g. cli) also generate GP faults and so we map these to
1050 * to EXC_BAD_ACCESS (and thence SIGSEGV) also - rather than
1051 * EXC_BAD_INSTRUCTION which is more accurate. We just can't
1052 * win!
1053 */
1054 exc = EXC_BAD_ACCESS;
1055 code = EXC_I386_GPFLT;
1056 subcode = err;
1057 break;
1058
1059 case T_PAGE_FAULT:
1060 {
1061 prot = VM_PROT_READ;
1062
1063 if (err & T_PF_WRITE)
1064 prot |= VM_PROT_WRITE;
1065 if (__improbable(err & T_PF_EXECUTE))
1066 prot |= VM_PROT_EXECUTE;
1067 #if DEVELOPMENT || DEBUG
1068 uint32_t fsig = 0;
1069 fsig = thread_fpsimd_hash(thread);
1070 #if DEBUG
1071 fsigs[0] = fsig;
1072 #endif
1073 #endif
1074 kret = vm_fault(thread->map,
1075 vaddr,
1076 prot, FALSE, VM_KERN_MEMORY_NONE,
1077 THREAD_ABORTSAFE, NULL, 0);
1078 #if DEVELOPMENT || DEBUG
1079 if (fsig) {
1080 uint32_t fsig2 = thread_fpsimd_hash(thread);
1081 #if DEBUG
1082 fsigcs++;
1083 fsigs[1] = fsig2;
1084 #endif
1085 if (fsig != fsig2) {
1086 panic("FP/SIMD state hash mismatch across fault thread: %p 0x%x->0x%x", thread, fsig, fsig2);
1087 }
1088 } else {
1089 #if DEBUG
1090 fsigns++;
1091 #endif
1092 }
1093 #endif
1094 if (__probable((kret == KERN_SUCCESS) || (kret == KERN_ABORTED))) {
1095 thread_exception_return();
1096 /*NOTREACHED*/
1097 }
1098
1099 user_page_fault_continue(kret);
1100 } /* NOTREACHED */
1101 break;
1102
1103 case T_SSE_FLOAT_ERROR:
1104 fpSSEexterrflt(); /* Propagates exception directly, doesn't return */
1105 return;
1106
1107
1108 case T_FLOATING_POINT_ERROR:
1109 fpexterrflt(); /* Propagates exception directly, doesn't return */
1110 return;
1111
1112 case T_DTRACE_RET:
1113 #if CONFIG_DTRACE
1114 if (dtrace_user_probe(saved_state) == KERN_SUCCESS)
1115 return; /* If it succeeds, we are done... */
1116 #endif
1117 /*
1118 * If we get an INT 0x7f when we do not expect to,
1119 * treat it as an illegal instruction
1120 */
1121 exc = EXC_BAD_INSTRUCTION;
1122 code = EXC_I386_INVOP;
1123 break;
1124
1125 default:
1126 panic("Unexpected user trap, type %d", type);
1127 return;
1128 }
1129 /* Note: Codepaths that directly return from user_trap() have pending
1130 * ASTs processed in locore
1131 */
1132 i386_exception(exc, code, subcode);
1133 /* NOTREACHED */
1134 }
1135
1136 /*
1137 * Handle exceptions for i386.
1138 *
1139 * If we are an AT bus machine, we must turn off the AST for a
1140 * delayed floating-point exception.
1141 *
1142 * If we are providing floating-point emulation, we may have
1143 * to retrieve the real register values from the floating point
1144 * emulator.
1145 */
1146 void
1147 i386_exception(
1148 int exc,
1149 mach_exception_code_t code,
1150 mach_exception_subcode_t subcode)
1151 {
1152 mach_exception_data_type_t codes[EXCEPTION_CODE_MAX];
1153
1154 DEBUG_KPRINT_SYSCALL_MACH("i386_exception: exc=%d code=0x%llx subcode=0x%llx\n",
1155 exc, code, subcode);
1156 codes[0] = code; /* new exception interface */
1157 codes[1] = subcode;
1158 exception_triage(exc, codes, 2);
1159 /*NOTREACHED*/
1160 }
1161
1162
1163 /* Synchronize a thread's x86_kernel_state (if any) with the given
1164 * x86_saved_state_t obtained from the trap/IPI handler; called in
1165 * kernel_trap() prior to entering the debugger, and when receiving
1166 * an "MP_KDP" IPI. Called with null saved_state if an incoming IPI
1167 * was detected from the kernel while spinning with interrupts masked.
1168 */
1169
1170 void
1171 sync_iss_to_iks(x86_saved_state_t *saved_state)
1172 {
1173 struct x86_kernel_state *iks = NULL;
1174 vm_offset_t kstack;
1175 boolean_t record_active_regs = FALSE;
1176
1177 /* The PAL may have a special way to sync registers */
1178 if (saved_state && saved_state->flavor == THREAD_STATE_NONE)
1179 pal_get_kern_regs( saved_state );
1180
1181 if (current_thread() != NULL &&
1182 (kstack = current_thread()->kernel_stack) != 0) {
1183 x86_saved_state64_t *regs = saved_state64(saved_state);
1184
1185 iks = STACK_IKS(kstack);
1186
1187 /* Did we take the trap/interrupt in kernel mode? */
1188 if (saved_state == NULL || /* NULL => polling in kernel */
1189 regs == USER_REGS64(current_thread()))
1190 record_active_regs = TRUE;
1191 else {
1192 iks->k_rbx = regs->rbx;
1193 iks->k_rsp = regs->isf.rsp;
1194 iks->k_rbp = regs->rbp;
1195 iks->k_r12 = regs->r12;
1196 iks->k_r13 = regs->r13;
1197 iks->k_r14 = regs->r14;
1198 iks->k_r15 = regs->r15;
1199 iks->k_rip = regs->isf.rip;
1200 }
1201 }
1202
1203 if (record_active_regs == TRUE) {
1204 /* Show the trap handler path */
1205 __asm__ volatile("movq %%rbx, %0" : "=m" (iks->k_rbx));
1206 __asm__ volatile("movq %%rsp, %0" : "=m" (iks->k_rsp));
1207 __asm__ volatile("movq %%rbp, %0" : "=m" (iks->k_rbp));
1208 __asm__ volatile("movq %%r12, %0" : "=m" (iks->k_r12));
1209 __asm__ volatile("movq %%r13, %0" : "=m" (iks->k_r13));
1210 __asm__ volatile("movq %%r14, %0" : "=m" (iks->k_r14));
1211 __asm__ volatile("movq %%r15, %0" : "=m" (iks->k_r15));
1212 /* "Current" instruction pointer */
1213 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:"
1214 : "=m" (iks->k_rip)
1215 :
1216 : "rax");
1217 }
1218 }
1219
1220 /*
1221 * This is used by the NMI interrupt handler (from mp.c) to
1222 * uncondtionally sync the trap handler context to the IKS
1223 * irrespective of whether the NMI was fielded in kernel
1224 * or user space.
1225 */
1226 void
1227 sync_iss_to_iks_unconditionally(__unused x86_saved_state_t *saved_state) {
1228 struct x86_kernel_state *iks;
1229 vm_offset_t kstack;
1230
1231 if ((kstack = current_thread()->kernel_stack) != 0) {
1232 iks = STACK_IKS(kstack);
1233 /* Display the trap handler path */
1234 __asm__ volatile("movq %%rbx, %0" : "=m" (iks->k_rbx));
1235 __asm__ volatile("movq %%rsp, %0" : "=m" (iks->k_rsp));
1236 __asm__ volatile("movq %%rbp, %0" : "=m" (iks->k_rbp));
1237 __asm__ volatile("movq %%r12, %0" : "=m" (iks->k_r12));
1238 __asm__ volatile("movq %%r13, %0" : "=m" (iks->k_r13));
1239 __asm__ volatile("movq %%r14, %0" : "=m" (iks->k_r14));
1240 __asm__ volatile("movq %%r15, %0" : "=m" (iks->k_r15));
1241 /* "Current" instruction pointer */
1242 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:" : "=m" (iks->k_rip)::"rax");
1243 }
1244 }
1245
1246 #if DEBUG
1247 #define TERI 1
1248 #endif
1249
1250 #if TERI
1251 extern void thread_exception_return_internal(void) __dead2;
1252
1253 void thread_exception_return(void) {
1254 thread_t thread = current_thread();
1255 ml_set_interrupts_enabled(FALSE);
1256 if (thread_is_64bit_addr(thread) != task_has_64Bit_addr(thread->task)) {
1257 panic("Task/thread bitness mismatch %p %p, task: %d, thread: %d", thread, thread->task, thread_is_64bit_addr(thread), task_has_64Bit_addr(thread->task));
1258 }
1259
1260 if (thread_is_64bit_addr(thread)) {
1261 if ((gdt_desc_p(USER64_CS)->access & ACC_PL_U) == 0) {
1262 panic("64-GDT mismatch %p, descriptor: %p", thread, gdt_desc_p(USER64_CS));
1263 }
1264 } else {
1265 if ((gdt_desc_p(USER_CS)->access & ACC_PL_U) == 0) {
1266 panic("32-GDT mismatch %p, descriptor: %p", thread, gdt_desc_p(USER_CS));
1267
1268 }
1269 }
1270 thread_exception_return_internal();
1271 }
1272 #endif
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