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33 * Mach Operating System
34 * Copyright (c) 1991,1990 Carnegie Mellon University
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38 * documentation is hereby granted, provided that both the copyright
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62 * Processor registers for ARM
64 #ifndef _ARM_PROC_REG_H_
65 #define _ARM_PROC_REG_H_
67 #if defined (__arm64__)
68 #include <pexpert/arm64/board_config.h>
69 #elif defined (__arm__)
70 #include <pexpert/arm/board_config.h>
74 #define __ARM_ARCH__ 7
75 #define __ARM_SUB_ARCH__ CPU_ARCH_ARMv7k
76 #define __ARM_VMSA__ 7
78 #if defined(__XNU_UP__)
82 /* For SMP kernels, force physical aperture to be mapped at PTE level so that its mappings
83 * can be updated to reflect cache attribute changes on alias mappings. This prevents
84 * prefetched physical aperture cachelines from becoming dirty in L1 due to a write to
85 * an uncached alias mapping on the same core. Subsequent uncached writes from another
86 * core may not snoop this line, and the dirty line may end up being evicted later to
87 * effectively overwrite the uncached writes from other cores. */
88 #define __ARM_PTE_PHYSMAP__ 1
90 /* __ARMA7_SMP__ controls whether we are consistent with the A7 MP_CORE spec; needed because entities other than
91 * the xnu-managed processors may need to snoop our cache operations.
93 #define __ARMA7_SMP__ 1
94 #define __ARM_COHERENT_CACHE__ 1
95 #define __ARM_L1_PTW__ 1
96 #define __ARM_DEBUG__ 7
97 #define __ARM_USER_PROTECT__ 1
98 #define __ARM_TIME_TIMEBASE_ONLY__ 1
100 #elif defined (APPLECYCLONE)
101 #define __ARM_ARCH__ 8
102 #define __ARM_VMSA__ 8
103 #define __ARM_SMP__ 1
104 #define __ARM_VFP__ 4
105 #define __ARM_COHERENT_CACHE__ 1
106 #define __ARM_COHERENT_IO__ 1
107 #define __ARM_IC_NOALIAS_ICACHE__ 1
108 #define __ARM_L1_PTW__ 1
109 #define __ARM_DEBUG__ 7
110 #define __ARM_ENABLE_SWAP__ 1
111 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
112 #define __ARM64_PMAP_SUBPAGE_L1__ 1
113 #define __ARM_KERNEL_PROTECT__ 1
115 #elif defined (APPLETYPHOON)
116 #define __ARM_ARCH__ 8
117 #define __ARM_VMSA__ 8
118 #define __ARM_SMP__ 1
119 #define __ARM_VFP__ 4
120 #define __ARM_COHERENT_CACHE__ 1
121 #define __ARM_COHERENT_IO__ 1
122 #define __ARM_IC_NOALIAS_ICACHE__ 1
123 #define __ARM_L1_PTW__ 1
124 #define __ARM_DEBUG__ 7
125 #define __ARM_ENABLE_SWAP__ 1
126 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
127 #define __ARM64_PMAP_SUBPAGE_L1__ 1
128 #define __ARM_KERNEL_PROTECT__ 1
130 #elif defined (APPLETWISTER)
131 #define __ARM_ARCH__ 8
132 #define __ARM_VMSA__ 8
133 #define __ARM_SMP__ 1
134 #define __ARM_VFP__ 4
135 #define __ARM_COHERENT_CACHE__ 1
136 #define __ARM_COHERENT_IO__ 1
137 #define __ARM_IC_NOALIAS_ICACHE__ 1
138 #define __ARM_L1_PTW__ 1
139 #define __ARM_DEBUG__ 7
140 #define __ARM_ENABLE_SWAP__ 1
141 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
142 #define __ARM_16K_PG__ 1
143 #define __ARM64_PMAP_SUBPAGE_L1__ 1
144 #define __ARM_KERNEL_PROTECT__ 1
146 #elif defined (APPLEHURRICANE)
147 #define __ARM_ARCH__ 8
148 #define __ARM_VMSA__ 8
149 #define __ARM_SMP__ 1
150 #define __ARM_VFP__ 4
151 #define __ARM_COHERENT_CACHE__ 1
152 #define __ARM_COHERENT_IO__ 1
153 #define __ARM_IC_NOALIAS_ICACHE__ 1
154 #define __ARM_L1_PTW__ 1
155 #define __ARM_DEBUG__ 7
156 #define __ARM_ENABLE_SWAP__ 1
157 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
158 #define __ARM_16K_PG__ 1
159 #define __ARM64_PMAP_SUBPAGE_L1__ 1
160 #define __ARM_KERNEL_PROTECT__ 1
161 #define __ARM_GLOBAL_SLEEP_BIT__ 1
162 #define __ARM_PAN_AVAILABLE__ 1
164 #elif defined (APPLEMONSOON)
165 #define __ARM_ARCH__ 8
166 #define __ARM_VMSA__ 8
167 #define __ARM_SMP__ 1
168 #define __ARM_AMP__ 1
169 #define __ARM_VFP__ 4
170 #define __ARM_COHERENT_CACHE__ 1
171 #define __ARM_COHERENT_IO__ 1
172 #define __ARM_IC_NOALIAS_ICACHE__ 1
173 #define __ARM_L1_PTW__ 1
174 #define __ARM_DEBUG__ 7
175 #define __ARM_ENABLE_SWAP__ 1
176 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
177 #define __ARM_16K_PG__ 1
178 #define __ARM64_PMAP_SUBPAGE_L1__ 1
179 #define __ARM_KERNEL_PROTECT__ 1
180 #define __ARM_GLOBAL_SLEEP_BIT__ 1
181 #define __ARM_PAN_AVAILABLE__ 1
182 #define __ARM_WKDM_ISA_AVAILABLE__ 1
183 #define __PLATFORM_WKDM_ALIGNMENT_MASK__ (0x3FULL)
184 #define __PLATFORM_WKDM_ALIGNMENT_BOUNDARY__ (64)
185 #define __ARM_CLUSTER_COUNT__ 2
187 #elif defined (BCM2837)
188 #define __ARM_ARCH__ 8
189 #define __ARM_VMSA__ 8
190 #define __ARM_SMP__ 1
191 #define __ARM_VFP__ 4
192 #define __ARM_COHERENT_CACHE__ 1
193 #define __ARM_L1_PTW__ 1
194 #define __ARM_DEBUG__ 7
195 #define __ARM64_PMAP_SUBPAGE_L1__ 1
197 #error processor not supported
200 #if __ARM_KERNEL_PROTECT__
202 * This feature is not currently implemented for 32-bit ARM CPU architectures.
203 * A discussion of this feature for 64-bit ARM CPU architectures can be found
204 * in the ARM64 version of this file.
207 #error __ARM_KERNEL_PROTECT__ is not supported on ARM32
209 #endif /* __ARM_KERNEL_PROTECT__ */
211 #if defined(ARM_BOARD_WFE_TIMEOUT_NS)
212 #define __ARM_ENABLE_WFE_ 1
214 #define __ARM_ENABLE_WFE_ 0
217 #define CONFIG_THREAD_GROUPS 0
220 #ifdef XNU_KERNEL_PRIVATE
223 #define ARM_VFP_DEBUG 0
233 * CPSR: Current Program Status Register
234 * SPSR: Saved Program Status Registers
236 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0
237 * +-----------------------------------------------------------+
238 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE |
239 * +-----------------------------------------------------------+
245 #define PSR_NF 0x80000000 /* Negative/Less than */
246 #define PSR_ZF 0x40000000 /* Zero */
247 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */
248 #define PSR_VF 0x10000000 /* Overflow */
249 #define PSR_QF 0x08000000 /* saturation flag (QADD ARMv5) */
252 * Modified execution mode flags
254 #define PSR_JF 0x01000000 /* Jazelle flag (BXJ ARMv5) */
255 #define PSR_EF 0x00000200 /* mixed-endian flag (SETEND ARMv6) */
256 #define PSR_AF 0x00000100 /* precise abort flag (ARMv6) */
257 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */
258 #define PSR_TFb 5 /* thumb flag (BX ARMv4T) */
263 #define PSR_IRQFb 7 /* IRQ : 0 = IRQ enable */
264 #define PSR_IRQF 0x00000080 /* IRQ : 0 = IRQ enable */
265 #define PSR_FIQF 0x00000040 /* FIQ : 0 = FIQ enable */
270 #define PSR_USER_MODE 0x00000010 /* User mode */
271 #define PSR_FIQ_MODE 0x00000011 /* FIQ mode */
272 #define PSR_IRQ_MODE 0x00000012 /* IRQ mode */
273 #define PSR_SVC_MODE 0x00000013 /* Supervisor mode */
274 #define PSR_ABT_MODE 0x00000017 /* Abort mode */
275 #define PSR_UND_MODE 0x0000001B /* Undefined mode */
277 #define PSR_MODE_MASK 0x0000001F
278 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE)
279 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE)
281 #define PSR_USERDFLT PSR_USER_MODE
282 #define PSR_USER_MASK (PSR_AF | PSR_IRQF | PSR_FIQF | PSR_MODE_MASK)
283 #define PSR_USER_SET PSR_USER_MODE
285 #define PSR_INTMASK PSR_IRQF /* Interrupt disable */
288 * FPEXC: Floating-Point Exception Register
291 #define FPEXC_EX 0x80000000 /* Exception status */
292 #define FPEXC_EX_BIT 31
293 #define FPEXC_EN 0x40000000 /* VFP : 1 = EN enable */
294 #define FPEXC_EN_BIT 30
298 * FPSCR: Floating-point Status and Control Register
301 #define FPSCR_DN 0x02000000 /* Default NaN */
302 #define FPSCR_FZ 0x01000000 /* Flush to zero */
304 #define FPSCR_DEFAULT FPSCR_DN | FPSCR_FZ
310 * IFSR: Instruction Fault Status Register
311 * DFSR: Data Fault Status Register
313 #define FSR_ALIGN 0x00000001 /* Alignment */
314 #define FSR_DEBUG 0x00000002 /* Debug (watch/break) */
315 #define FSR_ICFAULT 0x00000004 /* Fault on instruction cache maintenance */
316 #define FSR_SFAULT 0x00000005 /* Translation Section */
317 #define FSR_PFAULT 0x00000007 /* Translation Page */
318 #define FSR_SACCESS 0x00000003 /* Section access */
319 #define FSR_PACCESS 0x00000006 /* Page Access */
320 #define FSR_SDOM 0x00000009 /* Domain Section */
321 #define FSR_PDOM 0x0000000B /* Domain Page */
322 #define FSR_SPERM 0x0000000D /* Permission Section */
323 #define FSR_PPERM 0x0000000F /* Permission Page */
324 #define FSR_EXT 0x00001000 /* External (Implementation Defined Classification) */
326 #define FSR_MASK 0x0000040F /* Valid bits */
327 #define FSR_ALIGN_MASK 0x0000040D /* Valid bits to check align */
329 #define DFSR_WRITE 0x00000800 /* write data abort fault */
331 #if defined (ARMA7) || defined (APPLE_ARM64_ARCH_FAMILY) || defined (BCM2837)
333 #define TEST_FSR_VMFAULT(status) \
334 (((status) == FSR_PFAULT) \
335 || ((status) == FSR_PPERM) \
336 || ((status) == FSR_SFAULT) \
337 || ((status) == FSR_SPERM) \
338 || ((status) == FSR_ICFAULT) \
339 || ((status) == FSR_SACCESS) \
340 || ((status) == FSR_PACCESS))
342 #define TEST_FSR_TRANSLATION_FAULT(status) \
343 (((status) == FSR_SFAULT) \
344 || ((status) == FSR_PFAULT))
348 #error Incompatible CPU type configured
353 * Cache configuration
359 #define MMU_I_CLINE 5 /* cache line size as 1<<MMU_I_CLINE (32) */
362 #define MMU_CSIZE 15 /* cache size as 1<<MMU_CSIZE (32K) */
363 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
364 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
365 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
366 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
368 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
369 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
371 #define __ARM_L2CACHE__ 1
373 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<MMU_CSIZE */
374 #define L2_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
375 #define L2_NWAY 3 /* set associativity 1<<MMU_NWAY (8) */
376 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
377 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
378 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
380 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<MMU_SWAY */
381 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<MMU_NSET */
383 #elif defined (APPLECYCLONE)
386 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
389 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
390 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
391 #define MMU_NWAY 1 /* set associativity 1<<MMU_NWAY (2) */
392 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
393 #define MMU_I7WAY 31 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
394 #define MMU_I9WAY 31 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
396 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
397 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
399 #define __ARM_L2CACHE__ 1
401 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
402 #define L2_CLINE 6 /* cache line size as 1<<L2_CLINE (64) */
403 #define L2_NWAY 3 /* set associativity 1<<L2_NWAY (8) */
404 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
405 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<L2_I7WAY */
406 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<L2_I9WAY */
408 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
409 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
411 #elif defined (APPLETYPHOON)
414 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
417 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
418 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
419 #define MMU_NWAY 1 /* set associativity 1<<MMU_NWAY (2) */
420 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
421 #define MMU_I7WAY 31 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
422 #define MMU_I9WAY 31 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
424 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
425 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
427 #define __ARM_L2CACHE__ 1
429 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
430 #define L2_CLINE 6 /* cache line size as 1<<L2_CLINE (64) */
431 #define L2_NWAY 3 /* set associativity 1<<L2_NWAY (8) */
432 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
433 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<L2_I7WAY */
434 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<L2_I9WAY */
436 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
437 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
439 #elif defined (APPLETWISTER)
442 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
445 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
446 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
447 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
448 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
449 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
450 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
452 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
453 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
456 #define __ARM_L2CACHE__ 1
459 * For reasons discussed in the platform expert code, we round the reported
460 * L2 size to 4MB, and adjust the other parameters accordingly.
462 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
463 #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */
464 #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */
465 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
466 #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */
467 #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */
469 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
470 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
472 #elif defined (APPLEHURRICANE)
475 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
478 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
479 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
480 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
481 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
482 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
483 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
485 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
486 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
489 #define __ARM_L2CACHE__ 1
492 * For reasons discussed in the platform expert code, we round the reported
493 * L2 size to 4MB, and adjust the other parameters accordingly.
495 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
496 #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */
497 #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */
498 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
499 #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */
500 #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */
502 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
503 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
505 #elif defined (APPLEMONSOON)
507 /* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */
508 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
510 /* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */
511 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
512 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
513 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
514 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
515 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
516 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
518 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
519 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
522 #define __ARM_L2CACHE__ 1
525 * LLC (Monsoon L2, Mistral L3): 8MB, 128-byte lines, 16-way.
526 * L2E (Mistral L2): 1MB, 64-byte lines, 8-way.
528 * TODO: Our L2 cahes have different line sizes. I begin to suspect
529 * this may be a problem.
531 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
532 #define L2_CLINE 7 /* cache line size as 1<<L2_CLINE (128) */
533 #define L2_NWAY 4 /* set associativity as 1<<L2_NWAY (16) */
534 #define L2_I7SET 6 /* TODO: cp15 c7 set incrementer 1<<L2_I7SET */
535 #define L2_I7WAY 28 /* TODO: cp15 c7 way incrementer 1<<L2_I7WAY */
536 #define L2_I9WAY 28 /* TODO: cp15 c9 way incremenber 1<<L2_I9WAY */
538 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
539 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
541 #elif defined (BCM2837) /* Raspberry Pi 3 */
543 /* I-Cache. We don't have detailed spec so we just follow the ARM technical reference. */
544 #define MMU_I_CLINE 6
555 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY)
556 #define MMU_NSET (MMU_SWAY - MMU_CLINE)
558 #define __ARM_L2CACHE__ 1
560 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__
566 #define L2_SWAY (L2_CSIZE - L2_NWAY)
567 #define L2_NSET (L2_SWAY - L2_CLINE)
570 #error processor not supported
574 #if (__ARM_VMSA__ <= 7)
577 * SCTLR: System Control Register
580 * System Control Register (SCTLR)
582 * 31 30 29 28 27 25 24 22 21 20 19 17 15 14 13 12 11 10 5 2 1 0
583 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
584 * |0|TE|AFE|TRE|NMFI|0|EE|VE|11|FI|UWXN|WXN|1|HA|1|0|RR| V| I| Z|SW|000|1|C15BEN|11|C|A|M|
585 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
587 * TE Thumb Exception enable
588 * AFE Access flag enable
589 * TRE TEX remap enable
590 * NMFI Non-maskable FIQ (NMFI) support
591 * EE Exception Endianness
592 * VE Interrupt Vectors Enable
593 * FI Fast interrupts configuration enable
595 * UWXN Unprivileged write permission implies PL1 XN
596 * WXN Write permission implies XN
597 * HA Hardware Access flag enable
598 * RR Round Robin select
599 * V High exception vectors
600 * I Instruction cache enable
601 * Z Branch prediction enable
603 * C15BEN CP15 barrier enable
605 * A Alignment check enable
609 #define SCTLR_RESERVED 0x82DD8394
611 #define SCTLR_ENABLE 0x00000001 /* MMU enable */
612 #define SCTLR_ALIGN 0x00000002 /* Alignment check enable */
613 #define SCTLR_DCACHE 0x00000004 /* Data or Unified Cache enable */
614 #define SCTLR_BEN 0x00000040 /* CP15 barrier enable */
615 #define SCTLR_SW 0x00000400 /* SWP/SWPB Enable */
616 #define SCTLR_PREDIC 0x00000800 /* Branch prediction enable */
617 #define SCTLR_ICACHE 0x00001000 /* Instruction cache enabled. */
618 #define SCTLR_HIGHVEC 0x00002000 /* Vector table at 0xffff0000 */
619 #define SCTLR_RROBIN 0x00004000 /* Round Robin replacement */
620 #define SCTLR_HA 0x00020000 /* Hardware Access flag enable */
621 #define SCTLR_NMFI 0x08000000 /* Non-maskable FIQ */
622 #define SCTLR_TRE 0x10000000 /* TEX remap enable */
623 #define SCTLR_AFE 0x20000000 /* Access flag enable */
624 #define SCTLR_TE 0x40000000 /* Thumb Exception enable */
626 #define SCTLR_DEFAULT (SCTLR_AFE|SCTLR_TRE|SCTLR_HIGHVEC|SCTLR_ICACHE|SCTLR_PREDIC|SCTLR_DCACHE|SCTLR_ENABLE)
630 * PRRR: Primary Region Remap Register
632 * 31 24 20 19 18 17 16 0
633 * +---------------------------------------------------------------+
634 * | NOSn | Res |NS1|NS0|DS1|DS0| TRn |
635 * +---------------------------------------------------------------+
638 #define PRRR_NS1 0x00080000
639 #define PRRR_NS0 0x00040000
640 #define PRRR_DS1 0x00020000
641 #define PRRR_DS0 0x00010000
642 #define PRRR_NOSn_ISH(region) (0x1<<((region)+24))
645 #define PRRR_SETUP (0x1F08022A)
647 #error processor not supported
651 * NMRR, Normal Memory Remap Register
653 * 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
654 * +---------------------------------------------------------------+
655 * |OR7|OR6|OR5|OR4|OR3|OR2|OR1|OR0|IR7|IR6|IR5|IR4|IR3|IR2|IR1|IR0|
656 * +---------------------------------------------------------------+
659 #define NMRR_DISABLED 0x0 /* Non-cacheable */
660 #define NMRR_WRITEBACK 0x1 /* Write-Back, Write-Allocate */
661 #define NMRR_WRITETHRU 0x2 /* Write-Through, no Write-Allocate */
662 #define NMRR_WRITEBACKNO 0x3 /* Write-Back, no Write-Allocate */
665 #define NMRR_SETUP (0x01210121)
667 #error processor not supported
671 * TTBR: Translation Table Base Register
675 #define TTBR_IRGN_DISBALED 0x00000000 /* inner non-cacheable */
676 #define TTBR_IRGN_WRITEBACK 0x00000040 /* inner write back and allocate */
677 #define TTBR_IRGN_WRITETHRU 0x00000001 /* inner write thru */
678 #define TTBR_IRGN_WRITEBACKNO 0x00000041 /* inner write back no allocate */
680 #define TTBR_RGN_DISBALED 0x00000000 /* outer non-cacheable */
681 #define TTBR_RGN_WRITEBACK 0x00000008 /* outer write back and allocate */
682 #define TTBR_RGN_WRITETHRU 0x00000010 /* outer write thru outer cache */
683 #define TTBR_RGN_WRITEBACKNO 0x00000018 /* outer write back no allocate */
685 #define TTBR_SHARED 0x00000002 /* Shareable memory atribute */
686 #define TTBR_SHARED_NOTOUTER 0x00000020 /* Outer not shareable memory atribute */
689 #define TTBR_SETUP (TTBR_RGN_WRITEBACK|TTBR_IRGN_WRITEBACK|TTBR_SHARED)
691 #error processor not supported
695 * TTBCR: Translation Table Base Control register
702 * If N=0, always use translation table base register 0. Otherwise, if
703 * bits [31:32-N] of the address are all zero use base register 0. Otherwise,
704 * use base register 1.
706 * Reading from this register also returns the page table boundary for TTB0.
707 * Writing to it updates the boundary for TTB0. (0=16KB, 1=8KB, 2=4KB, etc...)
710 #define TTBCR_N_1GB_TTB0 0x2 /* 1 GB TTB0, 3GB TTB1 */
711 #define TTBCR_N_2GB_TTB0 0x1 /* 2 GB TTB0, 2GB TTB1 */
712 #define TTBCR_N_4GB_TTB0 0x0 /* 4 GB TTB0 */
713 #define TTBCR_N_MASK 0x3
720 #define ARM_PGSHIFT 12
721 #define ARM_PGBYTES (1 << ARM_PGSHIFT)
722 #define ARM_PGMASK (ARM_PGBYTES-1)
725 * DACR: Domain Access Control register
728 #define DAC_FAULT 0x0 /* invalid domain - everyone loses */
729 #define DAC_CLIENT 0x1 /* client domain - use AP bits */
730 #define DAC_RESERVE 0x2 /* reserved domain - undefined */
731 #define DAC_MANAGER 0x3 /* manager domain - all access */
732 #define DACR_SET(dom, x) ((x)<<((dom)<<1))
735 #define ARM_DOM_DEFAULT 0 /* domain that forces AP use */
736 #define ARM_DAC_SETUP 0x1
739 * ARM 2-level Page Table support
743 * Memory Attribute Index
745 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled */
746 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes */
747 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled */
748 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer */
749 #define CACHE_ATTRINDX_INNERWRITEBACK 0x4 /* inner cache enabled, buffer enabled, write allocate */
750 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE
751 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK
755 * Access protection bit values
757 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */
758 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */
759 #define AP_RONA 0x2 /* priv=read-only , user=no-access */
760 #define AP_RORO 0x3 /* priv=read-only , user=read-only */
763 * L1 Translation table
765 * Each translation table is up to 16KB
766 * 4096 32-bit entries of 1MB of address space.
769 #define ARM_TT_L1_SIZE 0x00100000 /* size of area covered by a tte */
770 #define ARM_TT_L1_OFFMASK 0x000FFFFF /* offset within an L1 entry */
771 #define ARM_TT_L1_TABLE_OFFMASK 0x000FFFFF /* offset within an L1 entry */
772 #define ARM_TT_L1_BLOCK_OFFMASK 0x000FFFFF /* offset within an L1 entry */
773 #define ARM_TT_L1_SUPER_OFFMASK 0x00FFFFFF /* offset within an L1 entry */
774 #define ARM_TT_L1_SHIFT 20 /* page descriptor shift */
775 #define ARM_TT_L1_INDEX_MASK 0xfff00000 /* mask for getting index in L1 table from virtual address */
777 #define ARM_TT_L1_PT_SIZE (4 * ARM_TT_L1_SIZE) /* 4 L1 table entries required to consume 1 L2 pagetable page */
778 #define ARM_TT_L1_PT_OFFMASK (ARM_TT_L1_PT_SIZE - 1)
781 * L2 Translation table
783 * Each translation table is up to 1KB
784 * 4096 32-bit entries of 1MB (2^30) of address space.
787 #define ARM_TT_L2_SIZE 0x00001000 /* size of area covered by a tte */
788 #define ARM_TT_L2_OFFMASK 0x00000FFF /* offset within an L2 entry */
789 #define ARM_TT_L2_SHIFT 12 /* page descriptor shift */
790 #define ARM_TT_L2_INDEX_MASK 0x000ff000 /* mask for getting index in L2 table from virtual address */
793 * Convenience definitions for:
794 * ARM_TT_LEAF: The last level of the configured page table format.
795 * ARM_TT_TWIG: The second to last level of the configured page table format.
796 * ARM_TT_ROOT: The first level of the configured page table format.
798 * My apologies to any botanists who may be reading this.
800 #define ARM_TT_LEAF_SIZE ARM_TT_L2_SIZE
801 #define ARM_TT_LEAF_OFFMASK ARM_TT_L2_OFFMASK
802 #define ARM_TT_LEAF_SHIFT ARM_TT_L2_SHIFT
803 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L2_INDEX_MASK
805 #define ARM_TT_TWIG_SIZE ARM_TT_L1_SIZE
806 #define ARM_TT_TWIG_OFFMASK ARM_TT_L1_OFFMASK
807 #define ARM_TT_TWIG_SHIFT ARM_TT_L1_SHIFT
808 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L1_INDEX_MASK
810 #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE
811 #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK
812 #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT
813 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK
816 * Level 1 Translation Table Entry
821 * +----------------------+-+----+--+--+--+
822 * | page table base addr | |dom |XN|00|01|
823 * +----------------------+-+----+--+--+--+
825 * direct (1MB) section entry
827 * 31 20 18 15 12 10 9 8 5 4 2 0
828 * +------------+--+-+-+-+---+--+-+----+--+--+--+
829 * | base addr |00|G|S|A|TEX|AP| |dom |XN|CB|10|
830 * +------------+--+-+-+-+---+--+-+----+--+--+--+
832 * super (16MB) section entry
834 * 31 24 23 18 15 12 10 9 8 5 4 2 0
835 * +---------+------+-+-+-+---+--+-+----+--+--+--+
836 * |base addr|000001|G|S|A|TEX|AP| |dom |XN|CB|10|
837 * +---------+------+-+-+-+---+--+-+----+--+--+--+
840 * 'G' is the notGlobal bit
841 * 'S' is the shared bit
842 * 'A' in the access permission extension (APX) bit
843 * 'TEX' remap register control bits
844 * 'AP' is the access protection
845 * 'dom' is the domain for the translation
846 * 'XN' is the eXecute Never bit
847 * 'CB' is the cache/buffer attribute
850 #define ARM_TTE_EMPTY 0x00000000 /* unasigned entry */
852 #define ARM_TTE_TYPE_FAULT 0x00000000 /* fault entry type */
853 #define ARM_TTE_TYPE_TABLE 0x00000001 /* page table type */
854 #define ARM_TTE_TYPE_BLOCK 0x00000002 /* section entry type */
855 #define ARM_TTE_TYPE_MASK 0x00000003 /* mask for extracting the type */
857 #define ARM_TTE_BLOCK_NGSHIFT 17
858 #define ARM_TTE_BLOCK_NG_MASK 0x00020000 /* mask to determine notGlobal bit */
859 #define ARM_TTE_BLOCK_NG 0x00020000 /* value for a per-process mapping */
861 #define ARM_TTE_BLOCK_SHSHIFT 16
862 #define ARM_TTE_BLOCK_SH_MASK 0x00010000 /* shared (SMP) mapping mask */
863 #define ARM_TTE_BLOCK_SH 0x00010000 /* shared (SMP) mapping */
865 #define ARM_TTE_BLOCK_CBSHIFT 2
866 #define ARM_TTE_BLOCK_CB(x) ((x) << ARM_TTE_BLOCK_CBSHIFT)
867 #define ARM_TTE_BLOCK_CB_MASK (3<< ARM_TTE_BLOCK_CBSHIFT)
869 #define ARM_TTE_BLOCK_AP0SHIFT 10
870 #define ARM_TTE_BLOCK_AP0 (1<<ARM_TTE_BLOCK_AP0SHIFT)
871 #define ARM_TTE_BLOCK_AP0_MASK (1<<ARM_TTE_BLOCK_AP0SHIFT)
873 #define ARM_TTE_BLOCK_AP1SHIFT 11
874 #define ARM_TTE_BLOCK_AP1 (1<<ARM_TTE_BLOCK_AP1SHIFT)
875 #define ARM_TTE_BLOCK_AP1_MASK (1<<ARM_TTE_BLOCK_AP1SHIFT)
877 #define ARM_TTE_BLOCK_AP2SHIFT 15
878 #define ARM_TTE_BLOCK_AP2 (1<<ARM_TTE_BLOCK_AP2SHIFT)
879 #define ARM_TTE_BLOCK_AP2_MASK (1<<ARM_TTE_BLOCK_AP2SHIFT)
882 /* access protections */
883 #define ARM_TTE_BLOCK_AP(ap) ((((ap)&0x1)<<ARM_TTE_BLOCK_AP1SHIFT) \
884 | ((((ap)>>1)&0x1)<<ARM_TTE_BLOCK_AP2SHIFT))
886 /* mask access protections */
887 #define ARM_TTE_BLOCK_APMASK (ARM_TTE_BLOCK_AP1_MASK \
888 | ARM_TTE_BLOCK_AP2_MASK)
890 #define ARM_TTE_BLOCK_AF ARM_TTE_BLOCK_AP0 /* value for access */
891 #define ARM_TTE_BLOCK_AFMASK ARM_TTE_BLOCK_AP0_MASK /* access mask */
893 #define ARM_TTE_TABLE_MASK 0xFFFFFC00 /* mask for a L2 page table entry */
894 #define ARM_TTE_TABLE_SHIFT 10 /* shift for L2 page table phys address */
896 #define ARM_TTE_BLOCK_L1_MASK 0xFFF00000 /* mask to extract phys address from L1 section entry */
897 #define ARM_TTE_BLOCK_L1_SHIFT 20 /* shift for 1MB section phys address */
899 #define ARM_TTE_SUPER_L1_MASK 0xFF000000 /* mask to extract phys address from L1 super entry */
900 #define ARM_TTE_SUPER_L1_SHIFT 24 /* shift for 16MB section phys address */
902 #define ARM_TTE_BLOCK_SUPER 0x00040000 /* make section a 16MB section */
903 #define ARM_TTE_BLOCK_SUPER_MASK 0x00F40000 /* make section a 16MB section */
905 #define ARM_TTE_BLOCK_NXSHIFT 4
906 #define ARM_TTE_BLOCK_NX 0x00000010 /* section is no execute */
907 #define ARM_TTE_BLOCK_NX_MASK 0x00000010 /* mask for extracting no execute bit */
908 #define ARM_TTE_BLOCK_PNX ARM_TTE_BLOCK_NX
910 #define ARM_TTE_BLOCK_TEX0SHIFT 12
911 #define ARM_TTE_BLOCK_TEX0 (1<<ARM_TTE_BLOCK_TEX0SHIFT)
912 #define ARM_TTE_BLOCK_TEX0_MASK (1<<ARM_TTE_BLOCK_TEX0SHIFT)
914 #define ARM_TTE_BLOCK_TEX1SHIFT 13
915 #define ARM_TTE_BLOCK_TEX1 (1<<ARM_TTE_BLOCK_TEX1SHIFT)
916 #define ARM_TTE_BLOCK_TEX1_MASK (1<<ARM_TTE_BLOCK_TEX1SHIFT)
918 #define ARM_TTE_BLOCK_TEX2SHIFT 14
919 #define ARM_TTE_BLOCK_TEX2 (1<<ARM_TTE_BLOCK_TEX2SHIFT)
920 #define ARM_TTE_BLOCK_TEX2_MASK (1<<ARM_TTE_BLOCK_TEX2SHIFT)
923 /* mask memory attributes index */
924 #define ARM_TTE_BLOCK_ATTRINDX(i) ((((i)&0x3)<<ARM_TTE_BLOCK_CBSHIFT) \
925 | ((((i)>>2)&0x1)<<ARM_TTE_BLOCK_TEX0SHIFT))
927 /* mask memory attributes index */
928 #define ARM_TTE_BLOCK_ATTRINDXMASK (ARM_TTE_BLOCK_CB_MASK \
929 | ARM_TTE_BLOCK_TEX0_MASK)
933 * Level 2 Page table entries
935 * The following page table entry types are possible:
939 * +----------------------------------------+--+
941 * +----------------------------------------+--+
943 * large (64KB) page entry
944 * 31 16 15 12 9 6 4 3 2 0
945 * +----------------+--+---+-+-+-+---+--+-+-+--+
946 * | base phys addr |XN|TEX|G|S|A|000|AP|C|B|01|
947 * +----------------+--+---+-+-+-+---+--+-+-+--+
949 * small (4KB) page entry
950 * 31 12 9 6 4 3 2 1 0
951 * +-----------------------+-+-+-+---+--+-+-+-+--+
952 * | base phys addr |G|S|A|TEX|AP|C|B|1|XN|
953 * +-----------------------+-+-+-+---+--+-+-+-+--+
956 * 'XN' is the eXecute Never bit
957 * 'G' is the notGlobal (process-specific) bit
958 * 'S' is the shared bit
959 * 'A' in the access permission extension (ATX) bit
960 * 'TEX' remap register control bits
961 * 'AP' is the access protection
962 * 'dom' is the domain for the translation
963 * 'C' is the cache attribute
964 * 'B' is the write buffer attribute
967 #define PTE_SHIFT 2 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */
968 #define PTE_PGENTRIES (1024 >> PTE_SHIFT) /* number of ptes per page */
970 #define ARM_PTE_EMPTY 0x00000000 /* unasigned - invalid entry */
972 /* markers for (invalid) PTE for a page sent to compressor */
973 #define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */
974 #define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */
975 #define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT)
976 #define ARM_PTE_IS_COMPRESSED(x) \
977 ((((x) & 0x3) == 0) && /* PTE is not valid... */ \
978 ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \
979 ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \
980 (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \
981 &(x), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
983 #define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */
984 #define ARM_PTE_TYPE 0x00000002 /* small page entry type */
985 #define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */
987 #define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */
988 #define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */
990 #define ARM_PTE_SHSHIFT 10
991 #define ARM_PTE_SHMASK 0x00000400 /* shared (SMP) mapping mask */
992 #define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */
994 #define ARM_PTE_CBSHIFT 2
995 #define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT)
996 #define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT)
998 #define ARM_PTE_AP0SHIFT 4
999 #define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT)
1000 #define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT)
1002 #define ARM_PTE_AP1SHIFT 5
1003 #define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT)
1004 #define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT)
1006 #define ARM_PTE_AP2SHIFT 9
1007 #define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT)
1008 #define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT)
1010 /* access protections */
1011 #define ARM_PTE_AP(ap) ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) \
1012 | ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT))
1014 /* mask access protections */
1015 #define ARM_PTE_APMASK (ARM_PTE_AP1_MASK \
1018 #define ARM_PTE_AF ARM_PTE_AP0 /* value for access */
1019 #define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */
1021 #define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */
1022 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
1024 #define ARM_PTE_NXSHIFT 0
1025 #define ARM_PTE_NX 0x00000001 /* small page no execute */
1026 #define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT)
1028 #define ARM_PTE_PNXSHIFT 0
1029 #define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */
1030 #define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT)
1032 #define ARM_PTE_TEX0SHIFT 6
1033 #define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT)
1034 #define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT)
1036 #define ARM_PTE_TEX1SHIFT 7
1037 #define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT)
1038 #define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT)
1040 #define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT
1041 #define ARM_PTE_WRITEABLE ARM_PTE_TEX1
1042 #define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK
1044 #define ARM_PTE_TEX2SHIFT 8
1045 #define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT)
1046 #define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT)
1048 #define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT
1049 #define ARM_PTE_WIRED ARM_PTE_TEX2
1050 #define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK
1052 /* mask memory attributes index */
1053 #define ARM_PTE_ATTRINDX(indx) ((((indx)&0x3)<<ARM_PTE_CBSHIFT) \
1054 | ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT))
1056 /* mask memory attributes index */
1057 #define ARM_PTE_ATTRINDXMASK (ARM_PTE_CB_MASK \
1058 | ARM_PTE_TEX0_MASK)
1060 #define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */
1061 #define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */
1062 #define ARM_SECTION_SIZE (1024*1024) /* 1MB */
1063 #define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */
1068 * Format of the Debug Status and Control Register (DBGDSCR)
1070 #define ARM_DBGDSCR_RXFULL (1 << 30)
1071 #define ARM_DBGDSCR_TXFULL (1 << 29)
1072 #define ARM_DBGDSCR_RXFULL_1 (1 << 27)
1073 #define ARM_DBGDSCR_TXFULL_1 (1 << 26)
1074 #define ARM_DBGDSCR_PIPEADV (1 << 25)
1075 #define ARM_DBGDSCR_INSTRCOMPL_1 (1 << 24)
1076 #define ARM_DBGDSCR_EXTDCCMODE_MASK (3 << 20)
1077 #define ARM_DBGDSCR_EXTDCCMODE_NONBLOCKING (0 << 20)
1078 #define ARM_DBGDSCR_EXTDCCMODE_STALL (1 << 20)
1079 #define ARM_DBGDSCR_EXTDCCMODE_FAST (1 << 20)
1080 #define ARM_DBGDSCR_ADADISCARD (1 << 19)
1081 #define ARM_DBGDSCR_NS (1 << 18)
1082 #define ARM_DBGDSCR_SPNIDDIS (1 << 17)
1083 #define ARM_DBGDSCR_SPIDDIS (1 << 16)
1084 #define ARM_DBGDSCR_MDBGEN (1 << 15)
1085 #define ARM_DBGDSCR_HDBGEN (1 << 14)
1086 #define ARM_DBGDSCR_ITREN (1 << 13)
1087 #define ARM_DBGDSCR_UDCCDIS (1 << 12)
1088 #define ARM_DBGDSCR_INTDIS (1 << 11)
1089 #define ARM_DBGDSCR_DBGACK (1 << 10)
1090 #define ARM_DBGDSCR_DBGNOPWRDWN (1 << 9)
1091 #define ARM_DBGDSCR_UND_1 (1 << 8)
1092 #define ARM_DBGDSCR_ADABORT_1 (1 << 7)
1093 #define ARM_DBGDSCR_SDABORT_1 (1 << 6)
1094 #define ARM_DBGDSCR_MOE_MASK (15 << 2)
1095 #define ARM_DBGDSCR_MOE_HALT_REQUEST (0 << 2)
1096 #define ARM_DBGDSCR_MOE_BREAKPOINT (1 << 2)
1097 #define ARM_DBGDSCR_MOE_ASYNC_WATCHPOINT (2 << 2)
1098 #define ARM_DBGDSCR_MOE_BKPT_INSTRUCTION (3 << 2)
1099 #define ARM_DBGDSCR_MOE_EXT_DEBUG_REQ (4 << 2)
1100 #define ARM_DBGDSCR_MOE_VECTOR_CATCH (5 << 2)
1101 #define ARM_DBGDSCR_MOE_DSIDE_ABORT (6 << 2)
1102 #define ARM_DBGDSCR_MOE_ISIDE_ABORT (7 << 2)
1103 #define ARM_DBGDSCR_MOE_OS_UNLOCK_CATCH (8 << 2)
1104 #define ARM_DBGDSCR_MOE_SYNC_WATCHPOINT (10 << 2)
1106 #define ARM_DBGDSCR_RESTARTED (1 << 1)
1107 #define ARM_DBGDSCR_HALTED (1 << 0)
1110 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers
1111 * Using ARMv7 names; ARMv6 and ARMv6.1 are bit-compatible
1113 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */
1114 #define ARM_DBGBVR_CONTEXTID_MASK 0xFFFFFFFF /* BVR only */
1116 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */
1117 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */
1118 #define ARM_DBGBCR_MATCH_MATCH (0 << 22)
1119 #define ARM_DBGBCR_MATCH_MISMATCH (1 << 22)
1120 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */
1121 #define ARM_DBGBCR_TYPE_IVA (0 << 21)
1122 #define ARM_DBGBCR_TYPE_CONTEXTID (1 << 21)
1123 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */
1124 #define ARM_DBG_CR_LINKED_LINKED (1 << 20)
1125 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20)
1126 #define ARM_DBG_CR_LINKED_BRP_MASK 0x000F0000 /* BCR & WCR */
1127 #define ARM_DBG_CR_SECURITY_STATE_MASK (3 << 14) /* BCR & WCR */
1128 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14)
1129 #define ARM_DBG_CR_SECURITY_STATE_NONSECURE (1 << 14)
1130 #define ARM_DBG_CR_SECURITY_STATE_SECURE (2 << 14)
1131 #define ARM_DBG_CR_HIGHER_MODE_MASK (1 << 13) /* BCR & WCR */
1132 #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13)
1133 #define ARM_DBG_CR_HIGHER_MODE_DISABLE (0 << 13)
1134 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */
1135 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */
1136 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */
1137 #define ARM_DBCWCR_ACCESS_CONTROL_LOAD (1 << 3)
1138 #define ARM_DBCWCR_ACCESS_CONTROL_STORE (2 << 3)
1139 #define ARM_DBCWCR_ACCESS_CONTROL_ANY (3 << 3)
1140 #define ARM_DBG_CR_MODE_CONTROL_MASK (3 << 1) /* BCR & WCR */
1141 #define ARM_DBG_CR_MODE_CONTROL_U_S_S (0 << 1) /* BCR only */
1142 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */
1143 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */
1144 #define ARM_DBG_CR_MODE_CONTROL_ANY (3 << 1) /* BCR & WCR */
1145 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */
1146 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0)
1147 #define ARM_DBG_CR_ENABLE_DISABLE (0 << 0)
1150 * Format of the Device Power-down and Reset Status Register (DBGPRSR)
1152 #define ARM_DBGPRSR_STICKY_RESET_STATUS (1 << 3)
1153 #define ARM_DBGPRSR_RESET_STATUS (1 << 2)
1154 #define ARM_DBGPRSR_STICKY_POWERDOWN_STATUS (1 << 1)
1155 #define ARM_DBGPRSR_POWERUP_STATUS (1 << 0)
1158 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR)
1160 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55
1162 /* ARMv7 Debug register map */
1163 #define ARM_DEBUG_OFFSET_DBGDIDR (0x000)
1164 #define ARM_DEBUG_OFFSET_DBGWFAR (0x018)
1165 #define ARM_DEBUG_OFFSET_DBGVCR (0x01C)
1166 #define ARM_DEBUG_OFFSET_DBGECR (0x024)
1167 #define ARM_DEBUG_OFFSET_DBGDSCCR (0x028)
1168 #define ARM_DEBUG_OFFSET_DBGDSMCR (0x02C)
1169 #define ARM_DEBUG_OFFSET_DBGDTRRX (0x080)
1170 #define ARM_DEBUG_OFFSET_DBGITR (0x084) /* Write-only */
1171 #define ARM_DEBUG_OFFSET_DBGPCSR (0x084) /* Read-only */
1172 #define ARM_DEBUG_OFFSET_DBGDSCR (0x088)
1173 #define ARM_DEBUG_OFFSET_DBGDTRTX (0x08C)
1174 #define ARM_DEBUG_OFFSET_DBGDRCR (0x090)
1175 #define ARM_DEBUG_OFFSET_DBGBVR (0x100) /* 0x100 - 0x13C */
1176 #define ARM_DEBUG_OFFSET_DBGBCR (0x140) /* 0x140 - 0x17C */
1177 #define ARM_DEBUG_OFFSET_DBGWVR (0x180) /* 0x180 - 0x1BC */
1178 #define ARM_DEBUG_OFFSET_DBGWCR (0x1C0) /* 0x1C0 - 0x1FC */
1179 #define ARM_DEBUG_OFFSET_DBGOSLAR (0x300)
1180 #define ARM_DEBUG_OFFSET_DBGOSLSR (0x304)
1181 #define ARM_DEBUG_OFFSET_DBGOSSRR (0x308)
1182 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310)
1183 #define ARM_DEBUG_OFFSET_DBGPRSR (0x314)
1184 #define ARM_DEBUG_OFFSET_DBGITCTRL (0xF00)
1185 #define ARM_DEBUG_OFFSET_DBGCLAIMSET (0xFA0)
1186 #define ARM_DEBUG_OFFSET_DBGCLAIMCLR (0xFA4)
1187 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0)
1188 #define ARM_DEBUG_OFFSET_DBGLSR (0xFB4)
1189 #define ARM_DEBUG_OFFSET_DBGAUTHSTATUS (0xFB8)
1190 #define ARM_DEBUG_OFFSET_DBGDEVID (0xFC8)
1191 #define ARM_DEBUG_OFFSET_DBGDEVTYPE (0xFCC)
1192 #define ARM_DEBUG_OFFSET_DBGPID0 (0xFD0)
1193 #define ARM_DEBUG_OFFSET_DBGPID1 (0xFD4)
1194 #define ARM_DEBUG_OFFSET_DBGPID2 (0xFD8)
1195 #define ARM_DEBUG_OFFSET_DBGPID3 (0xFDA)
1196 #define ARM_DEBUG_OFFSET_DBGPID4 (0xFDC)
1197 #define ARM_DEBUG_OFFSET_DBGCID0 (0xFF0)
1198 #define ARM_DEBUG_OFFSET_DBGCID1 (0xFF4)
1199 #define ARM_DEBUG_OFFSET_DBGCID2 (0xFF8)
1200 #define ARM_DEBUG_OFFSET_DBGCID3 (0xFFA)
1201 #define ARM_DEBUG_OFFSET_DBGCID4 (0xFFC)
1204 * Media and VFP Feature Register 1 (MVFR1)
1206 #define MVFR_ASIMD_HPFP 0x00100000UL
1208 #endif /* _ARM_PROC_REG_H_ */
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