iokit/Drivers/network/drvPPCUniN/UniNEnetRegisters.h

   1 /*
   2  * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 /*
  23  * Copyright (c) 1998-1999 Apple Computer
  24  *
  25  * Interface definition for the Sun GEM (UniN) Ethernet controller.
  26  *
  27  *
  28  */
  29
  30 /*
  31  *      Miscellaneous defines...
  32  */
  33 #define CACHE_LINE_SIZE         32       /* Bytes */
  34
  35 #define RX_RING_LENGTH_FACTOR   1               // valid from 0 to 8
  36 #define RX_RING_LENGTH                  (32 * (1 << RX_RING_LENGTH_FACTOR))     // 128 pkt descs                /* Packet descriptors   */
  37 #define RX_RING_WRAP_MASK               (RX_RING_LENGTH -1)
  38
  39 #define TX_RING_LENGTH_FACTOR   2               // valid from 0 to 8
  40 #define TX_RING_LENGTH                  (32 * (1 << TX_RING_LENGTH_FACTOR))     // 128 pkt descs
  41 #define TX_RING_WRAP_MASK               (TX_RING_LENGTH -1)
  42
  43 #define TX_MAX_MBUFS            (TX_RING_LENGTH / 2)
  44
  45 #define TX_DESC_PER_INT         32
  46
  47 #define NETWORK_BUFSIZE         (((ETHERMAXPACKET + ETHERCRC) + 7) & ~7)
  48
  49 #define TRANSMIT_QUEUE_SIZE     256
  50
  51 #define WATCHDOG_TIMER_MS       300
  52 #define TX_KDB_TIMEOUT          1000
  53
  54 #define PCI_PERIOD_33MHz        30
  55 #define PCI_PERIOD_66MHz        15
  56 #define RX_INT_LATENCY_uS       250
  57
  58
  59         struct GMAC_Registers
  60         {
  61                         /* Global Resources:    */                                                              // 0x0000
  62
  63                 UInt32  SEB_State;              //      3 bits for diagnostics
  64                 UInt32  Configuration;  //
  65                 UInt32  filler1;
  66                 UInt32  Status;
  67
  68                 UInt32  InterruptMask;                                                                          // 0x0010
  69                 UInt32  InterruptAck;
  70                 UInt32  filler2;
  71                 UInt32  StatusAlias;
  72
  73                 UInt8   filler3[ 0x1000 - 0x20 ];
  74
  75                 UInt32  PCIErrorStatus;                                                                         // 0x1000
  76                 UInt32  PCIErrorMask;
  77                 UInt32  BIFConfiguration;
  78                 UInt32  BIFDiagnostic;
  79
  80                 UInt32  SoftwareReset;                                                                          // 0x1010
  81
  82                 UInt8   filler4[ 0x2000 - 0x1014 ];
  83
  84                         /* Transmit DMA registers:      */
  85
  86                 UInt32  TxKick;                                                                                         // 0x2000
  87                 UInt32  TxConfiguration;
  88                 UInt32  TxDescriptorBaseLow;
  89                 UInt32  TxDescriptorBaseHigh;
  90
  91                 UInt32  filler5;                                                                                        // 0x2010
  92                 UInt32  TxFIFOWritePointer;
  93                 UInt32  TxFIFOShadowWritePointer;
  94                 UInt32  TxFIFOReadPointer;
  95
  96                 UInt32  TxFIFOShadowReadPointer;                                                        // 0x2020
  97                 UInt32  TxFIFOPacketCounter;
  98                 UInt32  TxStateMachine;
  99                 UInt32  filler6;
 100
 101                 UInt32  TxDataPointerLow;                                                                       // 0x2030
 102                 UInt32  TxDataPointerHigh;
 103
 104                 UInt8   filler7[ 0x2100 - 0x2038 ];
 105
 106                 UInt32  TxCompletion;                                                                           // 0x2100
 107                 UInt32  TxFIFOAddress;
 108                 UInt32  TxFIFOTag;
 109                 UInt32  TxFIFODataLow;
 110
 111                 UInt32  TxFIFODataHighT1;                                                                       // 0x2110
 112                 UInt32  TxFIFODataHighT0;
 113                 UInt32  TxFIFOSize;
 114
 115                 UInt8   filler8[ 0x4000 - 0x211C ];
 116
 117                         /* Receive DMA registers: */
 118
 119                 UInt32  RxConfiguration;                                                                        // 0x4000
 120                 UInt32  RxDescriptorBaseLow;
 121                 UInt32  RxDescriptorBaseHigh;
 122                 UInt32  RxFIFOWritePointer;
 123
 124                 UInt32  RxFIFOShadowWritePointer;                                                       // 0x4010
 125                 UInt32  RxFIFOReadPointer;
 126                 UInt32  RxFIFOPacketCounter;
 127                 UInt32  RxStateMachine;
 128
 129                 UInt32  PauseThresholds;                                                                        // 0x4020
 130                 UInt32  RxDataPointerLow;
 131                 UInt32  RxDataPointerHigh;
 132
 133                 UInt8   filler9[ 0x4100 - 0x402C ];
 134
 135                 UInt32  RxKick;                                                                                         // 0x4100
 136                 UInt32  RxCompletion;
 137                 UInt32  RxBlanking;
 138                 UInt32  RxFIFOAddress;
 139
 140                 UInt32  RxFIFOTag;                                                                                      // 0x4110
 141                 UInt32  RxFIFODataLow;
 142                 UInt32  RxFIFODataHighT0;
 143                 UInt32  RxFIFODataHighT1;
 144
 145                 UInt32  RxFIFOSize;                                                                                     // 0x4120
 146
 147                 UInt8   filler10[ 0x6000 - 0x4124 ];
 148
 149                         /* MAC registers: */
 150
 151                 UInt32  TxMACSoftwareResetCommand;                                                      // 0x6000
 152                 UInt32  RxMACSoftwareResetCommand;
 153                 UInt32  SendPauseCommand;
 154                 UInt32  filler11;
 155
 156                 UInt32  TxMACStatus;                                                                            // 0x6010
 157                 UInt32  RxMACStatus;
 158                 UInt32  MACControlStatus;
 159                 UInt32  filler12;
 160
 161                 UInt32  TxMACMask;                                                                                      // 0x6020
 162                 UInt32  RxMACMask;
 163                 UInt32  MACControlMask;
 164                 UInt32  filler13;
 165
 166                 UInt32  TxMACConfiguration;                                                                     // 0x6030
 167                 UInt32  RxMACConfiguration;
 168                 UInt32  MACControlConfiguration;
 169                 UInt32  XIFConfiguration;
 170
 171                 UInt32  InterPacketGap0;                                                                        // 0x6040
 172                 UInt32  InterPacketGap1;
 173                 UInt32  InterPacketGap2;
 174                 UInt32  SlotTime;
 175
 176                 UInt32  MinFrameSize;                                                                           // 0x6050
 177                 UInt32  MaxFrameSize;
 178                 UInt32  PASize;
 179                 UInt32  JamSize;
 180
 181                 UInt32  AttemptLimit;                                                                           // 0x6060
 182                 UInt32  MACControlType;
 183                 UInt8   filler14[ 0x6080 - 0x6068 ];
 184
 185                 UInt32  MACAddress[ 9 ];                                                                        // 0x6080
 186
 187                 UInt32  AddressFilter[ 3 ];                                                                     // 0x60A4
 188
 189                 UInt32  AddressFilter2_1Mask;                                                           // 0x60B0
 190                 UInt32  AddressFilter0Mask;
 191                 UInt32  filler15[ 2 ];
 192
 193                 UInt32  HashTable[ 16 ];                                                                        // 0x60C0
 194
 195                         /* Statistics registers:        */
 196
 197                 UInt32  NormalCollisionCounter;                                                         // 0x6100
 198                 UInt32  FirstAttemptSuccessfulCollisionCounter;
 199                 UInt32  ExcessiveCollisionCounter;
 200                 UInt32  LateCollisionCounter;
 201
 202                 UInt32  DeferTimer;                                                                                     // 0x6110
 203                 UInt32  PeakAttempts;
 204                 UInt32  ReceiveFrameCounter;
 205                 UInt32  LengthErrorCounter;
 206
 207                 UInt32  AlignmentErrorCounter;                                                          // 0x6120
 208                 UInt32  FCSErrorCounter;
 209                 UInt32  RxCodeViolationErrorCounter;
 210                 UInt32  filler16;
 211
 212                         /* Miscellaneous registers:     */
 213
 214                 UInt32  RandomNumberSeed;                                                                       // 0x6130
 215                 UInt32  StateMachine;
 216
 217                 UInt8   filler17[ 0x6200 - 0x6138 ];
 218
 219                         /* MIF registers: */
 220
 221                 UInt32  MIFBitBangClock;                                                                        // 0x6200
 222                 UInt32  MIFBitBangData;
 223                 UInt32  MIFBitBangOutputEnable;
 224                 UInt32  MIFBitBangFrame_Output;
 225
 226                 UInt32  MIFConfiguration;                                                                       // 0x6210
 227                 UInt32  MIFMask;
 228                 UInt32  MIFStatus;
 229                 UInt32  MIFStateMachine;
 230
 231                 UInt8   filler18[ 0x9000 - 0x6220 ];
 232
 233                         /* PCS/Serialink registers:     */
 234
 235                 UInt32  PCSMIIControl;                                                                          // 0x9000
 236                 UInt32  PCSMIIStatus;
 237                 UInt32  Advertisement;
 238                 UInt32  PCSMIILinkPartnerAbility;
 239
 240                 UInt32  PCSConfiguration;                                                                       // 0x9010
 241                 UInt32  PCSStateMachine;
 242                 UInt32  PCSInterruptStatus;
 243
 244                 UInt8   filler19[ 0x9050 - 0x901C ];
 245
 246                 UInt32  DatapathMode;                                                                           // 0x9050
 247                 UInt32  SerialinkControl;
 248                 UInt32  SharedOutputSelect;
 249                 UInt32  SerialinkState;
 250         };      /* end GMAC_Registers   */
 251
 252
 253 #define kConfiguration_Infinite_Burst   0x00000001
 254 #define kConfiguration_TX_DMA_Limit             (0x1F << 1)
 255 #define kConfiguration_RX_DMA_Limit             (0x1F << 6)
 256
 257         /* The following bits are used in the                                                           */
 258         /* Status, InterruptMask, InterruptAck, and StatusAlias registers:      */
 259
 260 #define kStatus_TX_INT_ME                               0x00000001
 261 #define kStatus_TX_ALL                                  0x00000002
 262 #define kStatus_TX_DONE                                 0x00000004
 263 #define kStatus_RX_DONE                                 0x00000010
 264 #define kStatus_Rx_Buffer_Not_Available 0x00000020
 265 #define kStatus_RX_TAG_ERROR                    0x00000040
 266 #define kStatus_PCS_INT                                 0x00002000
 267 #define kStatus_TX_MAC_INT                              0x00004000
 268 #define kStatus_RX_MAC_INT                              0x00008000
 269 #define kStatus_MAC_CTRL_INT                    0x00010000
 270 #define kStatus_MIF_Interrupt                   0x00020000
 271 #define kStatus_PCI_ERROR_INT                   0x00040000
 272 #define kStatus_TxCompletion_Shift              19
 273
 274 #define kInterruptMask_None                             0xFFFFFFFF
 275
 276 #define kBIFConfiguration_SLOWCLK       0x1
 277 #define kBIFConfiguration_B64D_DIS      0x2
 278 #define kBIFConfiguration_M66EN         0x8
 279
 280 #define kSoftwareReset_TX               0x1
 281 #define kSoftwareReset_RX               0x2
 282 #define kSoftwareReset_RSTOUT   0x4
 283
 284                 // register TxConfiguration 2004:
 285 #define kTxConfiguration_Tx_DMA_Enable                          0x00000001
 286 #define kTxConfiguration_Tx_Desc_Ring_Size_Shift        1                       // bits 1:4
 287 #define kTxConfiguration_TxFIFO_Threshold                       0x001FFC00      // obsolete
 288
 289                 // register RxConfiguration 4000:
 290 #define kRxConfiguration_Rx_DMA_Enable                          0x00000001
 291 #define kRxConfiguration_Rx_Desc_Ring_Size_Shift        1                       // bits 1:4
 292 #define kRxConfiguration_Batch_Disable                          0x00000020
 293 #define kRxConfiguration_First_Byte_Offset_Mask         0x00001C00
 294 #define kRxConfiguration_Checksum_Start_Offset_Mask     0x000FE000
 295 #define kRxConfiguration_RX_DMA_Threshold                       0x01000000      // 128 bytes
 296
 297 #define kPauseThresholds_Factor                                 64
 298 #define kPauseThresholds_OFF_Threshold_Shift    0       // 9 bit field
 299 #define kPauseThresholds_ON_Threshold_Shift             12
 300
 301 #define FACTOR33 ((RX_INT_LATENCY_uS * 1000) / (2048 * PCI_PERIOD_33MHz))
 302 #define FACTOR66 ((RX_INT_LATENCY_uS * 1000) / (2048 * PCI_PERIOD_66MHz))
 303
 304 #define F33 (FACTOR33 << kPauseThresholds_ON_Threshold_Shift )
 305 #define F66 (FACTOR66 << kPauseThresholds_ON_Threshold_Shift )
 306
 307 #define kRxBlanking_default_33  (F33 | 5)
 308 #define kRxBlanking_default_66  (F66 | 5)
 309
 310 #define kTxMACSoftwareResetCommand_Reset        1       // 1 bit register
 311 #define kRxMACSoftwareResetCommand_Reset        1
 312
 313 #define kSendPauseCommand_default       0x1BF0
 314                                                                                                                 // 0x6010:
 315 #define kTX_MAC_Status_Frame_Transmitted                0x001
 316 #define kTX_MAC_Status_Tx_Underrun                              0x002
 317 #define kTX_MAC_Status_Max_Pkt_Err                              0x004
 318 #define kTX_MAC_Status_Normal_Coll_Cnt_Exp              0x008
 319 #define kTX_MAC_Status_Excess_Coll_Cnt_Exp              0x010
 320 #define kTX_MAC_Status_Late_Coll_Cnt_Exp                0x020
 321 #define kTX_MAC_Status_First_Coll_Cnt_Exp               0x040
 322 #define kTX_MAC_Status_Defer_Timer_Exp                  0x080
 323 #define kTX_MAC_Status_Peak_Attempts_Cnt_Exp    0x100
 324                                                                                                                 // 0x6014:
 325 #define kRX_MAC_Status_Frame_Received                   0x01
 326 #define kRX_MAC_Status_Rx_Overflow                              0x02    // Rx FIFO overflow
 327 #define kRX_MAC_Status_Frame_Cnt_Exp                    0x04
 328 #define kRX_MAC_Status_Align_Err_Cnt_Exp                0x08
 329 #define kRX_MAC_Status_CRC_Err_Cnt_Exp                  0x10
 330 #define kRX_MAC_Status_Length_Err_Cnt_Exp               0x20
 331 #define kRX_MAC_Status_Viol_Err_Cnt_Exp                 0x40
 332
 333
 334 #ifdef CRAP
 335 #define kTxMACMask_default                      0x1FF           // was 0xFFFF
 336 #define kRxMACMask_default                      0x7F            // was 0xFFFF
 337 #define kMACControlMask_default         0X00000007      // was 0xFFFF
 338 #else
 339 #define kTxMACMask_default                      1                       // enable all but Frame_Transmitted
 340 #define kRxMACMask_default                      1                       // enable all but Frame_Received
 341 #define kMACControlMask_default         0xFFFFFFF8      // enable Paused stuff
 342 #endif // CRAP
 343
 344 #define kTxMACConfiguration_TxMac_Enable                        0x001
 345 #define kTxMACConfiguration_Ignore_Carrier_Sense        0x002
 346 #define kTxMACConfiguration_Ignore_Collisions           0x004
 347 #define kTxMACConfiguration_Enable_IPG0                         0x008
 348 #define kTxMACConfiguration_Never_Give_Up                       0x010
 349 #define kTxMACConfiguration_Never_Give_Up_Limit         0x020
 350 #define kTxMACConfiguration_No_Backoff                          0x040
 351 #define kTxMACConfiguration_Slow_Down                           0x080
 352 #define kTxMACConfiguration_No_FCS                                      0x100
 353 #define kTxMACConfiguration_TX_Carrier_Extension        0x200
 354
 355 #define kRxMACConfiguration_Rx_Mac_Enable                       0x001
 356 #define kRxMACConfiguration_Strip_Pad                           0x002
 357 #define kRxMACConfiguration_Strip_FCS                           0x004
 358 #define kRxMACConfiguration_Promiscuous                         0x008
 359 #define kRxMACConfiguration_Promiscuous_Group           0x010
 360 #define kRxMACConfiguration_Hash_Filter_Enable          0x020
 361 #define kRxMACConfiguration_Address_Filter_Enable       0x040
 362 #define kRxMACConfiguration_Disable_Discard_On_Err      0x080
 363 #define kRxMACConfiguration_Rx_Carrier_Extension        0x100
 364
 365 #define kMACControlConfiguration_Send_Pause_Enable              0x1
 366 #define kMACControlConfiguration_Receive_Pause_Enable   0x2
 367 #define kMACControlConfiguration_Pass_MAC_Control               0x4
 368
 369 #define kXIFConfiguration_Tx_MII_OE                     0x01    // output enable on the MII bus
 370 #define kXIFConfiguration_MII_Int_Loopback      0x02
 371 #define kXIFConfiguration_Disable_Echo          0x04
 372 #define kXIFConfiguration_GMIIMODE                      0x08
 373 #define kXIFConfiguration_MII_Buffer_OE         0x10
 374 #define kXIFConfiguration_LINKLED                       0x20
 375 #define kXIFConfiguration_FDPLXLED                      0x40
 376
 377 #define kInterPacketGap0_default        0
 378 #define kInterPacketGap1_default        8
 379 #define kInterPacketGap2_default        4
 380
 381 #define kSlotTime_default               0x0040
 382 #define kMinFrameSize_default   0x0040
 383 #define kMaxFrameSize_default   0x05EE
 384
 385 #define kGEMMacMaxFrameSize_Aligned     ((kMaxFrameSize_default + 7) & ~7)
 386
 387
 388 #define kPASize_default                 0x07
 389 #define kJamSize_default                0x04
 390 #define kAttemptLimit_default   0x10
 391 #define kMACControlType_default 0x8808
 392
 393 #define kMACAddress_default_6   0x0001
 394 #define kMACAddress_default_7   0xC200
 395 #define kMACAddress_default_8   0x0180
 396
 397 #define kMIFBitBangFrame_Output_ST_default      0x40000000      // 2 bits: ST of frame
 398 #define kMIFBitBangFrame_Output_OP_read         0x20000000      // OP code - 2 bits:
 399 #define kMIFBitBangFrame_Output_OP_write        0x10000000      // Read=10; Write=01
 400 #define kMIFBitBangFrame_Output_PHYAD_shift     23                      // 5 bit PHY ADdress
 401 #define kMIFBitBangFrame_Output_REGAD_shift     18                      // 5 bit REGister ADdress
 402 #define kMIFBitBangFrame_Output_TA_MSB          0x00020000      // Turn Around MSB
 403 #define kMIFBitBangFrame_Output_TA_LSB          0x00010000      // Turn Around LSB
 404
 405 #define kMIFConfiguration_PHY_Select    0x01
 406 #define kMIFConfiguration_Poll_Enable   0x02
 407 #define kMIFConfiguration_BB_Mode               0x04
 408 #define kMIFConfiguration_MDI_0                 0x10
 409 #define kMIFConfiguration_MDI_1                 0x20
 410
 411 #define kPCSMIIControl_1000_Mbs_Speed_Select    0x0040
 412 #define kPCSMIIControl_Collision_Test                   0x0080
 413 #define kPCSMIIControl_Duplex_Mode                              0x0100
 414 #define kPCSMIIControl_Restart_Auto_Negotiation 0x0200
 415 #define kPCSMIIControl_Isolate                                  0x0400
 416 #define kPCSMIIControl_Power_Down                               0x0800
 417 #define kPCSMIIControl_Auto_Negotiation_Enable  0x1000
 418 #define kPCSMIIControl_Wrapback                                 0x4000
 419 #define kPCSMIIControl_Reset                                    0x8000
 420
 421 #define kAdvertisement_Full_Duplex      0x0020
 422 #define kAdvertisement_Half_Duplex      0x0040
 423 #define kAdvertisement_PAUSE            0x0080  // symmetrical to link partner
 424 #define kAdvertisement_ASM_DIR          0x0100  // pause asymmetrical to link partner
 425 #define kAdvertisement_Ack                      0x4000
 426
 427 #define kPCSConfiguration_Enable                                        0x01
 428 #define kPCSConfiguration_Signal_Detect_Override        0x02
 429 #define kPCSConfiguration_Signal_Detect_Active_Low      0x04
 430 #define kPCSConfiguration_Jitter_Study                          // 2 bit field
 431 #define kPCSConfiguration_10ms_Timer_Override           0x20
 432
 433 #define kDatapathMode_XMode                             0x01
 434 #define kDatapathMode_ExtSERDESMode             0x02
 435 #define kDatapathMode_GMIIMode                  0x04
 436 #define kDatapathMode_GMIIOutputEnable  0x08
 437
 438 #define kSerialinkControl_DisableLoopback       0x01
 439 #define kSerialinkControl_EnableSyncDet         0x02
 440 #define kSerialinkControl_LockRefClk            0x04
 441
 442
 443
 444         /* Descriptor definitions:                                                              */
 445         /* Note: Own is in the high bit of frameDataSize field: */
 446
 447 #define kGEMRxDescFrameSize_Mask        0x7FFF
 448 #define kGEMRxDescFrameSize_Own         0x8000
 449
 450
 451         /* Rx flags field:      */
 452
 453 #define kGEMRxDescFlags_HashValueBit    0x00001000
 454 #define kGEMRxDescFlags_HashValueMask   0x0FFFF000
 455 #define kGEMRxDescFlags_HashPass                0x10000000
 456 #define kGEMRxDescFlags_AlternateAddr   0x20000000
 457 #define kGEMRxDescFlags_BadCRC                  0x40000000
 458
 459
 460 #define kGEMTxDescFlags0_BufferSizeMask         0x00007FFF
 461 //#define kGEMTxDescFlags0_BufferSizeBit                0x00000001
 462 #define kGEMTxDescFlags0_ChecksumStartMask      0x00FF8000
 463 #define kGEMTxDescFlags0_ChecksumStartBit       0x00008000
 464 #define kGEMTxDescFlags0_ChecksumStuffMask      0x1F000000
 465 #define kGEMTxDescFlags0_ChecksupStuffBit       0x01000000
 466 #define kGEMTxDescFlags0_ChecksumEnable         0x20000000
 467 #define kGEMTxDescFlags0_EndOfFrame                     0x40000000
 468 #define kGEMTxDescFlags0_StartOfFrame           0x80000000
 469
 470 #define kGEMTxDescFlags1_Int                            0x00000001
 471 #define kGEMTxDescFlags1_NoCRC                          0x00000002
 472
 473
 474 /*
 475  *      Receive/Transmit descriptor
 476  *
 477  */
 478 typedef struct _GEMRxDescriptor
 479 {
 480     u_int16_t           tcpPseudoChecksum;
 481     u_int16_t           frameDataSize;
 482     u_int32_t           flags;
 483     u_int32_t           bufferAddrLo;
 484     u_int32_t           bufferAddrHi;
 485 } GEMRxDescriptor;
 486
 487 /*
 488  *    Note: Own is in the high bit of frameDataSize field
 489  */
 490 #define kGEMRxDescFrameSize_Mask                0x7FFF
 491 #define kGEMRxDescFrameSize_Own                 0x8000
 492
 493 /*
 494  * Rx flags field
 495  */
 496 #define kGEMRxDescFlags_HashValueBit            0x00001000
 497 #define kGEMRxDescFlags_HashValueMask           0x0FFFF000
 498 #define kGEMRxDescFlags_HashPass                0x10000000
 499 #define kGEMRxDescFlags_AlternateAddr           0x20000000
 500 #define kGEMRxDescFlags_BadCRC                  0x40000000
 501
 502
 503 typedef struct _GEMTxDescriptor
 504 {
 505     u_int32_t           flags0;
 506     u_int32_t           flags1;
 507     u_int32_t           bufferAddrLo;
 508     u_int32_t           bufferAddrHi;
 509 } GEMTxDescriptor;
 510
 511 /*
 512  *
 513  */
 514 #define kGEMTxDescFlags0_BufferSizeMask         0x00007FFF
 515 #define kGEMTxDescFlags0_BufferSizeBit          0x00000001
 516 #define kGEMTxDescFlags0_ChecksumStartMask      0x00FF8000
 517 #define kGEMTxDescFlags0_ChecksumStartBit       0x00008000
 518 #define kGEMTxDescFlags0_ChecksumStuffMask      0x1F000000
 519 #define kGEMTxDescFlags0_ChecksupStuffBit       0x01000000
 520 #define kGEMTxDescFlags0_ChecksumEnable         0x20000000
 521 #define kGEMTxDescFlags0_EndOfFrame             0x40000000
 522 #define kGEMTxDescFlags0_StartOfFrame           0x80000000
 523
 524 #define kGEMTxDescFlags1_Int                    0x00000001
 525 #define kGEMTxDescFlags1_NoCRC                  0x00000002
 526
 527
 528
 529 #define kGEMBurstSize                           (CACHE_LINE_SIZE / 8)