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1 /*
2 * Copyright (c) 2000-2008 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_FREE_COPYRIGHT@
30 */
31 /*
32 * @APPLE_FREE_COPYRIGHT@
33 */
34
35 /*
36 * Author: Bill Angell, Apple
37 * Date: 9/auht-aught
38 *
39 * Random diagnostics
40 */
41
42
43 #include <kern/machine.h>
44 #include <kern/processor.h>
45 #include <mach/machine.h>
46 #include <mach/processor_info.h>
47 #include <mach/mach_types.h>
48 #include <mach/boolean.h>
49 #include <kern/thread.h>
50 #include <kern/task.h>
51 #include <kern/ipc_kobject.h>
52 #include <mach/vm_param.h>
53 #include <ipc/port.h>
54 #include <ipc/ipc_entry.h>
55 #include <ipc/ipc_space.h>
56 #include <ipc/ipc_object.h>
57 #include <ipc/ipc_port.h>
58 #include <ipc/ipc_right.h>
59 #include <vm/vm_kern.h>
60 #include <vm/vm_map.h>
61 #include <vm/vm_page.h>
62 #include <vm/pmap.h>
63 #include <ppc/cpu_internal.h>
64 #include <ppc/exception.h>
65 #include <ppc/Firmware.h>
66 #include <ppc/low_trace.h>
67 #include <ppc/db_low_trace.h>
68 #include <ppc/mappings.h>
69 #include <ppc/pmap.h>
70 #include <ppc/mem.h>
71 #include <ppc/savearea.h>
72 #include <ppc/Diagnostics.h>
73 #include <pexpert/pexpert.h>
74 #include <console/video_console.h>
75 #include <ppc/trap.h>
76
77 extern struct vc_info vinfo;
78 extern uint32_t warFlags;
79 #define warDisMBpoff 0x80000000
80
81 kern_return_t testPerfTrap(int trapno, struct savearea *ss,
82 unsigned int dsisr, addr64_t dar);
83
84
85 int diagCall(struct savearea *save) {
86
87 union {
88 unsigned long long tbase;
89 unsigned int tb[2];
90 } ttt, adj;
91 natural_t tbu, tbu2, tbl;
92 struct per_proc_info *per_proc; /* Area for my per_proc address */
93 int cpu, ret, subc;
94 unsigned int temp, temp2, *baddr, oldwar;
95 addr64_t src, snk;
96 uint64_t srrwrk;
97 scomcomm sarea;
98 ipc_port_t port;
99 ipc_entry_t ientry;
100 processor_t prssr;
101 vm_address_t addrs;
102
103
104 if(!(dgWork.dgFlags & enaDiagSCs)) return 0; /* If not enabled, cause an exception */
105
106 switch(save->save_r3) { /* Select the routine */
107
108 /*
109 * Adjust the timebase for drift recovery testing
110 */
111 case dgAdjTB: /* Adjust the timebase */
112
113 adj.tb[0] = 0; /* Clear high part */
114 adj.tb[1] = save->save_r4; /* Set low order */
115 if(adj.tb[1] & 0x80000000) adj.tb[0] = 0xFFFFFFFF; /* Propagate sign bit */
116
117 do { /* Read current time */
118 asm volatile(" mftbu %0" : "=r" (tbu));
119 asm volatile(" mftb %0" : "=r" (tbl));
120 asm volatile(" mftbu %0" : "=r" (tbu2));
121 } while (tbu != tbu2);
122
123 ttt.tb[0] = tbu; /* Set high */
124 ttt.tb[1] = tbl; /* Set low */
125
126 ttt.tbase = ttt.tbase + adj.tbase; /* Increment or decrement the TB */
127
128 tbu = ttt.tb[0]; /* Save in regular variable */
129 tbl = ttt.tb[1]; /* Save in regular variable */
130
131 mttb(0); /* Set low to keep from ticking */
132 mttbu(tbu); /* Set adjusted high */
133 mttb(tbl); /* Set adjusted low */
134
135 return -1; /* Return no AST checking... */
136
137 /*
138 * Return physical address of a page
139 */
140 case dgLRA:
141
142 save->save_r3 = pmap_find_phys(current_thread()->map->pmap, save->save_r4); /* Get read address */
143
144 return -1; /* Return no AST checking... */
145
146 /*
147 * Copy physical to virtual
148 */
149 case dgpcpy:
150
151
152 #if 1
153 src = (save->save_r4 << 32) | (0x00000000FFFFFFFFULL & save->save_r5); /* Merge into 64-bit */
154 snk = (save->save_r6 << 32) | (0x00000000FFFFFFFFULL & save->save_r7); /* Merge into 64-bit */
155 save->save_r3 = copypv(src, snk, save->save_r8, save->save_r9); /* Copy the physical page */
156 #endif
157 return 1; /* Return and check for ASTs... */
158
159 /*
160 * Read/Write physical memory
161 */
162 case dgprw:
163
164 src = (save->save_r5 << 32) | (0x00000000FFFFFFFFULL & save->save_r6); /* Merge into 64-bit */
165
166 switch(save->save_r4) { /* Select the actual function */
167
168 case 0:
169 save->save_r3 = (uint64_t)ml_phys_read_byte((unsigned int)src);
170 break;
171
172 case 1:
173 save->save_r3 = (uint64_t)ml_phys_read_byte_64(src);
174 break;
175
176 case 2:
177 save->save_r3 = (uint64_t)ml_phys_read((unsigned int)src);
178 break;
179
180 case 3:
181 save->save_r3 = (uint64_t)ml_phys_read_64(src);
182 break;
183
184 case 4:
185 ml_phys_write_byte((unsigned int)src, (unsigned int)save->save_r7);
186 break;
187
188 case 5:
189 ml_phys_write_byte_64(src, (unsigned int)save->save_r7);
190 break;
191
192 case 6:
193 ml_phys_write((unsigned int)src, (unsigned int)save->save_r7);
194 break;
195
196 case 7:
197 ml_phys_write_64(src, (unsigned int)save->save_r7);
198 break;
199 }
200
201 return 1; /* Return and check for ASTs... */
202
203
204 /*
205 * Soft reset processor
206 */
207 case dgreset:
208
209 cpu = save->save_r4; /* Get the requested CPU number */
210
211 if(cpu >= MAX_CPUS) { /* Check for bogus cpu */
212 save->save_r3 = KERN_FAILURE; /* Set failure */
213 return 1;
214 }
215
216 per_proc = PerProcTable[cpu].ppe_vaddr; /* Point to the processor */
217 if(!per_proc->running) return KERN_FAILURE; /* It is not running */
218
219
220 (void)PE_cpu_start(per_proc->cpu_id,
221 per_proc->start_paddr, (vm_offset_t)per_proc);
222
223 save->save_r3 = KERN_SUCCESS; /* Set scuuess */
224
225 return 1; /* Return and check for ASTs... */
226
227 /*
228 * Force cache flush
229 */
230 case dgFlush:
231
232 cacheInit(); /* Blow cache */
233 return 1; /* Return and check for ASTs... */
234
235 /*
236 * various hack tests
237 */
238 case dgtest:
239
240 kprintf("Trying to hang\n");
241 baddr = (unsigned *)((unsigned)&baddr | 1); /* Make an odd address */
242 __asm__ volatile("lwarx r2,0,%0" : : "r" (baddr));
243 kprintf("Didn't hang\n");
244
245 return 1; /* Return and check for ASTs... */
246
247
248
249 /*
250 * Create a physical block map into the current task
251 * Don't bother to check for any errors.
252 * parms - vaddr, paddr, size, prot, attributes
253 */
254 case dgBMphys:
255
256 pmap_map_block(current_thread()->map->pmap, (addr64_t)save->save_r4, /* Map in the block */
257 save->save_r5, save->save_r6, save->save_r7, save->save_r8, 0);
258
259 return 1; /* Return and check for ASTs... */
260
261
262 /*
263 * Remove any mapping from the current task
264 * Don't bother to check for any errors.
265 * parms - vaddr
266 */
267 case dgUnMap:
268
269 (void)mapping_remove(current_thread()->map->pmap, save->save_r4); /* Remove mapping */
270 return 1; /* Return and check for ASTs... */
271
272
273 /*
274 * Allows direct control of alignment handling.
275 *
276 * The bottom bit of the parameter is used to set the control bit, enaNotifyEM.
277 */
278 case dgAlign:
279
280 temp = dgWork.dgFlags; /* Save the old values */
281
282 temp2 = (save->save_r4 & 1) << (31 - enaNotifyEMb); /* Move parms into flag format */
283 dgWork.dgFlags = (temp & ~enaNotifyEM) | temp2; /* Set the flag */
284
285 save->save_r3 = (temp >> (31 - enaNotifyEMb)) & 1; /* Return the original */
286
287 return 1; /* Return and check for ASTs... */
288
289 /*
290 * Return info for boot screen
291 */
292 case dgBootScreen:
293
294 ml_set_interrupts_enabled(1);
295 (void)copyout((char *)&vinfo, save->save_r4, sizeof(struct vc_info)); /* Copy out the video info */
296 ml_set_interrupts_enabled(0);
297 return 1; /* Return and check for ASTs... */
298
299 /*
300 * Don't return info for boot screen
301 */
302 case dgCPNull:
303
304 ml_set_interrupts_enabled(1);
305 (void)copyout((char *)&vinfo, save->save_r4, 0); /* Copy out nothing */
306 ml_set_interrupts_enabled(0);
307 return 1; /* Return and check for ASTs... */
308
309 /*
310 * Test machine check handler - only on 64-bit machines
311 */
312 case dgmck:
313 if(!(PerProcTable[0].ppe_vaddr->pf.Available & pf64Bit)) return 0; /* Leave if not correct machine */
314
315 fwEmMck(save->save_r4, save->save_r5, save->save_r6, save->save_r7, save->save_r8, save->save_r9); /* Start injecting */
316
317 return -1; /* Return and don't check for ASTs... */
318
319 /*
320 * Set 64-bit on or off - only on 64-bit machines
321 */
322 case dg64:
323 if(!(PerProcTable[0].ppe_vaddr->pf.Available & pf64Bit)) return 0; /* Leave if not correct machine */
324
325 srrwrk = save->save_srr1 >> 63; /* Save the old 64-bit bit */
326
327 save->save_srr1 = (save->save_srr1 & 0x7FFFFFFFFFFFFFFFULL) | (save->save_r4 << 63); /* Set the requested mode */
328 save->save_r3 = srrwrk; /* Return the old value */
329
330 task_clear_64BitAddr(current_thread()->task);
331 if((save->save_r4 & 1)) task_set_64BitAddr(current_thread()->task);
332
333 return -1; /* Return and don't check for ASTs... */
334
335 /*
336 * Test the probe read function
337 */
338
339 case dgProbeRead:
340
341 src = (save->save_r4 << 32) | (0x00000000FFFFFFFFULL & save->save_r5); /* Merge into 64-bit */
342 save->save_r3 = ml_probe_read_64(src, &temp); /* Try the address */
343 save->save_r4 = temp; /* Return the data */
344 return -1; /* Regurn and don't check for ASTs */
345
346 /*
347 * Do perf monitor stuff
348 */
349
350 case dgPerfMon:
351
352 setPmon(save->save_r4, save->save_r5); /* Go load up MMCR0 and MMCR1 */
353 return -1; /* Regurn and don't check for ASTs */
354
355 /*
356 * Map a page
357 * Don't bother to check for any errors.
358 * parms - vaddr, paddr, prot, attributes
359 */
360 case dgMapPage:
361
362 (void)mapping_make(current_thread()->map->pmap, /* Map in the page */
363 (addr64_t)(((save->save_r5 & 0xFFFFFFFF) << 32) | (save->save_r5 & 0xFFFFFFFF)), save->save_r6, 0, 1, VM_PROT_READ|VM_PROT_WRITE);
364
365 return -1; /* Return and check for ASTs... */
366
367 /*
368 * SCOM interface
369 * parms - pointer to scomcomm
370 */
371 case dgScom:
372
373 ret = copyin(save->save_r4, (void *)&sarea, sizeof(scomcomm)); /* Get the data */
374 if(ret) return 0; /* Copyin failed - return an exception */
375
376 sarea.scomstat = 0xFFFFFFFFFFFFFFFFULL; /* Clear status */
377 cpu = cpu_number(); /* Get us */
378
379 if((sarea.scomcpu < real_ncpus) && PerProcTable[sarea.scomcpu].ppe_vaddr->running) {
380 if(sarea.scomcpu == cpu) { /* Is it us? */
381 if(sarea.scomfunc) { /* Are we writing */
382 sarea.scomstat = ml_scom_write(sarea.scomreg, sarea.scomdata); /* Write scom */
383 }
384 else {
385 sarea.scomstat = ml_scom_read(sarea.scomreg, &sarea.scomdata); /* Read scom */
386 }
387 }
388 else { /* Otherwise, tell the other processor */
389 (void)cpu_signal(sarea.scomcpu, SIGPcpureq, CPRQscom ,(unsigned int)&sarea); /* Ask him to do this */
390 (void)hw_cpu_sync((unsigned int*)&sarea.scomstat, LockTimeOut); /* Wait for the other processor to get its temperature */
391 }
392 }
393
394 ret = copyout((void *)&sarea, save->save_r4, sizeof(scomcomm)); /* Get the data */
395 if(ret) return 0; /* Copyin failed - return an exception */
396
397 return -1; /* Return and check for ASTs... */
398
399 /*
400 * Bind current thread to a processor. Parm is processor port. If port is 0, unbind.
401 */
402
403 case dgBind:
404
405 if(save->save_r4 == 0) { /* Are we unbinding? */
406 thread_bind(PROCESSOR_NULL); /* Unbind us */
407 save->save_r3 = KERN_SUCCESS; /* Set success */
408 return -1; /* Return and check asts */
409 }
410
411 ret = ipc_right_lookup_write(current_space(), (mach_port_name_t)save->save_r4,
412 &ientry); /* Look up the IPC entry */
413
414 if(ret != KERN_SUCCESS) { /* Couldn't find it */
415 save->save_r3 = ret; /* Pass back return */
416 return -1; /* Return and check asts */
417 }
418
419 port = (ipc_port_t)ientry->ie_object; /* Get the actual port */
420
421 if (!ip_active(port) || (ip_kotype(port) != IKOT_PROCESSOR)) { /* Active and a processor? */
422 is_write_unlock(current_space()); /* Unlock the space */
423 save->save_r3 = KERN_INVALID_ARGUMENT; /* This port is not a processor */
424 return -1; /* Return and check asts */
425 }
426
427 prssr = (processor_t)port->ip_kobject; /* Extract the processor */
428 is_write_unlock(current_space()); /* All done with the space now, unlock it */
429
430 /*
431 * The following probably isn't valid if a processor is in the processor going offline,
432 * but who cares, this is a diagnostic interface...
433 */
434
435 if(prssr->state == PROCESSOR_SHUTDOWN) { /* Are we trying to bind to an offline processor? */
436 save->save_r3 = KERN_INVALID_ARGUMENT; /* This processor is offline */
437 return -1; /* Return and check asts */
438 }
439
440 thread_bind(prssr); /* Bind us to the processor */
441 thread_block(THREAD_CONTINUE_NULL); /* Make it so */
442
443 save->save_r3 = KERN_SUCCESS; /* Set success */
444 return -1; /* Return and check asts */
445
446 /*
447 * Return per_proc for the named processor. Pass in a port. Returns per_proc or 0 if failure
448 */
449
450 case dgPproc:
451
452 ret = ipc_right_lookup_write(current_space(), (mach_port_name_t)save->save_r4,
453 &ientry); /* Look up the IPC entry */
454
455 if(ret != KERN_SUCCESS) { /* Couldn't find it */
456 save->save_r3 = 0; /* Pass back return */
457 return -1; /* Return and check asts */
458 }
459
460 port = (ipc_port_t)ientry->ie_object; /* Get the actualy port */
461
462 if (!ip_active(port) || (ip_kotype(port) != IKOT_PROCESSOR)) { /* Active and a processor? */
463 is_write_unlock(current_space()); /* Unlock the space */
464 save->save_r3 = 0; /* This port is not a processor */
465 return -1; /* Return and check asts */
466 }
467
468 prssr = (processor_t)port->ip_kobject; /* Extract the processor */
469 is_write_unlock(current_space()); /* All done with the space now, unlock it */
470
471 save->save_r3 = (uint64_t)(uint32_t)PerProcTable[prssr->cpu_num].ppe_vaddr; /* Pass back ther per proc */
472 return -1; /* Return and check asts */
473
474 /*
475 * Allocate contiguous memory in the kernel. Pass in size, pass back vaddr or 0 for error
476 * Note that this must be explicitly released by the user. There is an "issue"
477 * if we try to allocate directly into the user: the contiguous area has a kernel wire
478 * on it. If we terminate, we will hang waiting for wire to be released. Ain't no
479 * way that will happen, so we do it in the kernel and make them release it. That way
480 * we will leak rather than hang.
481 *
482 */
483 case dgAcntg:
484
485 addrs = 0; /* Clear just in case */
486
487 ret = kmem_alloc_contig(kernel_map, &addrs, (vm_size_t)save->save_r4,
488 PAGE_MASK, 0, 0); /* That which does not make us stronger, kills us... */
489 if(ret != KERN_SUCCESS) addrs = 0; /* Pass 0 if error */
490
491 save->save_r3 = (uint64_t)addrs; /* Pass back whatever */
492 return -1; /* Return and check for ASTs... */
493
494
495 /*
496 * Return physical address of a page in the kernel
497 */
498 case dgKlra:
499
500 save->save_r3 = pmap_find_phys(kernel_pmap, save->save_r4); /* Get read address */
501 return -1; /* Return no AST checking... */
502
503 /*
504 * Release kernel memory - intent is to release congiguous memory
505 */
506 case dgKfree:
507
508 kmem_free( kernel_map, (vm_address_t) save->save_r4, (vm_size_t)save->save_r5);
509 return -1; /* Return no AST checking... */
510
511
512 case dgWar: /* Set or reset workaround flags */
513
514 save->save_r3 = (uint32_t)warFlags; /* Get the old flags */
515 oldwar = warFlags; /* Remember the old war flags */
516
517 subc = (int32_t)save->save_r4; /* Extract the subcommand */
518 switch(subc) { /* Do what we need */
519 case 1: /* Replace all */
520 warFlags = (uint32_t)save->save_r5; /* Do them all */
521 break;
522
523 case 2: /* Turn on selected workarounds */
524 warFlags = warFlags | (uint32_t)save->save_r5;
525 break;
526
527 case 3: /* Turn off selected workarounds */
528 warFlags = warFlags & ~((uint32_t)save->save_r5);
529 break;
530
531 case 4: /* Start up selected workaround */
532 break;
533
534 case 5: /* Stop selected workaround */
535 break;
536
537 case 6: /* Reset specific workaround parameters to default */
538 break;
539
540 case 7: /* Set workaround parameters */
541 break;
542
543 default:
544
545 break;
546
547 }
548
549 save->save_r3 = oldwar; /* Pass back original */
550 return -1;
551
552
553 default: /* Handle invalid ones */
554 return 0; /* Return an exception */
555
556 }
557
558 };
559
560 kern_return_t
561 testPerfTrap(int trapno, struct savearea *ss, unsigned int dsisr, addr64_t dar)
562 {
563
564 if(trapno != T_ALIGNMENT) return KERN_FAILURE;
565
566 kprintf("alignment exception at %08llX, srr1 = %08llX, dsisr = %08X, dar = %08llX\n",
567 ss->save_srr0, ss->save_srr1, dsisr, dar);
568
569 return KERN_SUCCESS;
570 }
571