osfmk/arm/cpuid.c

   1 /*
   2  * Copyright (c) 2007-2016 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31
  32 #include <pexpert/pexpert.h>
  33 #include <arm/cpuid.h>
  34 #include <arm/cpuid_internal.h>
  35 #include <vm/vm_page.h>
  36 #include "proc_reg.h"
  37
  38 #include <libkern/section_keywords.h>
  39
  40 /* Temporary types to aid decoding,
  41  * Everything in Little Endian */
  42
  43 typedef struct {
  44         uint32_t
  45
  46         Ctype1:3,       /* 2:0 */
  47         Ctype2:3,       /* 5:3 */
  48         Ctype3:3,       /* 8:6 */
  49         Ctypes:15,      /* 6:23 - Don't Care */
  50         LoC:3,          /* 26-24 - Level of Coherency */
  51         LoU:3,          /* 29:27 - Level of Unification */
  52         RAZ:2;          /* 31:30 - Read-As-Zero */
  53 }               arm_cache_clidr_t;
  54
  55 typedef union {
  56         arm_cache_clidr_t bits;
  57         uint32_t        value;
  58 }               arm_cache_clidr_info_t;
  59
  60
  61 typedef struct {
  62         uint32_t
  63
  64         LineSize:3,     /* 2:0 - Number of words in cache line */
  65         Assoc:10,       /* 12:3 - Associativity of cache */
  66         NumSets:15,     /* 27:13 - Number of sets in cache */
  67         c_type:4;       /* 31:28 - Cache type */
  68 }               arm_cache_ccsidr_t;
  69
  70
  71 typedef union {
  72         arm_cache_ccsidr_t bits;
  73         uint32_t        value;
  74 }               arm_cache_ccsidr_info_t;
  75
  76 /* Statics */
  77
  78 static SECURITY_READ_ONLY_LATE(arm_cpu_info_t) cpuid_cpu_info;
  79 static SECURITY_READ_ONLY_LATE(cache_info_t) cpuid_cache_info;
  80
  81 /* Code */
  82
  83 __private_extern__
  84 void
  85 do_cpuid(void)
  86 {
  87         cpuid_cpu_info.value = machine_read_midr();
  88 #if             (__ARM_ARCH__ == 8)
  89
  90         cpuid_cpu_info.arm_info.arm_arch = CPU_ARCH_ARMv8;
  91
  92 #elif   (__ARM_ARCH__ == 7)
  93   #ifdef __ARM_SUB_ARCH__
  94         cpuid_cpu_info.arm_info.arm_arch = __ARM_SUB_ARCH__;
  95   #else
  96         cpuid_cpu_info.arm_info.arm_arch = CPU_ARCH_ARMv7;
  97   #endif
  98 #else
  99         /* 1176 architecture lives in the extended feature register */
 100         if (cpuid_cpu_info.arm_info.arm_arch == CPU_ARCH_EXTENDED) {
 101                 arm_isa_feat1_reg isa = machine_read_isa_feat1();
 102
 103                 /*
 104                  * if isa feature register 1 [15:12] == 0x2, this chip
 105                  * supports sign extention instructions, which indicate ARMv6
 106                  */
 107                 if (isa.field.sign_zero_ext_support == 0x2) {
 108                         cpuid_cpu_info.arm_info.arm_arch = CPU_ARCH_ARMv6;
 109                 }
 110         }
 111 #endif
 112 }
 113
 114 arm_cpu_info_t *
 115 cpuid_info(void)
 116 {
 117         return &cpuid_cpu_info;
 118 }
 119
 120 int
 121 cpuid_get_cpufamily(void)
 122 {
 123         int cpufamily = 0;
 124
 125         switch (cpuid_info()->arm_info.arm_implementor) {
 126         case CPU_VID_ARM:
 127                 switch (cpuid_info()->arm_info.arm_part) {
 128                 case CPU_PART_CORTEXA9:
 129                         cpufamily = CPUFAMILY_ARM_14;
 130                         break;
 131                 case CPU_PART_CORTEXA8:
 132                         cpufamily = CPUFAMILY_ARM_13;
 133                         break;
 134                 case CPU_PART_CORTEXA7:
 135                         cpufamily = CPUFAMILY_ARM_15;
 136                         break;
 137                 case CPU_PART_1136JFS:
 138                 case CPU_PART_1176JZFS:
 139                         cpufamily = CPUFAMILY_ARM_11;
 140                         break;
 141                 case CPU_PART_926EJS:
 142                 case CPU_PART_920T:
 143                         cpufamily = CPUFAMILY_ARM_9;
 144                         break;
 145                 default:
 146                         cpufamily = CPUFAMILY_UNKNOWN;
 147                         break;
 148                 }
 149                 break;
 150
 151         case CPU_VID_INTEL:
 152                 cpufamily = CPUFAMILY_ARM_XSCALE;
 153                 break;
 154
 155         case CPU_VID_APPLE:
 156                 switch (cpuid_info()->arm_info.arm_part) {
 157                 case CPU_PART_SWIFT:
 158                         cpufamily = CPUFAMILY_ARM_SWIFT;
 159                         break;
 160                 case CPU_PART_CYCLONE:
 161                         cpufamily = CPUFAMILY_ARM_CYCLONE;
 162                         break;
 163                 case CPU_PART_TYPHOON:
 164                 case CPU_PART_TYPHOON_CAPRI:
 165                         cpufamily = CPUFAMILY_ARM_TYPHOON;
 166                         break;
 167                 case CPU_PART_TWISTER:
 168                 case CPU_PART_TWISTER_ELBA_MALTA:
 169                         cpufamily = CPUFAMILY_ARM_TWISTER;
 170                         break;
 171                 case CPU_PART_HURRICANE:
 172                 case CPU_PART_HURRICANE_MYST:
 173                         cpufamily = CPUFAMILY_ARM_HURRICANE;
 174                         break;
 175                 case CPU_PART_MONSOON:
 176                 case CPU_PART_MISTRAL:
 177                         cpufamily = CPUFAMILY_ARM_MONSOON_MISTRAL;
 178                         break;
 179                 default:
 180                         cpufamily = CPUFAMILY_UNKNOWN;
 181                         break;
 182                 }
 183                 break;
 184
 185         default:
 186                 cpufamily = CPUFAMILY_UNKNOWN;
 187                 break;
 188         }
 189
 190         return cpufamily;
 191 }
 192
 193 void
 194 do_debugid(void)
 195 {
 196         machine_do_debugid();
 197 }
 198
 199 arm_debug_info_t *
 200 arm_debug_info(void)
 201 {
 202         return machine_arm_debug_info();
 203 }
 204
 205 void
 206 do_mvfpid(void)
 207 {
 208         return machine_do_mvfpid();
 209 }
 210
 211 arm_mvfp_info_t
 212 *arm_mvfp_info(void)
 213 {
 214         return machine_arm_mvfp_info();
 215 }
 216
 217 void
 218 do_cacheid(void)
 219 {
 220         arm_cache_clidr_info_t arm_cache_clidr_info;
 221         arm_cache_ccsidr_info_t arm_cache_ccsidr_info;
 222
 223         arm_cache_clidr_info.value = machine_read_clidr();
 224
 225
 226         /* Select L1 data/unified cache */
 227
 228         machine_write_csselr(CSSELR_L1, CSSELR_DATA_UNIFIED);
 229         arm_cache_ccsidr_info.value = machine_read_ccsidr();
 230
 231         cpuid_cache_info.c_unified = (arm_cache_clidr_info.bits.Ctype1 == 0x4) ? 1 : 0;
 232
 233         switch (arm_cache_ccsidr_info.bits.c_type) {
 234         case 0x1:
 235                 cpuid_cache_info.c_type = CACHE_WRITE_ALLOCATION;
 236                 break;
 237         case 0x2:
 238                 cpuid_cache_info.c_type = CACHE_READ_ALLOCATION;
 239                 break;
 240         case 0x4:
 241                 cpuid_cache_info.c_type = CACHE_WRITE_BACK;
 242                 break;
 243         case 0x8:
 244                 cpuid_cache_info.c_type = CACHE_WRITE_THROUGH;
 245                 break;
 246         default:
 247                 cpuid_cache_info.c_type = CACHE_UNKNOWN;
 248         }
 249
 250         cpuid_cache_info.c_linesz = 4 * (1<<(arm_cache_ccsidr_info.bits.LineSize + 2));
 251         cpuid_cache_info.c_assoc = (arm_cache_ccsidr_info.bits.Assoc + 1);
 252
 253         /* I cache size */
 254         cpuid_cache_info.c_isize = (arm_cache_ccsidr_info.bits.NumSets + 1) * cpuid_cache_info.c_linesz * cpuid_cache_info.c_assoc;
 255
 256         /* D cache size */
 257         cpuid_cache_info.c_dsize = (arm_cache_ccsidr_info.bits.NumSets + 1) * cpuid_cache_info.c_linesz * cpuid_cache_info.c_assoc;
 258
 259
 260         if ((arm_cache_clidr_info.bits.Ctype3 == 0x4) ||
 261             (arm_cache_clidr_info.bits.Ctype2 == 0x4) || (arm_cache_clidr_info.bits.Ctype2 == 0x2)) {
 262
 263                 if (arm_cache_clidr_info.bits.Ctype3 == 0x4) {
 264                         /* Select L3 (LLC) if the SoC is new enough to have that.
 265                          * This will be the second-level cache for the highest-performing ACC. */
 266                         machine_write_csselr(CSSELR_L3, CSSELR_DATA_UNIFIED);
 267                 } else {
 268                         /* Select L2 data cache */
 269                         machine_write_csselr(CSSELR_L2, CSSELR_DATA_UNIFIED);
 270                 }
 271                 arm_cache_ccsidr_info.value = machine_read_ccsidr();
 272
 273                 cpuid_cache_info.c_linesz = 4 * (1<<(arm_cache_ccsidr_info.bits.LineSize + 2));
 274                 cpuid_cache_info.c_assoc = (arm_cache_ccsidr_info.bits.Assoc + 1);
 275                 cpuid_cache_info.c_l2size = (arm_cache_ccsidr_info.bits.NumSets + 1) * cpuid_cache_info.c_linesz * cpuid_cache_info.c_assoc;
 276                 cpuid_cache_info.c_inner_cache_size = cpuid_cache_info.c_dsize;
 277                 cpuid_cache_info.c_bulksize_op = cpuid_cache_info.c_l2size;
 278
 279                 /* capri has a 2MB L2 cache unlike every other SoC up to this
 280                  * point with a 1MB L2 cache, so to get the same performance
 281                  * gain from coloring, we have to double the number of colors.
 282                  * Note that in general (and in fact as it's implemented in
 283                  * i386/cpuid.c), the number of colors is calculated as the
 284                  * cache line size * the number of sets divided by the page
 285                  * size. Also note that for H8 devices and up, the page size
 286                  * will be 16k instead of 4, which will reduce the number of
 287                  * colors required. Thus, this is really a temporary solution
 288                  * for capri specifically that we may want to generalize later:
 289                  *
 290                  * TODO: Are there any special considerations for our unusual
 291                  * cache geometries (3MB)?
 292                  */
 293                 vm_cache_geometry_colors = ((arm_cache_ccsidr_info.bits.NumSets + 1) * cpuid_cache_info.c_linesz) / PAGE_SIZE;
 294                 kprintf(" vm_cache_geometry_colors: %d\n", vm_cache_geometry_colors);
 295         } else {
 296                 cpuid_cache_info.c_l2size = 0;
 297
 298                 cpuid_cache_info.c_inner_cache_size = cpuid_cache_info.c_dsize;
 299                 cpuid_cache_info.c_bulksize_op = cpuid_cache_info.c_dsize;
 300         }
 301
 302         kprintf("%s() - %u bytes %s cache (I:%u D:%u (%s)), %u-way assoc, %u bytes/line\n",
 303                 __FUNCTION__,
 304                 cpuid_cache_info.c_dsize + cpuid_cache_info.c_isize,
 305                 ((cpuid_cache_info.c_type == CACHE_WRITE_BACK) ? "WB" :
 306         (cpuid_cache_info.c_type == CACHE_WRITE_THROUGH ? "WT" : "Unknown")),
 307                 cpuid_cache_info.c_isize,
 308                 cpuid_cache_info.c_dsize,
 309                 (cpuid_cache_info.c_unified) ? "unified" : "separate",
 310                 cpuid_cache_info.c_assoc,
 311                 cpuid_cache_info.c_linesz);
 312 }
 313
 314 cache_info_t   *
 315 cache_info(void)
 316 {
 317         return &cpuid_cache_info;
 318 }