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26 #include <ppc/proc_reg.h>
30 #include <mach/ppc/vm_param.h>
31 #include <ppc/exception.h>
35 * ml_set_physical() -- turn off DR and (if 64-bit) turn SF on
36 * it is assumed that pf64Bit is already in cr6
37 * ml_set_physical_get_ffs() -- turn DR off, SF on, and get feature flags
38 * ml_set_physical_disabled() -- turn DR and EE off, SF on, get feature flags
39 * ml_set_translation_off() -- turn DR, IR, and EE off, SF on, get feature flags
41 * Callable only from assembler, these return:
44 * r10 -- feature flags (pf64Bit etc, ie SPRG 2)
45 * cr6 -- feature flags 24-27, ie pf64Bit, pf128Byte, and pf32Byte
47 * Uses r0 and r2. ml_set_translation_off also uses r3 and cr5.
51 .globl EXT(ml_set_translation_off)
52 LEXT(ml_set_translation_off)
53 mfsprg r10,2 // get feature flags
55 mtcrf 0x02,r10 // move pf64Bit etc to cr6
56 ori r0,r0,lo16(MASK(MSR_EE)+MASK(MSR_FP)+MASK(MSR_IR)+MASK(MSR_DR)) // turn off all 4
58 oris r0,r0,hi16(MASK(MSR_VEC)) // Turn off vector too
59 mtcrf 0x04,r10 // move pfNoMSRir etc to cr5
60 andc r2,r11,r0 // turn off EE, IR, and DR
61 bt++ pf64Bitb,ml_set_physical_64 // skip if 64-bit (only they take the hint)
62 bf pfNoMSRirb,ml_set_physical_32 // skip if we can load MSR directly
63 li r0,loadMSR // Get the MSR setter SC
64 mr r3,r2 // copy new MSR to r2
69 .globl EXT(ml_set_physical_disabled)
71 LEXT(ml_set_physical_disabled)
73 mfsprg r10,2 // get feature flags
74 ori r0,r0,lo16(MASK(MSR_EE)) // turn EE and fp off
75 mtcrf 0x02,r10 // move pf64Bit etc to cr6
76 b ml_set_physical_join
79 .globl EXT(ml_set_physical_get_ffs)
81 LEXT(ml_set_physical_get_ffs)
82 mfsprg r10,2 // get feature flags
83 mtcrf 0x02,r10 // move pf64Bit etc to cr6
85 .globl EXT(ml_set_physical)
88 li r0,0 // do not turn off interrupts
91 oris r0,r0,hi16(MASK(MSR_VEC)) // Always gonna turn of vectors
93 ori r0,r0,lo16(MASK(MSR_DR)+MASK(MSR_FP)) // always turn off DR and FP bit
94 andc r2,r11,r0 // turn off DR and maybe EE
95 bt++ pf64Bitb,ml_set_physical_64 // skip if 64-bit (only they take the hint)
97 mtmsr r2 // turn off translation
102 li r0,1 // get a 1 to slam into SF
103 rldimi r2,r0,63,MSR_SF_BIT // set SF bit (bit 0)
104 mtmsrd r2 // set 64-bit mode, turn off data relocation
110 * ml_restore(old_MSR)
112 * Callable only from assembler, restores the MSR in r11 saved by ml_set_physical.
113 * We assume cr6 and r11 are as set by ml_set_physical, ie:
114 * cr6 - pf64Bit flag (feature flags 24-27)
119 .globl EXT(ml_restore)
122 bt++ pf64Bitb,ml_restore_64 // handle 64-bit cpus (only they take the hint)
123 mtmsr r11 // restore a 32-bit MSR
128 mtmsrd r11 // restore a 64-bit MSR
133 /* PCI config cycle probing
135 * boolean_t ml_probe_read(vm_offset_t paddr, unsigned int *val)
137 * Read the memory location at physical address paddr.
138 * This is a part of a device probe, so there is a good chance we will
139 * have a machine check here. So we have to be able to handle that.
140 * We assume that machine checks are enabled both in MSR and HIDs
143 ; Force a line boundry here
145 .globl EXT(ml_probe_read)
149 mfsprg r9,2 ; Get feature flags
151 rlwinm. r0,r9,0,pf64Bitb,pf64Bitb ; Are we on a 64-bit machine?
152 rlwinm r3,r3,0,0,31 ; Clean up for 64-bit machines
153 bne++ mpr64bit ; Go do this the 64-bit way...
155 mpr32bit: lis r8,hi16(MASK(MSR_VEC)) ; Get the vector flag
156 mfmsr r0 ; Save the current MSR
157 ori r8,r8,lo16(MASK(MSR_FP)) ; Add the FP flag
159 neg r10,r3 ; Number of bytes to end of page
160 andc r0,r0,r8 ; Clear VEC and FP
161 rlwinm. r10,r10,0,20,31 ; Clear excess junk and test for page bndry
162 ori r8,r8,lo16(MASK(MSR_EE)|MASK(MSR_IR)|MASK(MSR_DR)) ; Drop EE, IR, and DR
163 mr r12,r3 ; Save the load address
164 andc r2,r0,r8 ; Clear VEC, FP, and EE
165 mtcrf 0x04,r9 ; Set the features
166 cmplwi cr1,r10,4 ; At least 4 bytes left in page?
167 beq- mprdoit ; We are right on the boundary...
169 bltlr- cr1 ; No, just return failure...
173 bt pfNoMSRirb,mprNoMSR ; No MSR...
175 mtmsr r2 ; Translation and all off
176 isync ; Toss prefetch
181 li r0,loadMSR ; Get the MSR setter SC
182 mr r3,r2 ; Get new MSR
188 mfspr r6, hid0 ; Get a copy of hid0
190 rlwinm. r5, r9, 0, pfNoMuMMCKb, pfNoMuMMCKb ; Check for NoMuMMCK
193 rlwinm r5, r6, 0, ice+1, ice-1 ; Turn off L1 I-Cache
195 isync ; Wait for I-Cache off
196 rlwinm r5, r6, 0, mum+1, mum-1 ; Turn off MuM w/ I-Cache on
201 ; We need to insure that there is no more than 1 BAT register that
202 ; can get a hit. There could be repercussions beyond the ken
203 ; of mortal man. It is best not to tempt fate.
206 ; Note: we will reload these from the shadow BATs later
208 li r10,0 ; Clear a register
210 sync ; Make sure all is well
212 mtdbatu 1,r10 ; Invalidate DBAT 1
213 mtdbatu 2,r10 ; Invalidate DBAT 2
214 mtdbatu 3,r10 ; Invalidate DBAT 3
216 rlwinm r10,r12,0,0,14 ; Round down to a 128k boundary
217 ori r11,r10,0x32 ; Set uncached, coherent, R/W
218 ori r10,r10,2 ; Make the upper half (128k, valid supervisor)
219 mtdbatl 0,r11 ; Set lower BAT first
220 mtdbatu 0,r10 ; Now the upper
221 sync ; Just make sure
223 dcbf 0,r12 ; Make sure we kill the cache to avoid paradoxes
226 ori r11,r2,lo16(MASK(MSR_DR)) ; Turn on data translation
227 mtmsr r11 ; Do it for real
228 isync ; Make sure of it
230 eieio ; Make sure of all previous accesses
231 sync ; Make sure it is all caught up
233 lwz r11,0(r12) ; Get it and maybe machine check here
235 eieio ; Make sure of ordering again
236 sync ; Get caught up yet again
237 isync ; Do not go further till we are here
239 mtmsr r2 ; Turn translation back off
242 lis r10,hi16(EXT(shadow_BAT)+shdDBAT) ; Get shadow address
243 ori r10,r10,lo16(EXT(shadow_BAT)+shdDBAT) ; Get shadow address
245 lwz r5,0(r10) ; Pick up DBAT 0 high
246 lwz r6,4(r10) ; Pick up DBAT 0 low
247 lwz r7,8(r10) ; Pick up DBAT 1 high
248 lwz r8,16(r10) ; Pick up DBAT 2 high
249 lwz r9,24(r10) ; Pick up DBAT 3 high
251 mtdbatu 0,r5 ; Restore DBAT 0 high
252 mtdbatl 0,r6 ; Restore DBAT 0 low
253 mtdbatu 1,r7 ; Restore DBAT 1 high
254 mtdbatu 2,r8 ; Restore DBAT 2 high
255 mtdbatu 3,r9 ; Restore DBAT 3 high
260 mtmsr r0 ; Restore translation and exceptions
261 isync ; Toss speculations
263 stw r11,0(r4) ; Save the loaded value
266 ; Force a line boundry here. This means we will be able to check addresses better
268 .globl EXT(ml_probe_read_mck)
269 LEXT(ml_probe_read_mck)
272 /* PCI config cycle probing - 64-bit
274 * boolean_t ml_probe_read_64(addr64_t paddr, unsigned int *val)
276 * Read the memory location at physical address paddr.
277 * This is a part of a device probe, so there is a good chance we will
278 * have a machine check here. So we have to be able to handle that.
279 * We assume that machine checks are enabled both in MSR and HIDs
282 ; Force a line boundry here
284 .globl EXT(ml_probe_read_64)
286 LEXT(ml_probe_read_64)
288 mfsprg r9,2 ; Get feature flags
289 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
290 rlwinm. r0,r9,0,pf64Bitb,pf64Bitb ; Are we on a 64-bit machine?
291 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
293 mr r4,r5 ; Move result to common register
294 beq-- mpr32bit ; Go do this the 32-bit way...
296 mpr64bit: andi. r0,r3,3 ; Check if we are on a word boundary
297 li r0,0 ; Clear the EE bit (and everything else for that matter)
298 bne-- mprFail ; Boundary not good...
299 mfmsr r11 ; Get the MSR
300 mtmsrd r0,1 ; Set the EE bit only (do not care about RI)
301 rlwinm r11,r11,0,MSR_EE_BIT,MSR_EE_BIT ; Isolate just the EE bit
302 mfmsr r10 ; Refresh our view of the MSR (VMX/FP may have changed)
303 or r12,r10,r11 ; Turn on EE if on before we turned it off
304 ori r0,r0,lo16(MASK(MSR_IR)|MASK(MSR_DR)) ; Get the IR and DR bits
306 sldi r2,r2,63 ; Get the 64-bit bit
307 andc r10,r10,r0 ; Clear IR and DR
308 or r10,r10,r2 ; Set 64-bit
311 mtmsrd r10 ; Translation and EE off, 64-bit on
314 sldi r0,r0,32+8 ; Get the right bit to inhibit caching
316 mfspr r8,hid4 ; Get HID4
317 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
319 mtspr hid4,r2 ; Make real accesses cache-inhibited
320 isync ; Toss prefetches
322 lis r7,0xE000 ; Get the unlikeliest ESID possible
323 srdi r7,r7,1 ; Make 0x7FFFFFFFF0000000
324 slbie r7 ; Make sure the ERAT is cleared
329 eieio ; Make sure of all previous accesses
331 lwz r11,0(r3) ; Get it and maybe machine check here
333 eieio ; Make sure of ordering again
334 sync ; Get caught up yet again
335 isync ; Do not go further till we are here
338 mtspr hid4,r8 ; Make real accesses not cache-inhibited
339 isync ; Toss prefetches
341 lis r7,0xE000 ; Get the unlikeliest ESID possible
342 srdi r7,r7,1 ; Make 0x7FFFFFFFF0000000
343 slbie r7 ; Make sure the ERAT is cleared
345 mtmsrd r12 ; Restore entry MSR
348 stw r11,0(r4) ; Pass back the result
349 li r3,1 ; Indicate success
352 mprFail: li r3,0 ; Set failure
355 ; Force a line boundry here. This means we will be able to check addresses better
357 .globl EXT(ml_probe_read_mck_64)
358 LEXT(ml_probe_read_mck_64)
361 /* Read physical address byte
363 * unsigned int ml_phys_read_byte(vm_offset_t paddr)
364 * unsigned int ml_phys_read_byte_64(addr64_t paddr)
366 * Read the byte at physical address paddr. Memory should not be cache inhibited.
369 ; Force a line boundry here
372 .globl EXT(ml_phys_read_byte_64)
374 LEXT(ml_phys_read_byte_64)
376 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
377 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
378 b ml_phys_read_byte_join
380 .globl EXT(ml_phys_read_byte)
382 LEXT(ml_phys_read_byte)
383 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
384 ml_phys_read_byte_join: ; r3 = address to read (reg64_t)
385 mflr r11 ; Save the return
386 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
388 lbz r3,0(r3) ; Get the byte
389 b rdwrpost ; Clean up and leave...
392 /* Read physical address half word
394 * unsigned int ml_phys_read_half(vm_offset_t paddr)
395 * unsigned int ml_phys_read_half_64(addr64_t paddr)
397 * Read the half word at physical address paddr. Memory should not be cache inhibited.
400 ; Force a line boundry here
403 .globl EXT(ml_phys_read_half_64)
405 LEXT(ml_phys_read_half_64)
407 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
408 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
409 b ml_phys_read_half_join
411 .globl EXT(ml_phys_read_half)
413 LEXT(ml_phys_read_half)
414 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
415 ml_phys_read_half_join: ; r3 = address to read (reg64_t)
416 mflr r11 ; Save the return
417 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
419 lhz r3,0(r3) ; Get the half word
420 b rdwrpost ; Clean up and leave...
423 /* Read physical address word
425 * unsigned int ml_phys_read(vm_offset_t paddr)
426 * unsigned int ml_phys_read_64(addr64_t paddr)
427 * unsigned int ml_phys_read_word(vm_offset_t paddr)
428 * unsigned int ml_phys_read_word_64(addr64_t paddr)
430 * Read the word at physical address paddr. Memory should not be cache inhibited.
433 ; Force a line boundry here
436 .globl EXT(ml_phys_read_64)
437 .globl EXT(ml_phys_read_word_64)
439 LEXT(ml_phys_read_64)
440 LEXT(ml_phys_read_word_64)
442 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
443 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
444 b ml_phys_read_word_join
446 .globl EXT(ml_phys_read)
447 .globl EXT(ml_phys_read_word)
450 LEXT(ml_phys_read_word)
451 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
452 ml_phys_read_word_join: ; r3 = address to read (reg64_t)
453 mflr r11 ; Save the return
454 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
456 lwz r3,0(r3) ; Get the word
457 b rdwrpost ; Clean up and leave...
460 /* Read physical address double word
462 * unsigned long long ml_phys_read_double(vm_offset_t paddr)
463 * unsigned long long ml_phys_read_double_64(addr64_t paddr)
465 * Read the double word at physical address paddr. Memory should not be cache inhibited.
468 ; Force a line boundry here
471 .globl EXT(ml_phys_read_double_64)
473 LEXT(ml_phys_read_double_64)
475 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
476 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
477 b ml_phys_read_double_join
479 .globl EXT(ml_phys_read_double)
481 LEXT(ml_phys_read_double)
482 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
483 ml_phys_read_double_join: ; r3 = address to read (reg64_t)
484 mflr r11 ; Save the return
485 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
487 lwz r4,4(r3) ; Get the low word
488 lwz r3,0(r3) ; Get the high word
489 b rdwrpost ; Clean up and leave...
492 /* Write physical address byte
494 * void ml_phys_write_byte(vm_offset_t paddr, unsigned int data)
495 * void ml_phys_write_byte_64(addr64_t paddr, unsigned int data)
497 * Write the byte at physical address paddr. Memory should not be cache inhibited.
501 .globl EXT(ml_phys_write_byte_64)
503 LEXT(ml_phys_write_byte_64)
505 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
506 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
507 mr r4,r5 ; Copy over the data
508 b ml_phys_write_byte_join
510 .globl EXT(ml_phys_write_byte)
512 LEXT(ml_phys_write_byte)
513 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
514 ml_phys_write_byte_join: ; r3 = address to write (reg64_t), r4 = data
515 mflr r11 ; Save the return
516 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
518 stb r4,0(r3) ; Set the byte
519 b rdwrpost ; Clean up and leave...
522 /* Write physical address half word
524 * void ml_phys_write_half(vm_offset_t paddr, unsigned int data)
525 * void ml_phys_write_half_64(addr64_t paddr, unsigned int data)
527 * Write the half word at physical address paddr. Memory should not be cache inhibited.
531 .globl EXT(ml_phys_write_half_64)
533 LEXT(ml_phys_write_half_64)
535 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
536 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
537 mr r4,r5 ; Copy over the data
538 b ml_phys_write_half_join
540 .globl EXT(ml_phys_write_half)
542 LEXT(ml_phys_write_half)
543 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
544 ml_phys_write_half_join: ; r3 = address to write (reg64_t), r4 = data
545 mflr r11 ; Save the return
546 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
548 sth r4,0(r3) ; Set the half word
549 b rdwrpost ; Clean up and leave...
552 /* Write physical address word
554 * void ml_phys_write(vm_offset_t paddr, unsigned int data)
555 * void ml_phys_write_64(addr64_t paddr, unsigned int data)
556 * void ml_phys_write_word(vm_offset_t paddr, unsigned int data)
557 * void ml_phys_write_word_64(addr64_t paddr, unsigned int data)
559 * Write the word at physical address paddr. Memory should not be cache inhibited.
563 .globl EXT(ml_phys_write_64)
564 .globl EXT(ml_phys_write_word_64)
566 LEXT(ml_phys_write_64)
567 LEXT(ml_phys_write_word_64)
569 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
570 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
571 mr r4,r5 ; Copy over the data
572 b ml_phys_write_word_join
574 .globl EXT(ml_phys_write)
575 .globl EXT(ml_phys_write_word)
578 LEXT(ml_phys_write_word)
579 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
580 ml_phys_write_word_join: ; r3 = address to write (reg64_t), r4 = data
581 mflr r11 ; Save the return
582 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
584 stw r4,0(r3) ; Set the word
585 b rdwrpost ; Clean up and leave...
588 /* Write physical address double word
590 * void ml_phys_write_double(vm_offset_t paddr, unsigned long long data)
591 * void ml_phys_write_double_64(addr64_t paddr, unsigned long long data)
593 * Write the double word at physical address paddr. Memory should not be cache inhibited.
597 .globl EXT(ml_phys_write_double_64)
599 LEXT(ml_phys_write_double_64)
601 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
602 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
603 mr r4,r5 ; Copy over the high data
604 mr r5,r6 ; Copy over the low data
605 b ml_phys_write_double_join
607 .globl EXT(ml_phys_write_double)
609 LEXT(ml_phys_write_double)
610 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
611 ml_phys_write_double_join: ; r3 = address to write (reg64_t), r4,r5 = data (long long)
612 mflr r11 ; Save the return
613 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
615 stw r4,0(r3) ; Set the high word
616 stw r5,4(r3) ; Set the low word
617 b rdwrpost ; Clean up and leave...
622 rdwrpre: mfsprg r12,2 ; Get feature flags
623 lis r8,hi16(MASK(MSR_VEC)) ; Get the vector flag
624 mfmsr r10 ; Save the MSR
625 ori r8,r8,lo16(MASK(MSR_FP)) ; Add the FP flag
626 mtcrf 0x02,r12 ; move pf64Bit
627 andc r10,r10,r8 ; Clear VEC and FP
628 ori r9,r8,lo16(MASK(MSR_EE)|MASK(MSR_IR)|MASK(MSR_DR)) ; Drop EE, DR, and IR
629 li r2,1 ; Prepare for 64 bit
630 andc r9,r10,r9 ; Clear VEC, FP, DR, and EE
631 bf-- pf64Bitb,rdwrpre32 ; Join 32-bit code...
633 srdi r7,r3,31 ; Get a 1 if address is in I/O memory
634 rldimi r9,r2,63,MSR_SF_BIT ; set SF bit (bit 0)
635 cmpldi cr7,r7,1 ; Is source in I/O memory?
636 mtmsrd r9 ; set 64-bit mode, turn off EE, DR, and IR
639 sldi r0,r2,32+8 ; Get the right bit to turn off caching
641 bnelr++ cr7 ; We are not in the I/O area, all ready...
643 mfspr r8,hid4 ; Get HID4
644 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
646 mtspr hid4,r2 ; Make real accesses cache-inhibited
647 isync ; Toss prefetches
649 lis r7,0xE000 ; Get the unlikeliest ESID possible
650 srdi r7,r7,1 ; Make 0x7FFFFFFFF0000000
651 slbie r7 ; Make sure the ERAT is cleared
655 blr ; Finally, all ready...
659 rdwrpre32: rlwimi r9,r10,0,MSR_IR_BIT,MSR_IR_BIT ; Leave the IR bit unchanged
660 mtmsr r9 ; Drop EE, DR, and leave IR unchanged
662 blr ; All set up, leave...
666 rdwrpost: mtlr r11 ; Restore the return
667 bt++ pf64Bitb,rdwrpost64 ; Join 64-bit code...
669 mtmsr r10 ; Restore entry MSR (sans FP and VEC)
673 rdwrpost64: bne++ cr7,rdwrpcok ; Skip enabling real mode caching if we did not change it...
676 mtspr hid4,r8 ; Make real accesses not cache-inhibited
677 isync ; Toss prefetches
679 lis r7,0xE000 ; Get the unlikeliest ESID possible
680 srdi r7,r7,1 ; Make 0x7FFFFFFFF0000000
681 slbie r7 ; Make sure the ERAT is cleared
683 rdwrpcok: mtmsrd r10 ; Restore entry MSR (sans FP and VEC)
688 /* set interrupts enabled or disabled
690 * boolean_t set_interrupts_enabled(boolean_t enable)
692 * Set EE bit to "enable" and return old value as boolean
695 ; Force a line boundry here
697 .globl EXT(ml_set_interrupts_enabled)
699 LEXT(ml_set_interrupts_enabled)
701 andi. r4,r3,1 ; Are we turning interruptions on?
702 lis r0,hi16(MASK(MSR_VEC)) ; Get vector enable
703 mfmsr r5 ; Get the current MSR
704 ori r0,r0,lo16(MASK(MSR_EE)|MASK(MSR_FP)) ; Get float enable and EE enable
705 rlwinm r3,r5,17,31,31 ; Set return value
706 andc r5,r5,r0 ; Force VEC and FP off
707 bne CheckPreemption ; Interrupts going on, check ASTs...
709 mtmsr r5 ; Slam diable (always going disabled here)
710 isync ; Need this because FP/Vec might go off
717 ori r5,r5,lo16(MASK(MSR_EE)) ; Turn on the enable
718 lwz r8,PP_NEED_AST(r7) ; Get pointer to AST flags
719 mfsprg r9,1 ; Get current activation
720 li r6,AST_URGENT ; Get the type we will preempt for
721 lwz r7,ACT_PREEMPT_CNT(r9) ; Get preemption count
722 lwz r8,0(r8) ; Get AST flags
723 lis r0,hi16(DoPreemptCall) ; High part of Preempt FW call
724 cmpwi cr1,r7,0 ; Are preemptions masked off?
725 and. r8,r8,r6 ; Are we urgent?
726 crorc cr1_eq,cr0_eq,cr1_eq ; Remember if preemptions are masked or not urgent
727 ori r0,r0,lo16(DoPreemptCall) ; Bottome of FW call
729 mtmsr r5 ; Restore the MSR now, before we can preempt
730 isync ; Need this because FP/Vec might go off
732 beqlr++ cr1 ; Return if no premption...
737 /* Set machine into idle power-saving mode.
739 * void machine_idle_ppc(void)
741 * We will use the PPC NAP or DOZE for this.
742 * This call always returns. Must be called with spllo (i.e., interruptions
747 ; Force a line boundry here
749 .globl EXT(machine_idle_ppc)
751 LEXT(machine_idle_ppc)
753 lis r0,hi16(MASK(MSR_VEC)) ; Get the vector flag
754 mfmsr r3 ; Save the MSR
755 ori r0,r0,lo16(MASK(MSR_FP)) ; Add the FP flag
756 andc r3,r3,r0 ; Clear VEC and FP
757 ori r0,r0,lo16(MASK(MSR_EE)) ; Drop EE also
758 andc r5,r3,r0 ; Clear VEC, FP, DR, and EE
760 mtmsr r5 ; Hold up interruptions for now
761 isync ; May have messed with fp/vec
762 mfsprg r12,0 ; Get the per_proc_info
763 mfsprg r11,2 ; Get CPU specific features
764 mfspr r6,hid0 ; Get the current power-saving mode
765 mtcrf 0xC7,r11 ; Get the facility flags
767 lis r4,hi16(napm) ; Assume we can nap
768 bt pfWillNapb,yesnap ; Yeah, nap is ok...
770 lis r4,hi16(dozem) ; Assume we can doze
771 bt pfCanDozeb,yesnap ; We can sleep or doze one this machine...
773 ori r3,r3,lo16(MASK(MSR_EE)) ; Flip on EE
774 mtmsr r3 ; Turn interruptions back on
777 yesnap: mftbu r9 ; Get the upper timebase
778 mftb r7 ; Get the lower timebase
779 mftbu r8 ; Get the upper one again
780 cmplw r9,r8 ; Did the top tick?
781 bne- yesnap ; Yeah, need to get it again...
782 stw r8,napStamp(r12) ; Set high order time stamp
783 stw r7,napStamp+4(r12) ; Set low order nap stamp
785 rlwinm. r7,r11,0,pfNoL2PFNapb,pfNoL2PFNapb ; Turn off L2 Prefetch before nap?
788 mfspr r7,msscr0 ; Get currect MSSCR0 value
789 rlwinm r7,r7,0,0,l2pfes-1 ; Disable L2 Prefetch
790 mtspr msscr0,r7 ; Updates MSSCR0 value
795 rlwinm. r7,r11,0,pfSlowNapb,pfSlowNapb ; Should nap at slow speed?
798 mfspr r7,hid1 ; Get current HID1 value
799 oris r7,r7,hi16(hid1psm) ; Select PLL1
800 mtspr hid1,r7 ; Update HID1 value
805 ; We have to open up interruptions here because book 4 says that we should
806 ; turn on only the POW bit and that we should have interrupts enabled
807 ; The interrupt handler will detect that nap or doze is set if an interrupt
808 ; is taken and set everything up to return directly to machine_idle_ret.
809 ; So, make sure everything we need there is already set up...
812 li r10,hi16(dozem|napm|sleepm) ; Mask of power management bits
814 bf-- pf64Bitb,mipNSF1 ; skip if 32-bit...
816 sldi r4,r4,32 ; Position the flags
817 sldi r10,r10,32 ; Position the masks
820 mipNSF1: andc r6,r6,r10 ; Clean up the old power bits
822 ori r7,r5,lo16(MASK(MSR_EE)) ; Flip on EE
823 or r6,r6,r4 ; Set nap or doze
824 oris r5,r7,hi16(MASK(MSR_POW)) ; Turn on power management in next MSR
827 mtspr hid0,r6 ; Set up the HID for nap/doze
828 mfspr r6,hid0 ; Yes, this is silly, keep it here
829 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
830 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
831 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
832 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
833 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
834 isync ; Make sure it is set
836 mtmsr r7 ; Enable for interrupts
837 rlwinm. r11,r11,0,pfAltivecb,pfAltivecb ; Do we have altivec?
839 dssall ; Stop the streams before we nap/doze
841 minovec: sync ; Make sure queues are clear
842 mtmsr r5 ; Nap or doze
843 isync ; Make sure this takes before we proceed
844 b minovec ; loop if POW does not take
846 ; Note that the interrupt handler will turn off the nap/doze bits in the hid.
847 ; Also remember that the interrupt handler will force return to here whenever
848 ; the nap/doze bits are set.
850 .globl EXT(machine_idle_ret)
851 LEXT(machine_idle_ret)
852 mtmsr r7 ; Make sure the MSR is what we want
853 isync ; In case we turn on translation
857 /* Put machine to sleep.
858 * This call never returns. We always exit sleep via a soft reset.
859 * All external interruptions must be drained at this point and disabled.
861 * void ml_ppc_sleep(void)
863 * We will use the PPC SLEEP for this.
865 * There is one bit of hackery in here: we need to enable for
866 * interruptions when we go to sleep and there may be a pending
867 * decrimenter rupt. So we make the decrimenter 0x7FFFFFFF and enable for
868 * interruptions. The decrimenter rupt vector recognizes this and returns
869 * directly back here.
873 ; Force a line boundry here
875 .globl EXT(ml_ppc_sleep)
880 mfmsr r5 ; Hack to spin instead of sleep
881 rlwinm r5,r5,0,MSR_DR_BIT+1,MSR_IR_BIT-1 ; Turn off translation
882 rlwinm r5,r5,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Turn off interruptions
883 mtmsr r5 ; No talking
886 deadsleep: addi r3,r3,1 ; Make analyzer happy
889 b deadsleep ; Die the death of 1000 joys...
892 mfsprg r12,0 ; Get the per_proc_info
893 mfspr r4,hid0 ; Get the current power-saving mode
894 eqv r10,r10,r10 ; Get all foxes
895 mfsprg r11,2 ; Get CPU specific features
897 rlwinm. r5,r11,0,pfNoL2PFNapb,pfNoL2PFNapb ; Turn off L2 Prefetch before sleep?
900 mfspr r5,msscr0 ; Get currect MSSCR0 value
901 rlwinm r5,r5,0,0,l2pfes-1 ; Disable L2 Prefetch
902 mtspr msscr0,r5 ; Updates MSSCR0 value
907 rlwinm. r5,r11,0,pf64Bitb,pf64Bitb ; PM bits are shifted on 64bit systems.
910 rlwinm r4,r4,0,sleep+1,doze-1 ; Clear all possible power-saving modes (not DPM though)
911 oris r4,r4,hi16(sleepm) ; Set sleep
915 lis r5, hi16(dozem|napm|sleepm) ; Clear all possible power-saving modes (not DPM though)
918 lis r5, hi16(napm) ; Set sleep
919 // lis r5, hi16(dozem) ; Set sleep
924 mfmsr r5 ; Get the current MSR
925 rlwinm r10,r10,0,1,31 ; Make 0x7FFFFFFF
926 mtdec r10 ; Load decrimenter with 0x7FFFFFFF
927 isync ; and make sure,
928 mfdec r9 ; really sure, it gets there
930 mtcrf 0x07,r11 ; Get the cache flags, etc
932 rlwinm r5,r5,0,MSR_DR_BIT+1,MSR_IR_BIT-1 ; Turn off translation
934 ; Note that we need translation off before we set the HID to sleep. Otherwise
935 ; we will ignore any PTE misses that occur and cause an infinite loop.
937 bt pfNoMSRirb,mpsNoMSR ; No MSR...
939 mtmsr r5 ; Translation off
940 isync ; Toss prefetch
944 li r0,loadMSR ; Get the MSR setter SC
945 mr r3,r5 ; Get new MSR
949 ori r3,r5,lo16(MASK(MSR_EE)) ; Flip on EE
951 mtspr hid0,r4 ; Set up the HID to sleep
952 mfspr r4,hid0 ; Yes, this is silly, keep it here
953 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
954 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
955 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
956 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
957 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
959 mtmsr r3 ; Enable for interrupts to drain decrimenter
961 add r6,r4,r5 ; Just waste time
962 add r6,r6,r4 ; A bit more
963 add r6,r6,r5 ; A bit more
965 mtmsr r5 ; Interruptions back off
966 isync ; Toss prefetch
969 ; We are here with translation off, interrupts off, all possible
970 ; interruptions drained off, and a decrimenter that will not pop.
973 bl EXT(cacheInit) ; Clear out the caches. This will leave them on
974 bl EXT(cacheDisable) ; Turn off all caches
976 mfmsr r5 ; Get the current MSR
977 oris r5,r5,hi16(MASK(MSR_POW)) ; Turn on power management in next MSR
978 ; Leave EE off because power goes off shortly
981 sync ; Sync it all up
982 mtmsr r5 ; Do sleep with interruptions enabled
984 b slSleepNow ; Go back to sleep if we wake up...
988 /* Initialize all caches including the TLBs
990 * void cacheInit(void)
992 * This is used to force the caches to an initial clean state. First, we
993 * check if the cache is on, if so, we need to flush the contents to memory.
994 * Then we invalidate the L1. Next, we configure and invalidate the L2 etc.
995 * Finally we turn on all of the caches
997 * Note that if translation is not disabled when this is called, the TLB will not
998 * be completely clear after return.
1002 ; Force a line boundry here
1004 .globl EXT(cacheInit)
1008 mfsprg r12,0 ; Get the per_proc_info
1009 mfspr r9,hid0 ; Get the current power-saving mode
1011 mfsprg r11,2 ; Get CPU specific features
1012 mfmsr r7 ; Get the current MSR
1013 rlwinm r7,r7,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1014 rlwinm r7,r7,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1015 rlwimi r11,r11,pfLClckb+1,31,31 ; Move pfLClck to another position (to keep from using non-volatile CRs)
1016 rlwinm r5,r7,0,MSR_DR_BIT+1,MSR_IR_BIT-1 ; Turn off translation
1017 rlwinm r5,r5,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Turn off interruptions
1018 mtcrf 0x87,r11 ; Get the feature flags
1019 lis r10,hi16(dozem|napm|sleepm|dpmm) ; Mask of power management bits
1020 bf-- pf64Bitb,cIniNSF1 ; Skip if 32-bit...
1022 sldi r10,r10,32 ; Position the masks
1024 cIniNSF1: andc r4,r9,r10 ; Clean up the old power bits
1025 mtspr hid0,r4 ; Set up the HID
1026 mfspr r4,hid0 ; Yes, this is silly, keep it here
1027 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1028 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1029 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1030 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1031 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1033 bt pfNoMSRirb,ciNoMSR ; No MSR...
1035 mtmsr r5 ; Translation and all off
1036 isync ; Toss prefetch
1040 li r0,loadMSR ; Get the MSR setter SC
1041 mr r3,r5 ; Get new MSR
1045 bf pfAltivecb,cinoDSS ; No Altivec here...
1047 dssall ; Stop streams
1050 cinoDSS: li r5,tlbieLock ; Get the TLBIE lock
1051 li r0,128 ; Get number of TLB entries
1053 li r6,0 ; Start at 0
1054 bf-- pf64Bitb,citlbhang ; Skip if 32-bit...
1055 li r0,1024 ; Get the number of TLB entries
1057 citlbhang: lwarx r2,0,r5 ; Get the TLBIE lock
1058 mr. r2,r2 ; Is it locked?
1059 bne- citlbhang ; It is locked, go wait...
1060 stwcx. r0,0,r5 ; Try to get it
1061 bne- citlbhang ; We was beat...
1063 mtctr r0 ; Set the CTR
1065 cipurgeTLB: tlbie r6 ; Purge this entry
1066 addi r6,r6,4096 ; Next page
1067 bdnz cipurgeTLB ; Do them all...
1069 mtcrf 0x80,r11 ; Set SMP capability
1070 sync ; Make sure all TLB purges are done
1071 eieio ; Order, order in the court
1073 bf pfSMPcapb,cinoSMP ; SMP incapable...
1075 tlbsync ; Sync all TLBs
1079 bf-- pf64Bitb,cinoSMP ; Skip if 32-bit...
1080 ptesync ; Wait for quiet again
1083 cinoSMP: stw r2,tlbieLock(0) ; Unlock TLBIE lock
1085 bt++ pf64Bitb,cin64 ; Skip if 64-bit...
1087 rlwinm. r0,r9,0,ice,dce ; Were either of the level 1s on?
1088 beq- cinoL1 ; No, no need to flush...
1090 rlwinm. r0,r11,0,pfL1fab,pfL1fab ; do we have L1 flush assist?
1091 beq ciswdl1 ; If no hw flush assist, go do by software...
1093 mfspr r8,msscr0 ; Get the memory system control register
1094 oris r8,r8,hi16(dl1hwfm) ; Turn on the hardware flush request
1096 mtspr msscr0,r8 ; Start the flush operation
1098 ciwdl1f: mfspr r8,msscr0 ; Get the control register again
1100 rlwinm. r8,r8,0,dl1hwf,dl1hwf ; Has the flush request been reset yet?
1101 bne ciwdl1f ; No, flush is still in progress...
1102 b ciinvdl1 ; Go invalidate l1...
1105 ; We need to either make this very complicated or to use ROM for
1106 ; the flush. The problem is that if during the following sequence a
1107 ; snoop occurs that invalidates one of the lines in the cache, the
1108 ; PLRU sequence will be altered making it possible to miss lines
1109 ; during the flush. So, we either need to dedicate an area of RAM
1110 ; to each processor, lock use of a RAM area, or use ROM. ROM is
1111 ; by far the easiest. Note that this is not an issue for machines
1112 ; that have harware flush assists.
1115 ciswdl1: lwz r0,pfl1dSize(r12) ; Get the level 1 cache size
1117 bf 31,cisnlck ; Skip if pfLClck not set...
1120 rlwinm r6,r4,0,0,l2pfes-1 ; ?
1121 mtspr msscr0,r6 ; Set it
1125 mfspr r8,ldstcr ; Save the LDSTCR
1126 li r2,1 ; Get a mask of 0x01
1127 lis r3,0xFFF0 ; Point to ROM
1128 rlwinm r11,r0,29,3,31 ; Get the amount of memory to handle all indexes
1130 li r6,0 ; Start here
1132 cisiniflsh: dcbf r6,r3 ; Flush each line of the range we use
1133 addi r6,r6,32 ; Bump to the next
1134 cmplw r6,r0 ; Have we reached the end?
1135 blt+ cisiniflsh ; Nope, continue initial flush...
1137 sync ; Make sure it is done
1139 addi r11,r11,-1 ; Get mask for index wrap
1140 li r6,0 ; Get starting offset
1142 cislckit: not r5,r2 ; Lock all but 1 way
1143 rlwimi r5,r8,0,0,23 ; Build LDSTCR
1144 mtspr ldstcr,r5 ; Lock a way
1145 sync ; Clear out memory accesses
1146 isync ; Wait for all
1149 cistouch: lwzx r10,r3,r6 ; Pick up some trash
1150 addi r6,r6,32 ; Go to the next index
1151 and. r0,r6,r11 ; See if we are about to do next index
1152 bne+ cistouch ; Nope, do more...
1154 sync ; Make sure it is all done
1157 sub r6,r6,r11 ; Back up to start + 1
1158 addi r6,r6,-1 ; Get it right
1160 cisflush: dcbf r3,r6 ; Flush everything out
1161 addi r6,r6,32 ; Go to the next index
1162 and. r0,r6,r11 ; See if we are about to do next index
1163 bne+ cisflush ; Nope, do more...
1165 sync ; Make sure it is all done
1169 rlwinm. r2,r2,1,24,31 ; Shift to next way
1170 bne+ cislckit ; Do this for all ways...
1172 mtspr ldstcr,r8 ; Slam back to original
1180 b cinoL1 ; Go on to level 2...
1183 cisnlck: rlwinm r2,r0,0,1,30 ; Double cache size
1184 add r0,r0,r2 ; Get 3 times cache size
1185 rlwinm r0,r0,26,6,31 ; Get 3/2 number of cache lines
1186 lis r3,0xFFF0 ; Dead recon ROM address for now
1187 mtctr r0 ; Number of lines to flush
1189 ciswfldl1a: lwz r2,0(r3) ; Flush anything else
1190 addi r3,r3,32 ; Next line
1191 bdnz ciswfldl1a ; Flush the lot...
1193 ciinvdl1: sync ; Make sure all flushes have been committed
1195 mfspr r8,hid0 ; Get the HID0 bits
1196 rlwinm r8,r8,0,dce+1,ice-1 ; Clear cache enables
1197 mtspr hid0,r8 ; and turn off L1 cache
1198 sync ; Make sure all is done
1201 ori r8,r8,lo16(icem|dcem|icfim|dcfim) ; Set the HID0 bits for enable, and invalidate
1205 mtspr hid0,r8 ; Start the invalidate and turn on cache
1206 rlwinm r8,r8,0,dcfi+1,icfi-1 ; Turn off the invalidate bits
1207 mtspr hid0,r8 ; Turn off the invalidate (needed for some older machines)
1213 ; Flush and disable the level 2
1215 mfsprg r10,2 ; need to check 2 features we did not put in CR
1216 rlwinm. r0,r10,0,pfL2b,pfL2b ; do we have L2?
1217 beq cinol2 ; No level 2 cache to flush
1219 mfspr r8,l2cr ; Get the L2CR
1220 lwz r3,pfl2cr(r12) ; Get the L2CR value
1221 rlwinm. r0,r8,0,l2e,l2e ; Was the L2 enabled?
1222 bne ciflushl2 ; Yes, force flush
1223 cmplwi r8, 0 ; Was the L2 all the way off?
1224 beq ciinvdl2 ; Yes, force invalidate
1225 lis r0,hi16(l2sizm|l2clkm|l2ramm|l2ohm) ; Get confiuration bits
1226 xor r2,r8,r3 ; Get changing bits?
1227 ori r0,r0,lo16(l2slm|l2dfm|l2bypm) ; More config bits
1228 and. r0,r0,r2 ; Did any change?
1229 bne- ciinvdl2 ; Yes, just invalidate and get PLL synced...
1232 rlwinm. r0,r10,0,pfL2fab,pfL2fab ; hardware-assisted L2 flush?
1233 beq ciswfl2 ; Flush not in hardware...
1235 mr r10,r8 ; Take a copy now
1237 bf 31,cinol2lck ; Skip if pfLClck not set...
1239 oris r10,r10,hi16(l2ionlym|l2donlym) ; Set both instruction- and data-only
1241 mtspr l2cr,r10 ; Lock out the cache
1245 cinol2lck: ori r10,r10,lo16(l2hwfm) ; Request flush
1246 sync ; Make sure everything is done
1248 mtspr l2cr,r10 ; Request flush
1250 cihwfl2: mfspr r10,l2cr ; Get back the L2CR
1251 rlwinm. r10,r10,0,l2hwf,l2hwf ; Is the flush over?
1252 bne+ cihwfl2 ; Nope, keep going...
1253 b ciinvdl2 ; Flush done, go invalidate L2...
1256 lwz r0,pfl2Size(r12) ; Get the L2 size
1257 oris r2,r8,hi16(l2dom) ; Set L2 to data only mode
1259 b ciswfl2doa ; Branch to next line...
1263 mtspr l2cr,r2 ; Disable L2
1266 b ciswfl2dod ; It is off, go invalidate it...
1269 b ciswfl2dob ; Branch to next...
1272 sync ; Finish memory stuff
1273 isync ; Stop speculation
1274 b ciswfl2doc ; Jump back up and turn on data only...
1276 rlwinm r0,r0,27,5,31 ; Get the number of lines
1277 lis r10,0xFFF0 ; Dead recon ROM for now
1278 mtctr r0 ; Set the number of lines
1280 ciswfldl2a: lwz r0,0(r10) ; Load something to flush something
1281 addi r10,r10,32 ; Next line
1282 bdnz ciswfldl2a ; Do the lot...
1284 ciinvdl2: rlwinm r3,r3,0,l2e+1,31 ; Clear the enable bit
1285 b cinla ; Branch to next line...
1288 cinlc: mtspr l2cr,r8 ; Disable L2
1291 b ciinvl2 ; It is off, go invalidate it...
1293 cinla: b cinlb ; Branch to next...
1295 cinlb: sync ; Finish memory stuff
1296 isync ; Stop speculation
1297 b cinlc ; Jump back up and turn off cache...
1302 cmplwi r3, 0 ; Should the L2 be all the way off?
1303 beq cinol2 ; Yes, done with L2
1305 oris r2,r8,hi16(l2im) ; Get the invalidate flag set
1307 mtspr l2cr,r2 ; Start the invalidate
1310 ciinvdl2a: mfspr r2,l2cr ; Get the L2CR
1311 mfsprg r0,2 ; need to check a feature in "non-volatile" set
1312 rlwinm. r0,r0,0,pfL2ib,pfL2ib ; flush in HW?
1313 beq ciinvdl2b ; Flush not in hardware...
1314 rlwinm. r2,r2,0,l2i,l2i ; Is the invalidate still going?
1315 bne+ ciinvdl2a ; Assume so, this will take a looong time...
1317 b cinol2 ; No level 2 cache to flush
1319 rlwinm. r2,r2,0,l2ip,l2ip ; Is the invalidate still going?
1320 bne+ ciinvdl2a ; Assume so, this will take a looong time...
1322 mtspr l2cr,r8 ; Turn off the invalidate request
1327 ; Flush and enable the level 3
1329 bf pfL3b,cinol3 ; No level 3 cache to flush
1331 mfspr r8,l3cr ; Get the L3CR
1332 lwz r3,pfl3cr(r12) ; Get the L3CR value
1333 rlwinm. r0,r8,0,l3e,l3e ; Was the L3 enabled?
1334 bne ciflushl3 ; Yes, force flush
1335 cmplwi r8, 0 ; Was the L3 all the way off?
1336 beq ciinvdl3 ; Yes, force invalidate
1337 lis r0,hi16(l3pem|l3sizm|l3dxm|l3clkm|l3spom|l3ckspm) ; Get configuration bits
1338 xor r2,r8,r3 ; Get changing bits?
1339 ori r0,r0,lo16(l3pspm|l3repm|l3rtm|l3cyam|l3dmemm|l3dmsizm) ; More config bits
1340 and. r0,r0,r2 ; Did any change?
1341 bne- ciinvdl3 ; Yes, just invalidate and get PLL synced...
1344 sync ; 7450 book says do this even though not needed
1345 mr r10,r8 ; Take a copy now
1347 bf 31,cinol3lck ; Skip if pfL23lck not set...
1349 oris r10,r10,hi16(l3iom) ; Set instruction-only
1350 ori r10,r10,lo16(l3donlym) ; Set data-only
1352 mtspr l3cr,r10 ; Lock out the cache
1356 cinol3lck: ori r10,r10,lo16(l3hwfm) ; Request flush
1357 sync ; Make sure everything is done
1359 mtspr l3cr,r10 ; Request flush
1361 cihwfl3: mfspr r10,l3cr ; Get back the L3CR
1362 rlwinm. r10,r10,0,l3hwf,l3hwf ; Is the flush over?
1363 bne+ cihwfl3 ; Nope, keep going...
1365 ciinvdl3: rlwinm r8,r3,0,l3e+1,31 ; Clear the enable bit
1366 sync ; Make sure of life, liberty, and justice
1367 mtspr l3cr,r8 ; Disable L3
1370 cmplwi r3, 0 ; Should the L3 be all the way off?
1371 beq cinol3 ; Yes, done with L3
1373 ori r8,r8,lo16(l3im) ; Get the invalidate flag set
1375 mtspr l3cr,r8 ; Start the invalidate
1377 ciinvdl3b: mfspr r8,l3cr ; Get the L3CR
1378 rlwinm. r8,r8,0,l3i,l3i ; Is the invalidate still going?
1379 bne+ ciinvdl3b ; Assume so...
1382 lwz r10, pfBootConfig(r12) ; ?
1383 rlwinm. r10, r10, 24, 28, 31 ; ?
1384 beq ciinvdl3nopdet ; ?
1388 rlwimi r2, r8, 0, 24, 31 ; ?
1389 subfic r10, r10, 32 ; ?
1391 ori r2, r2, 0x0080 ; ?
1394 mtspr l3pdet, r8 ; ?
1398 mfspr r8,l3cr ; Get the L3CR
1399 rlwinm r8,r8,0,l3clken+1,l3clken-1 ; Clear the clock enable bit
1400 mtspr l3cr,r8 ; Disable the clock
1403 ciinvdl3c: addi r2,r2,-1 ; ?
1407 mfspr r10,msssr0 ; ?
1408 rlwinm r10,r10,0,vgL3TAG+1,vgL3TAG-1 ; ?
1409 mtspr msssr0,r10 ; ?
1412 mtspr l3cr,r3 ; Enable it as desired
1415 mfsprg r0,2 ; need to check a feature in "non-volatile" set
1416 rlwinm. r0,r0,0,pfL2b,pfL2b ; is there an L2 cache?
1417 beq cinol2a ; No level 2 cache to enable
1419 lwz r3,pfl2cr(r12) ; Get the L2CR value
1420 cmplwi r3, 0 ; Should the L2 be all the way off?
1421 beq cinol2a : Yes, done with L2
1422 mtspr l2cr,r3 ; Enable it as desired
1426 ; Invalidate and turn on L1s
1430 bt 31,cinoexit ; Skip if pfLClck set...
1432 rlwinm r8,r9,0,dce+1,ice-1 ; Clear the I- and D- cache enables
1433 mtspr hid0,r8 ; Turn off dem caches
1436 ori r8,r9,lo16(icem|dcem|icfim|dcfim) ; Set the HID0 bits for enable, and invalidate
1437 rlwinm r9,r8,0,dcfi+1,icfi-1 ; Turn off the invalidate bits
1441 mtspr hid0,r8 ; Start the invalidate and turn on L1 cache
1443 cinoexit: mtspr hid0,r9 ; Turn off the invalidate (needed for some older machines) and restore entry conditions
1445 mtmsr r7 ; Restore MSR to entry
1451 ; Handle 64-bit architecture
1452 ; This processor can not run without caches, so we just push everything out
1453 ; and flush. It will be relativily clean afterwards
1459 li r10,hi16(dozem|napm|sleepm) ; Mask of power management bits we want cleared
1460 sldi r10,r10,32 ; Position the masks
1461 andc r9,r9,r10 ; Clean up the old power bits
1464 mtspr hid0,r4 ; Set up the HID
1465 mfspr r4,hid0 ; Yes, this is silly, keep it here
1466 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1467 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1468 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1469 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1470 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1473 mfspr r10,hid1 ; Save hid1
1474 mfspr r4,hid4 ; Save hid4
1475 mr r12,r10 ; Really save hid1
1476 mr r11,r4 ; Get a working copy of hid4
1479 eqv r2,r2,r2 ; Get all foxes
1481 rldimi r10,r0,55,7 ; Clear I$ prefetch bits (7:8)
1484 mtspr hid1,r10 ; Stick it
1485 mtspr hid1,r10 ; Stick it again
1488 rldimi r11,r2,38,25 ; Disable D$ prefetch (25:25)
1491 mtspr hid4,r11 ; Stick it
1494 li r3,8 ; Set bit 28+32
1495 sldi r3,r3,32 ; Make it bit 28
1496 or r3,r3,r11 ; Turn on the flash invalidate L1D$
1498 oris r5,r11,0x0600 ; Set disable L1D$ bits
1500 mtspr hid4,r3 ; Invalidate
1503 mtspr hid4,r5 ; Un-invalidate and disable L1D$
1506 lis r8,GUSModeReg ; Get the GUS mode ring address
1507 mfsprg r0,2 ; Get the feature flags
1508 ori r8,r8,0x8000 ; Set to read data
1509 rlwinm. r0,r0,pfSCOMFixUpb+1,31,31 ; Set shift if we need a fix me up
1513 mtspr scomc,r8 ; Request the GUS mode
1514 mfspr r11,scomd ; Get the GUS mode
1515 mfspr r8,scomc ; Get back the status (we just ignore it)
1519 sld r11,r11,r0 ; Fix up if needed
1521 ori r6,r11,lo16(GUSMdmapen) ; Set the bit that means direct L2 cache address
1522 lis r8,GUSModeReg ; Get GUS mode register address
1526 mtspr scomd,r6 ; Set that we want direct L2 mode
1527 mtspr scomc,r8 ; Tell GUS we want direct L2 mode
1528 mfspr r3,scomc ; Get back the status
1532 li r3,0 ; Clear start point
1534 cflushlp: lis r6,0x0040 ; Pick 4MB line as our target
1535 or r6,r6,r3 ; Put in the line offset
1536 lwz r5,0(r6) ; Load a line
1537 addis r6,r6,8 ; Roll bit 42:44
1538 lwz r5,0(r6) ; Load a line
1539 addis r6,r6,8 ; Roll bit 42:44
1540 lwz r5,0(r6) ; Load a line
1541 addis r6,r6,8 ; Roll bit 42:44
1542 lwz r5,0(r6) ; Load a line
1543 addis r6,r6,8 ; Roll bit 42:44
1544 lwz r5,0(r6) ; Load a line
1545 addis r6,r6,8 ; Roll bit 42:44
1546 lwz r5,0(r6) ; Load a line
1547 addis r6,r6,8 ; Roll bit 42:44
1548 lwz r5,0(r6) ; Load a line
1549 addis r6,r6,8 ; Roll bit 42:44
1550 lwz r5,0(r6) ; Load a line
1552 addi r3,r3,128 ; Next line
1553 andis. r5,r3,8 ; Have we done enough?
1554 beq++ cflushlp ; Not yet...
1558 lis r6,0x0040 ; Pick 4MB line as our target
1560 cflushx: dcbf 0,r6 ; Flush line and invalidate
1561 addi r6,r6,128 ; Next line
1562 andis. r5,r6,0x0080 ; Have we done enough?
1563 beq++ cflushx ; Keep on flushing...
1565 mr r3,r10 ; Copy current hid1
1566 rldimi r3,r2,54,9 ; Set force icbi match mode
1568 li r6,0 ; Set start if ICBI range
1570 mtspr hid1,r3 ; Stick it
1571 mtspr hid1,r3 ; Stick it again
1574 cflicbi: icbi 0,r6 ; Kill I$
1575 addi r6,r6,128 ; Next line
1576 andis. r5,r6,1 ; Have we done them all?
1577 beq++ cflicbi ; Not yet...
1579 lis r8,GUSModeReg ; Get GUS mode register address
1583 mtspr scomd,r11 ; Set that we do not want direct mode
1584 mtspr scomc,r8 ; Tell GUS we do not want direct mode
1585 mfspr r3,scomc ; Get back the status
1590 mtspr hid1,r12 ; Restore entry hid1
1591 mtspr hid1,r12 ; Stick it again
1595 mtspr hid4,r4 ; Restore entry hid4
1599 mtmsr r7 ; Restore MSR to entry
1605 /* Disables all caches
1607 * void cacheDisable(void)
1609 * Turns off all caches on the processor. They are not flushed.
1613 ; Force a line boundry here
1615 .globl EXT(cacheDisable)
1619 mfsprg r11,2 ; Get CPU specific features
1620 mtcrf 0x83,r11 ; Set feature flags
1622 bf pfAltivecb,cdNoAlt ; No vectors...
1624 dssall ; Stop streams
1628 btlr pf64Bitb ; No way to disable a 64-bit machine...
1630 mfspr r5,hid0 ; Get the hid
1631 rlwinm r5,r5,0,dce+1,ice-1 ; Clear the I- and D- cache enables
1632 mtspr hid0,r5 ; Turn off dem caches
1635 rlwinm. r0,r11,0,pfL2b,pfL2b ; is there an L2?
1636 beq cdNoL2 ; Skip if no L2...
1638 mfspr r5,l2cr ; Get the L2
1639 rlwinm r5,r5,0,l2e+1,31 ; Turn off enable bit
1641 b cinlaa ; Branch to next line...
1644 cinlcc: mtspr l2cr,r5 ; Disable L2
1647 b cdNoL2 ; It is off, we are done...
1649 cinlaa: b cinlbb ; Branch to next...
1651 cinlbb: sync ; Finish memory stuff
1652 isync ; Stop speculation
1653 b cinlcc ; Jump back up and turn off cache...
1657 bf pfL3b,cdNoL3 ; Skip down if no L3...
1659 mfspr r5,l3cr ; Get the L3
1660 rlwinm r5,r5,0,l3e+1,31 ; Turn off enable bit
1661 rlwinm r5,r5,0,l3clken+1,l3clken-1 ; Turn off cache enable bit
1662 mtspr l3cr,r5 ; Disable the caches
1669 /* Initialize processor thermal monitoring
1670 * void ml_thrm_init(void)
1672 * Build initial TAU registers and start them all going.
1673 * We ca not do this at initial start up because we need to have the processor frequency first.
1674 * And just why is this in assembler when it does not have to be?? Cause I am just too
1675 * lazy to open up a "C" file, thats why.
1678 ; Force a line boundry here
1680 .globl EXT(ml_thrm_init)
1684 mfsprg r12,0 ; Get the per_proc blok
1685 lis r11,hi16(EXT(gPEClockFrequencyInfo)) ; Get top of processor information
1686 mfsprg r10,2 ; Get CPU specific features
1687 ori r11,r11,lo16(EXT(gPEClockFrequencyInfo)) ; Get bottom of processor information
1688 mtcrf 0x40,r10 ; Get the installed features
1690 li r3,lo16(thrmtidm|thrmvm) ; Set for lower-than thermal event at 0 degrees
1691 bflr pfThermalb ; No thermal monitoring on this cpu
1692 mtspr thrm1,r3 ; Do it
1694 lwz r3,thrmthrottleTemp(r12) ; Get our throttle temprature
1695 rlwinm r3,r3,31-thrmthre,thrmthrs,thrmthre ; Position it
1696 ori r3,r3,lo16(thrmvm) ; Set for higher-than event
1697 mtspr thrm2,r3 ; Set it
1699 lis r4,hi16(1000000) ; Top of million
1701 ; Note: some CPU manuals say this is processor clocks, some say bus rate. The latter
1702 ; makes more sense because otherwise we can not get over about 400MHz.
1704 lwz r3,PECFIcpurate(r11) ; Get the processor speed
1706 lwz r3,PECFIbusrate(r11) ; Get the bus speed
1708 ori r4,r4,lo16(1000000) ; Bottom of million
1709 lis r7,hi16(thrmsitvm>>1) ; Get top of highest possible value
1710 divwu r3,r3,r4 ; Get number of cycles per microseconds
1711 ori r7,r7,lo16(thrmsitvm>>1) ; Get the bottom of the highest possible value
1712 addi r3,r3,1 ; Insure we have enough
1713 mulli r3,r3,20 ; Get 20 microseconds worth of cycles
1714 cmplw r3,r7 ; Check against max
1715 ble+ smallenuf ; It is ok...
1718 smallenuf: rlwinm r3,r3,31-thrmsitve,thrmsitvs,thrmsitve ; Position
1719 ori r3,r3,lo16(thrmem) ; Enable with at least 20micro sec sample
1720 stw r3,thrm3val(r12) ; Save this in case we need it later
1721 mtspr thrm3,r3 ; Do it
1725 /* Set thermal monitor bounds
1726 * void ml_thrm_set(unsigned int low, unsigned int high)
1728 * Set TAU to interrupt below low and above high. A value of
1729 * zero disables interruptions in that direction.
1732 ; Force a line boundry here
1734 .globl EXT(ml_thrm_set)
1738 mfmsr r0 ; Get the MSR
1739 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1740 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1741 rlwinm r6,r0,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Clear EE bit
1745 mfsprg r12,0 ; Get the per_proc blok
1747 rlwinm. r6,r3,31-thrmthre,thrmthrs,thrmthre ; Position it and see if enabled
1748 mfsprg r9,2 ; Get CPU specific features
1749 stw r3,thrmlowTemp(r12) ; Set the low temprature
1750 mtcrf 0x40,r9 ; See if we can thermal this machine
1751 rlwinm r9,r9,(((31-thrmtie)+(pfThermIntb+1))&31),thrmtie,thrmtie ; Set interrupt enable if this machine can handle it
1752 bf pfThermalb,tsetcant ; No can do...
1753 beq tsetlowo ; We are setting the low off...
1754 ori r6,r6,lo16(thrmtidm|thrmvm) ; Set the lower-than and valid bit
1755 or r6,r6,r9 ; Set interruption request if supported
1757 tsetlowo: mtspr thrm1,r6 ; Cram the register
1759 rlwinm. r6,r4,31-thrmthre,thrmthrs,thrmthre ; Position it and see if enabled
1760 stw r4,thrmhighTemp(r12) ; Set the high temprature
1761 beq tsethigho ; We are setting the high off...
1762 ori r6,r6,lo16(thrmvm) ; Set valid bit
1763 or r6,r6,r9 ; Set interruption request if supported
1765 tsethigho: mtspr thrm2,r6 ; Cram the register
1767 tsetcant: mtmsr r0 ; Reenable interruptions
1770 /* Read processor temprature
1771 * unsigned int ml_read_temp(void)
1775 ; Force a line boundry here
1777 .globl EXT(ml_read_temp)
1781 mfmsr r9 ; Save the MSR
1782 li r5,15 ; Starting point for ranging (start at 15 so we do not overflow)
1783 rlwinm r9,r9,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1784 rlwinm r9,r9,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1785 rlwinm r8,r9,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Turn off interruptions
1786 mfsprg r7,2 ; Get CPU specific features
1787 mtmsr r8 ; Do not allow interruptions
1788 mtcrf 0x40,r7 ; See if we can thermal this machine
1789 bf pfThermalb,thrmcant ; No can do...
1791 mfspr r11,thrm1 ; Save thrm1
1793 thrmrange: rlwinm r4,r5,31-thrmthre,thrmthrs,thrmthre ; Position it
1794 ori r4,r4,lo16(thrmtidm|thrmvm) ; Flip on the valid bit and make comparision for less than
1796 mtspr thrm1,r4 ; Set the test value
1798 thrmreada: mfspr r3,thrm1 ; Get the thermal register back
1799 rlwinm. r0,r3,0,thrmtiv,thrmtiv ; Has it settled yet?
1800 beq+ thrmreada ; Nope...
1802 rlwinm. r0,r3,0,thrmtin,thrmtin ; Are we still under the threshold?
1803 bne thrmsearch ; No, we went over...
1805 addi r5,r5,16 ; Start by trying every 16 degrees
1806 cmplwi r5,127 ; Have we hit the max?
1807 blt- thrmrange ; Got some more to do...
1809 thrmsearch: rlwinm r4,r5,31-thrmthre,thrmthrs,thrmthre ; Position it
1810 ori r4,r4,lo16(thrmtidm|thrmvm) ; Flip on the valid bit and make comparision for less than
1812 mtspr thrm1,r4 ; Set the test value
1814 thrmread: mfspr r3,thrm1 ; Get the thermal register back
1815 rlwinm. r0,r3,0,thrmtiv,thrmtiv ; Has it settled yet?
1816 beq+ thrmread ; Nope...
1818 rlwinm. r0,r3,0,thrmtin,thrmtin ; Are we still under the threshold?
1819 beq thrmdone ; No, we hit it...
1820 addic. r5,r5,-1 ; Go down a degree
1821 bge+ thrmsearch ; Try again (until we are below freezing)...
1823 thrmdone: addi r3,r5,1 ; Return the temprature (bump it up to make it correct)
1824 mtspr thrm1,r11 ; Restore the thermal register
1825 mtmsr r9 ; Re-enable interruptions
1828 thrmcant: eqv r3,r3,r3 ; Return bogus temprature because we can not read it
1829 mtmsr r9 ; Re-enable interruptions
1832 /* Throttle processor speed up or down
1833 * unsigned int ml_throttle(unsigned int step)
1835 * Returns old speed and sets new. Both step and return are values from 0 to
1836 * 255 that define number of throttle steps, 0 being off and "ictcfim" is max * 2.
1840 ; Force a line boundry here
1842 .globl EXT(ml_throttle)
1846 mfmsr r9 ; Save the MSR
1847 rlwinm r9,r9,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1848 rlwinm r9,r9,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1849 rlwinm r8,r9,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Turn off interruptions
1850 cmplwi r3,lo16(ictcfim>>1) ; See if we are going too far
1851 mtmsr r8 ; Do not allow interruptions
1853 ble+ throtok ; Throttle value is ok...
1854 li r3,lo16(ictcfim>>1) ; Set max
1856 throtok: rlwinm. r4,r3,1,ictcfib,ictcfie ; Set the throttle
1857 beq throtoff ; Skip if we are turning it off...
1858 ori r4,r4,lo16(thrmvm) ; Turn on the valid bit
1860 throtoff: mfspr r3,ictc ; Get the old throttle
1861 mtspr ictc,r4 ; Set the new
1862 rlwinm r3,r3,31,1,31 ; Shift throttle value over
1863 mtmsr r9 ; Restore interruptions
1867 ** ml_get_timebase()
1869 ** Entry - R3 contains pointer to 64 bit structure.
1871 ** Exit - 64 bit structure filled in.
1874 ; Force a line boundry here
1876 .globl EXT(ml_get_timebase)
1878 LEXT(ml_get_timebase)
1893 * unsigned int cpu_number(void)
1895 * Returns the current cpu number.
1899 .globl EXT(cpu_number)
1903 mfsprg r7,0 ; Get per-proc block
1904 lhz r3,PP_CPU_NUMBER(r7) ; Get CPU number
1908 * thread_t current_thread(void)
1910 * Return the active thread for both inside and outside osfmk consumption
1913 .globl EXT(current_thread)
1915 LEXT(current_thread)
1918 lwz r3,ACT_THREAD(r3)
1922 * set_machine_current_thread(thread_t)
1924 * Set the active thread
1927 .globl EXT(set_machine_current_thread)
1929 LEXT(set_machine_current_thread)
1931 mfsprg r6,0 ; Get the per_proc
1932 stw r3,PP_ACTIVE_THREAD(r6) ; Set the active thread
1936 * void set_machine_current_act(thread_act_t)
1938 * Set the current activation
1941 .globl EXT(set_machine_current_act)
1943 LEXT(set_machine_current_act)
1945 mtsprg 1,r3 ; Set spr1 with the active thread
1949 * thread_act_t current_act(void)
1951 * Return the current activation
1954 .globl EXT(current_act)
1962 * cpu_data_t* get_cpu_data(void)
1964 * Return the cpu_data
1967 .globl EXT(get_cpu_data)
1971 mfsprg r3,0 ; Get the per_proc
1972 addi r3,r3,PP_ACTIVE_THREAD ; Get the pointer to the CPU data from per proc
1979 ; Force a line boundry here
1981 .globl EXT(ml_sense_nmi)
1988 ** ml_set_processor_speed()
1991 ; Force a line boundry here
1993 .globl EXT(ml_set_processor_speed)
1995 LEXT(ml_set_processor_speed)
1996 mfsprg r5, 0 ; Get the per_proc_info
1998 cmpli cr0, r3, 0 ; Turn off BTIC before low speed
2000 mfspr r4, hid0 ; Get the current hid0 value
2001 rlwinm r4, r4, 0, btic+1, btic-1 ; Clear the BTIC bit
2003 mtspr hid0, r4 ; Set the new hid0 value
2008 mfspr r4, hid1 ; Get the current PLL settings
2009 rlwimi r4, r3, 31-hid1ps, hid1ps, hid1ps ; Copy the PLL Select bit
2010 stw r4, pfHID1(r5) ; Save the new hid1 value
2011 mtspr hid1, r4 ; Select desired PLL
2013 cmpli cr0, r3, 0 ; Restore BTIC after high speed
2015 lwz r4, pfHID0(r5) ; Load the hid0 value
2017 mtspr hid0, r4 ; Set the hid0 value
2025 ** ml_set_processor_voltage()
2028 ; Force a line boundry here
2030 .globl EXT(ml_set_processor_voltage)
2032 LEXT(ml_set_processor_voltage)
2033 mfspr r4, hid2 ; Get HID2 value
2034 rlwimi r4, r3, 31-hid2vmin, hid2vmin, hid2vmin ; Insert the voltage mode bit
2035 mtspr hid2, r4 ; Set the voltage mode
2036 sync ; Make sure it is done
projects / apple / xnu.git / blob