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[apple/xnu.git] / osfmk / ppc / Firmware.s
1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
7 *
8 * This file contains Original Code and/or Modifications of Original Code
9 * as defined in and that are subject to the Apple Public Source License
10 * Version 2.0 (the 'License'). You may not use this file except in
11 * compliance with the License. Please obtain a copy of the License at
12 * http://www.opensource.apple.com/apsl/ and read it before using this
13 * file.
14 *
15 * The Original Code and all software distributed under the License are
16 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
17 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
18 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
20 * Please see the License for the specific language governing rights and
21 * limitations under the License.
22 *
23 * @APPLE_LICENSE_HEADER_END@
24 */
25 /*
26 * @OSF_FREE_COPYRIGHT@
27 */
28 /*
29 * @APPLE_FREE_COPYRIGHT@
30 */
31
32 /*
33 Firmware.s
34
35 Handle things that should be treated as an extension of the hardware
36
37 Lovingly crafted by Bill Angell using traditional methods and only natural or recycled materials.
38 No animal products are used other than rendered otter bile and deep fried pork lard.
39
40 */
41
42 #include <cpus.h>
43 #include <ppc/asm.h>
44 #include <ppc/proc_reg.h>
45 #include <ppc/spec_reg.h>
46 #include <ppc/exception.h>
47 #include <mach/machine/vm_param.h>
48 #include <assym.s>
49
50
51 /*
52 * Here we generate the table of supported firmware calls
53 */
54
55
56
57 .data
58 .align 5 /* Line up on cache line */
59
60 .globl EXT(FWtable)
61
62 EXT(FWtable):
63
64 .globl CutTrace /* Let everyone know 'bout it */
65 .set CutTrace,(.-EXT(FWtable))/4|0x80000000 /* Call number for CutTrace */
66 .long callUnimp /* This was already handled in lowmem_vectors */
67
68 #include <ppc/FirmwareCalls.h>
69
70 .set EXT(FirmwareCnt), (.-EXT(FWtable))/4 /* Get the top number */
71
72 .text
73
74 #define SIMPLESCC 1
75 #define NOTQUITEASSIMPLE 1
76 /*
77 * This routine handles the firmware call routine. It must be entered with IR and DR off,
78 * interruptions disabled, and in supervisor state.
79 *
80 * When we enter, we expect R0 to have call number, and LR
81 * to point to the return. Also, all registers saved in savearea in R13.
82 * R3 is as passed in by the user. All others must be gotten from the save area
83 */
84
85
86 .align 5
87 .globl EXT(FirmwareCall)
88
89 LEXT(FirmwareCall)
90
91 rlwinm r1,r0,2,1,29 /* Clear out bit 0 and multiply by 4 */
92 lis r12,HIGH_ADDR(EXT(FWtable)) /* Get the high part of the firmware call table */
93 cmplwi r1,EXT(FirmwareCnt)*4 /* Is it a valid firmware call number */
94 ori r12,r12,LOW_ADDR(EXT(FWtable)) /* Now the low part */
95 ble+ goodCall /* Yeah, it is... */
96
97 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
98 b EXT(FCReturn) ; Bye dudes...
99
100 goodCall: mfsprg r10,0 /* Make sure about the per_proc block */
101 lwzx r1,r1,r12 /* Pick up the address of the routine */
102 lwz r4,saver4+4(r13) /* Pass in caller's R4 */
103 lwz r5,saver5+4(r13) /* Pass in caller's R5 */
104 rlwinm. r1,r1,0,0,29 /* Make sure the flag bits are clear */
105
106 mtlr r1 /* Put it in the LR */
107 beq- callUnimp /* This one was unimplimented... */
108
109 blrl /* Call the routine... */
110
111 stw r3,saver3+4(r13) /* Pass back the return code to caller */
112 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
113 b EXT(FCReturn) ; Bye dudes...
114
115 callUnimp: li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
116 b EXT(FCReturn) ; Bye dudes...
117
118 /*
119 * This routine is used to store using a real address. It stores parmeter1 at parameter2.
120 */
121
122 .align 5
123 .globl EXT(StoreReal)
124
125 LEXT(StoreReal)
126
127 lis r0,HIGH_ADDR(StoreRealCall) /* Get the top part of the SC number */
128 ori r0,r0,LOW_ADDR(StoreRealCall) /* and the bottom part */
129 sc /* Do it to it */
130 blr /* Bye bye, Birdie... */
131
132 .align 5
133 .globl EXT(StoreRealLL)
134
135 LEXT(StoreRealLL)
136
137 stw r3,0(r4) /* Store the word */
138 blr /* Leave... */
139
140 /*
141 * This routine is used to clear a range of physical pages.
142 */
143
144 .align 5
145 .globl EXT(ClearReal)
146
147 LEXT(ClearReal)
148
149 lis r0,HIGH_ADDR(ClearRealCall) /* Get the top part of the SC number */
150 ori r0,r0,LOW_ADDR(ClearRealCall) /* and the bottom part */
151 sc /* Do it to it */
152 blr /* Bye bye, Birdie... */
153
154
155 .align 5
156 .globl EXT(ClearRealLL)
157
158 LEXT(ClearRealLL)
159
160 /*
161 * We take the first parameter as a physical address. The second is the length in bytes.
162 * Being crazy, I'll round the address down, and the length up. We could end up clearing
163 * an extra page at the start and one at the end, but we don't really care. If someone
164 * is stupid enough to give me unaligned addresses and lengths, I am just arrogant enough
165 * to take them at their word and to hell with them.
166 */
167
168 neg r5,r3 /* Negate the address */
169 addi r4,r4,4095 /* Round length up */
170 rlwinm r5,r5,0,20,31 /* Save extra length */
171 rlwinm r3,r3,0,0,19 /* Round the page on down */
172 add r4,r4,r5 /* Add up all extra lengths */
173 li r6,32 /* Get a displacement */
174 rlwinm r4,r4,0,0,19 /* Round the length back down */
175
176 clrloop: subi r4,r4,32 /* Back off a cache line */
177 dcbz 0,r3 /* Do the even line */
178 sub. r4,r4,r6 /* Back off a second time (we only do this to generate a CR */
179 dcbz r6,r3 /* Clear the even line */
180 addi r3,r3,64 /* Move up to every other line */
181 bgt+ clrloop /* Go until we've done it all... */
182
183 blr /* Leave... */
184 /*
185 * This routine will read in 32 byte of real storage.
186 */
187
188 .align 5
189 .globl EXT(ReadReal)
190
191 LEXT(ReadReal)
192
193 mfsprg r9,2 ; Get the features
194 mfmsr r0 ; Get the MSR
195 li r8,lo16(MASK(MSR_DR)) ; Get the DR bit
196 rlwinm. r9,r9,0,pf64Bitb,pf64Bitb ; Are we 64-bit?
197 ori r8,r8,lo16(MASK(MSR_EE)) ; Add in the EE bit
198 li r7,1 ; Get set for it
199 andc r8,r0,r8 ; Turn off EE and DR
200 bt-- cr0_eq,rr32a ; Yes, we are...
201
202 rldimi r8,r7,63,MSR_SF_BIT ; Set SF bit (bit 0)
203 sldi r3,r3,32 ; Slide on over for true 64-bit address
204 mtmsrd r8
205 isync
206 or r3,r3,r4 ; Join top and bottom of address
207 mr r4,r5 ; Set destination address
208 b rrJoina ; Join on up...
209
210 rr32a: mr r3,r4 ; Position bottom of long long
211 mr r4,r5 ; Set destination address
212 mtmsr r8 /* Disable EE and DR */
213 isync /* Just make sure about it */
214
215 rrJoina: lwz r5,0(r3) /* Get word 0 */
216 lwz r6,4(r3) /* Get word 1 */
217 lwz r7,8(r3) /* Get word 2 */
218 lwz r8,12(r3) /* Get word 3 */
219 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
220 lwz r9,16(r3) /* Get word 4 */
221 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
222 lwz r10,20(r3) /* Get word 5 */
223 andc r0,r0,r2 ; Clear VEC and FP enables
224 lwz r11,24(r3) /* Get word 6 */
225 lwz r12,28(r3) /* Get word 7 */
226
227 bt-- cr0_eq,rr32b ; We are not 64-bit...
228
229 mtmsrd r0
230 isync
231 b rrJoinb ; Join on up...
232
233 rr32b: mtmsr r0 /* Restore original machine state */
234 isync /* Insure goodness */
235
236 rrJoinb: stw r5,0(r4) /* Set word 0 */
237 stw r6,4(r4) /* Set word 1 */
238 stw r7,8(r4) /* Set word 2 */
239 stw r8,12(r4) /* Set word 3 */
240 stw r9,16(r4) /* Set word 4 */
241 stw r10,20(r4) /* Set word 5 */
242 stw r11,24(r4) /* Set word 6 */
243 stw r12,28(r4) /* Set word 7 */
244
245 blr
246
247
248 /*
249 * This routine is used to load all 4 DBATs.
250 */
251
252 .align 5
253 .globl EXT(LoadDBATs)
254
255 LEXT(LoadDBATs)
256
257
258 lis r0,HIGH_ADDR(LoadDBATsCall) /* Top half of LoadDBATsCall firmware call number */
259 ori r0,r0,LOW_ADDR(LoadDBATsCall) /* Bottom half */
260 sc /* Do it to it */
261
262 blr /* Bye bye, Birdie... */
263
264
265 .align 5
266 .globl EXT(xLoadDBATsLL)
267
268 LEXT(xLoadDBATsLL)
269
270 lwz r4,0(r3) /* Get DBAT 0 high */
271 lwz r5,4(r3) /* Get DBAT 0 low */
272 lwz r6,8(r3) /* Get DBAT 1 high */
273 lwz r7,12(r3) /* Get DBAT 1 low */
274 lwz r8,16(r3) /* Get DBAT 2 high */
275 lwz r9,20(r3) /* Get DBAT 2 low */
276 lwz r10,24(r3) /* Get DBAT 3 high */
277 lwz r11,28(r3) /* Get DBAT 3 low */
278
279 sync /* Common decency and the state law require that you wash your hands */
280 mtdbatu 0,r4 /* Load DBAT 0 high */
281 mtdbatl 0,r5 /* Load DBAT 0 low */
282 mtdbatu 1,r6 /* Load DBAT 1 high */
283 mtdbatl 1,r7 /* Load DBAT 1 low */
284 mtdbatu 2,r8 /* Load DBAT 2 high */
285 mtdbatl 2,r9 /* Load DBAT 2 low */
286 mtdbatu 3,r10 /* Load DBAT 3 high */
287 mtdbatl 3,r11 /* Load DBAT 3 low */
288 sync /* Make sure it's done */
289 isync /* Toss out anything new */
290
291 blr /* Leave... */
292
293 /*
294 * This routine is used to load all 4 IBATs.
295 */
296
297 .align 5
298 .globl EXT(LoadIBATs)
299
300 LEXT(LoadIBATs)
301
302
303 lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of LoadIBATsCall firmware call number */
304 ori r0,r0,LOW_ADDR(LoadIBATsCall) /* Bottom half */
305 sc /* Do it to it */
306 blr /* Bye bye, Birdie... */
307
308 .align 5
309 .globl EXT(xLoadIBATsLL)
310
311 LEXT(xLoadIBATsLL)
312
313 lwz r4,0(r3) /* Get IBAT 0 high */
314 lwz r5,4(r3) /* Get IBAT 0 low */
315 lwz r6,8(r3) /* Get IBAT 1 high */
316 lwz r7,12(r3) /* Get IBAT 1 low */
317 lwz r8,16(r3) /* Get IBAT 2 high */
318 lwz r9,20(r3) /* Get IBAT 2 low */
319 lwz r10,24(r3) /* Get IBAT 3 high */
320 lwz r11,28(r3) /* Get IBAT 3 low */
321
322 sync /* Common decency and the state law require that you wash your hands */
323 mtibatu 0,r4 /* Load IBAT 0 high */
324 mtibatl 0,r5 /* Load IBAT 0 low */
325 mtibatu 1,r6 /* Load IBAT 1 high */
326 mtibatl 1,r7 /* Load IBAT 1 low */
327 mtibatu 2,r8 /* Load IBAT 2 high */
328 mtibatl 2,r9 /* Load IBAT 2 low */
329 mtibatu 3,r10 /* Load IBAT 3 high */
330 mtibatl 3,r11 /* Load IBAT 3 low */
331 sync /* Make sure it's done */
332 isync /* Toss out anything new */
333
334 blr /* Leave... */
335
336
337 /*
338 * This is the glue to call the CutTrace firmware call
339 */
340
341 .align 5
342 .globl EXT(dbgTrace)
343
344 LEXT(dbgTrace)
345
346 lis r0,HIGH_ADDR(CutTrace) /* Top half of CreateFakeIO firmware call number */
347 ori r0,r0,LOW_ADDR(CutTrace) /* Bottom half */
348 sc /* Do it to it */
349 blr /* Bye bye, Birdie... */
350
351 /*
352 * This is the glue to create a fake I/O interruption
353 */
354
355 .align 5
356 .globl EXT(CreateFakeIO)
357
358 LEXT(CreateFakeIO)
359
360 lis r0,HIGH_ADDR(CreateFakeIOCall) /* Top half of CreateFakeIO firmware call number */
361 ori r0,r0,LOW_ADDR(CreateFakeIOCall) /* Bottom half */
362 sc /* Do it to it */
363 blr /* Bye bye, Birdie... */
364
365 /*
366 * This is the glue to create a fake Dec interruption
367 */
368
369 .align 5
370 .globl EXT(CreateFakeDEC)
371
372 LEXT(CreateFakeDEC)
373
374 #if 0
375 mflr r4 ; (TEST/DEBUG)
376 bl EXT(ml_sense_nmi) ; (TEST/DEBUG)
377 mtlr r4 ; (TEST/DEBUG)
378 #endif
379
380 lis r0,HIGH_ADDR(CreateFakeDECCall) /* Top half of CreateFakeDEC firmware call number */
381 ori r0,r0,LOW_ADDR(CreateFakeDECCall) /* Bottom half */
382 sc /* Do it to it */
383 blr /* Bye bye, Birdie... */
384
385
386 /*
387 * This is the glue to create a shutdown context
388 */
389
390 .align 5
391 .globl EXT(CreateShutdownCTX)
392
393 LEXT(CreateShutdownCTX)
394
395 lis r0,HIGH_ADDR(CreateShutdownCTXCall) /* Top half of CreateFakeIO firmware call number */
396 ori r0,r0,LOW_ADDR(CreateShutdownCTXCall) /* Bottom half */
397 sc /* Do it to it */
398 blr /* Bye bye, Birdie... */
399
400 /*
401 * This is the glue to choke system
402 */
403
404 .align 5
405 .globl EXT(ChokeSys)
406
407 LEXT(ChokeSys)
408
409 lis r0,HIGH_ADDR(Choke) /* Top half of Choke firmware call number */
410 ori r0,r0,LOW_ADDR(Choke) /* Bottom half */
411 sc /* Do it to it */
412 blr /* Bye bye, Birdie... */
413
414 /*
415 * Used to initialize the SCC for debugging output
416 */
417
418
419 .align 5
420 .globl EXT(fwSCCinit)
421
422 LEXT(fwSCCinit)
423
424 mfmsr r8 /* Save the MSR */
425 mr. r3,r3 /* See if printer or modem */
426 rlwinm r12,r8,0,28,25 /* Turn off translation */
427 lis r10,0xF301 /* Set the top part */
428 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
429 #if 0
430 mtmsr r12 /* Smash the MSR */
431 isync /* Make it clean */
432 #endif
433
434 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
435 beq+ fwSCCprnt /* It sure are... */
436 ori r10,r10,0x0002 /* Move it over to the modem port */
437
438 fwSCCprnt: dcbf 0,r10 /* Insure it is out */
439 sync
440 eieio
441 dcbi 0,r10 /* Toss it */
442 sync
443
444
445 li r7,0x09 /* Set the register */
446 stb r7,0(r10) /* Set the register */
447 dcbf 0,r10 /* Force it out */
448 sync /* Make sure it's out there */
449 dcbi 0,r10
450 eieio
451
452 li r7,0x80 /* Reset channel A */
453 stb r7,0(r10) /* Set the register */
454 dcbf 0,r10 /* Force it out */
455 sync /* Make sure it's out there */
456 dcbi 0,r10
457 eieio
458
459 li r7,0x04 /* Set the register */
460 stb r7,0(r10) /* Set the register */
461 dcbf 0,r10 /* Force it out */
462 sync /* Make sure it's out there */
463 dcbi 0,r10
464 eieio
465
466 li r7,0x44 /* x16 clock, 1 stop bit */
467 stb r7,0(r10) /* Set the register */
468 dcbf 0,r10 /* Force it out */
469 sync /* Make sure it's out there */
470 dcbi 0,r10
471 eieio
472
473 li r7,0x03 /* Set the register */
474 stb r7,0(r10) /* Set the register */
475 dcbf 0,r10 /* Force it out */
476 sync /* Make sure it's out there */
477 dcbi 0,r10
478 eieio
479
480 li r7,0xC0 /* 8 bits per char */
481 stb r7,0(r10) /* Set the register */
482 dcbf 0,r10 /* Force it out */
483 sync /* Make sure it's out there */
484 dcbi 0,r10
485 eieio
486
487 li r7,0x05 /* Set the register */
488 stb r7,0(r10) /* Set the register */
489 dcbf 0,r10 /* Force it out */
490 sync /* Make sure it's out there */
491 dcbi 0,r10
492 eieio
493
494 li r7,0xE2 /* DTR mode, 8bit/char */
495 stb r7,0(r10) /* Set the register */
496 dcbf 0,r10 /* Force it out */
497 sync /* Make sure it's out there */
498 dcbi 0,r10
499 eieio
500
501 li r7,0x02 /* Set the register */
502 stb r7,0(r10) /* Set the register */
503 dcbf 0,r10 /* Force it out */
504 sync /* Make sure it's out there */
505 dcbi 0,r10
506 eieio
507
508 li r7,0x00 /* Vector 0 */
509 stb r7,0(r10) /* Set the register */
510 dcbf 0,r10 /* Force it out */
511 sync /* Make sure it's out there */
512 dcbi 0,r10
513 eieio
514
515 li r7,0x0A /* Set the register */
516 stb r7,0(r10) /* Set the register */
517 dcbf 0,r10 /* Force it out */
518 sync /* Make sure it's out there */
519 dcbi 0,r10
520 eieio
521
522 li r7,0x00 /* Clear misc controls */
523 stb r7,0(r10) /* Set the register */
524 dcbf 0,r10 /* Force it out */
525 sync /* Make sure it's out there */
526 dcbi 0,r10
527 eieio
528
529 li r7,0x0B /* Set the register */
530 stb r7,0(r10) /* Set the register */
531 dcbf 0,r10 /* Force it out */
532 sync /* Make sure it's out there */
533 dcbi 0,r10
534 eieio
535
536 li r7,0x50 /* B/R gen T/R */
537 stb r7,0(r10) /* Set the register */
538 dcbf 0,r10 /* Force it out */
539 sync /* Make sure it's out there */
540 dcbi 0,r10
541 eieio
542
543 li r7,0x0C /* Set the register */
544 stb r7,0(r10) /* Set the register */
545 dcbf 0,r10 /* Force it out */
546 sync /* Make sure it's out there */
547 dcbi 0,r10
548 eieio
549
550 li r7,0x0A /* 9600 baud low */
551 stb r7,0(r10) /* Set the register */
552 dcbf 0,r10 /* Force it out */
553 sync /* Make sure it's out there */
554 dcbi 0,r10
555 eieio
556
557 li r7,0x0D /* Set the register */
558 stb r7,0(r10) /* Set the register */
559 dcbf 0,r10 /* Force it out */
560 sync /* Make sure it's out there */
561 dcbi 0,r10
562 eieio
563
564 li r7,0x00 /* 9600 baud high */
565 stb r7,0(r10) /* Set the register */
566 dcbf 0,r10 /* Force it out */
567 sync /* Make sure it's out there */
568 dcbi 0,r10
569 eieio
570
571 li r7,0x03 /* Set the register */
572 stb r7,0(r10) /* Set the register */
573 dcbf 0,r10 /* Force it out */
574 sync /* Make sure it's out there */
575 dcbi 0,r10
576 eieio
577
578 li r7,0xC1 /* 8 bits/char, Rx enable */
579 stb r7,0(r10) /* Set the register */
580 dcbf 0,r10 /* Force it out */
581 sync /* Make sure it's out there */
582 dcbi 0,r10
583 eieio
584
585 li r7,0x05 /* Set the register */
586 stb r7,0(r10) /* Set the register */
587 dcbf 0,r10 /* Force it out */
588 sync /* Make sure it's out there */
589 dcbi 0,r10
590 eieio
591
592 li r7,0xEA /* 8 bits/char, Tx enable */
593 stb r7,0(r10) /* Set the register */
594 dcbf 0,r10 /* Force it out */
595 sync /* Make sure it's out there */
596 dcbi 0,r10
597 eieio
598
599 li r7,0x0E /* Set the register */
600 stb r7,0(r10) /* Set the register */
601 dcbf 0,r10 /* Force it out */
602 sync /* Make sure it's out there */
603 dcbi 0,r10
604 eieio
605
606 li r7,0x01 /* BR rate gen enable */
607 stb r7,0(r10) /* Set the register */
608 dcbf 0,r10 /* Force it out */
609 sync /* Make sure it's out there */
610 dcbi 0,r10
611 eieio
612
613 li r7,0x0F /* Set the register */
614 stb r7,0(r10) /* Set the register */
615 dcbf 0,r10 /* Force it out */
616 sync /* Make sure it's out there */
617 dcbi 0,r10
618 eieio
619
620 li r7,0x00 /* ints off */
621 stb r7,0(r10) /* Set the register */
622 dcbf 0,r10 /* Force it out */
623 sync /* Make sure it's out there */
624 dcbi 0,r10
625 eieio
626
627 li r7,0x10 /* Reset ext/stat ints */
628 stb r7,0(r10) /* Set the register */
629 dcbf 0,r10 /* Force it out */
630 sync /* Make sure it's out there */
631 dcbi 0,r10
632 eieio
633
634 li r7,0x10 /* Reset ext/stat ints */
635 stb r7,0(r10) /* Set the register */
636 dcbf 0,r10 /* Force it out */
637 sync /* Make sure it's out there */
638 dcbi 0,r10
639 eieio
640
641 li r7,0x01 /* Set the register */
642 stb r7,0(r10) /* Set the register */
643 dcbf 0,r10 /* Force it out */
644 sync /* Make sure it's out there */
645 dcbi 0,r10
646 eieio
647
648 li r7,0x10 /* int on Rx, no Tx int enable */
649 stb r7,0(r10) /* Set the register */
650 dcbf 0,r10 /* Force it out */
651 sync /* Make sure it's out there */
652 dcbi 0,r10
653 eieio
654
655 li r7,0x09 /* Set the register */
656 stb r7,0(r10) /* Set the register */
657 dcbf 0,r10 /* Force it out */
658 sync /* Make sure it's out there */
659 dcbi 0,r10
660 eieio
661
662 li r7,0x0A /* int on Rx, Tx int enable */
663 stb r7,0(r10) /* Set the register */
664 dcbf 0,r10 /* Force it out */
665 sync /* Master enable, no vector */
666 dcbi 0,r10
667 eieio
668
669 li r7,0x09 /* Set the register */
670 stb r7,0(r10) /* Set the register */
671 dcbf 0,r10 /* Force it out */
672 sync /* Make sure it's out there */
673 dcbi 0,r10
674 eieio
675
676 li r7,0x02 /* No vector */
677 stb r7,0(r10) /* Set the register */
678 dcbf 0,r10 /* Force it out */
679 sync /* Master enable, no vector */
680 dcbi 0,r10
681 eieio
682
683 lbz r7,0(r10) /* Clear interrupts */
684 sync /* Master enable, no vector */
685 dcbi 0,r10
686 eieio
687
688 wSCCrdy: eieio /* Barricade it */
689 lbz r7,0(r10) /* Get current status */
690 dcbi 0,r10
691 sync
692 andi. r7,r7,0x04 /* Is transmitter empty? */
693 beq wSCCrdy /* Nope... */
694
695 eieio
696
697 #if 0
698 mtmsr r8 /* Restore 'rupts and TR */
699 isync
700 #endif
701 blr /* Leave... */
702
703 /*
704 * This routine is used to write debug output to either the modem or printer port.
705 * parm 1 is printer (0) or modem (1); parm 2 is ID (printed directly); parm 3 converted to hex
706 */
707
708 .align 5
709 .globl EXT(dbgDisp)
710
711 LEXT(dbgDisp)
712
713 mr r12,r0 /* Keep R0 pristene */
714 lis r0,HIGH_ADDR(dbgDispCall) /* Top half of dbgDispCall firmware call number */
715 ori r0,r0,LOW_ADDR(dbgDispCall) /* Bottom half */
716
717 sc /* Go display the stuff */
718
719 mr r0,r12 /* Restore R0 */
720 blr /* Return... */
721
722 /* Here's the low-level part of dbgDisp */
723
724 .align 5
725 .globl EXT(dbgDispLL)
726
727 LEXT(dbgDispLL)
728
729 dbgDispInt: mfmsr r8 /* Save the MSR */
730
731 #if 0
732 lis r10,0xF301 /* (TEST/DEBUG) */
733 ori r10,r10,0x2002 /* (TEST/DEBUG) */
734 dcbf 0,r10 /* (TEST/DEBUG) */
735 sync /* (TEST/DEBUG) */
736 dcbi 0,r10 /* (TEST/DEBUG) */
737 eieio /* (TEST/DEBUG) */
738 li r7,0x35 /* (TEST/DEBUG) */
739 stb r7,4(r10) /* (TEST/DEBUG) */
740
741 lis r7,10 /* (TEST/DEBUG) */
742 spw6: addi r7,r7,-1 /* (TEST/DEBUG) */
743 mr. r7,r7 /* (TEST/DEBUG) */
744 bne- spw6 /* (TEST/DEBUG) */
745 dcbf 0,r10 /* (TEST/DEBUG) */
746 sync /* (TEST/DEBUG) */
747 dcbi 0,r10 /* (TEST/DEBUG) */
748 eieio /* (TEST/DEBUG) */
749 #endif
750
751 rlwinm r12,r8,0,28,25 /* Turn off translation */
752 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
753
754 mflr r11 /* Save the link register */
755
756 #if 0
757 mr r7,r12 /* (TEST/DEBUG) */
758 bl dumpr7 /* (TEST/DEBUG) */
759 #endif
760
761 mr. r3,r3 /* See if printer or modem */
762 lis r10,0xF301 /* Set the top part */
763 mr r3,r4 /* Copy the ID parameter */
764
765 #if 0
766 mr r9,r12 /* (TEST/DEBUG) */
767
768 mtmsr r12 /* (TEST/DEBUG) */
769 isync /* (TEST/DEBUG) */
770
771 #if 0
772 mtmsr r8 /* (TEST/DEBUG) */
773 isync /* (TEST/DEBUG) */
774 #endif
775
776 lis r12,0xF301 /* (TEST/DEBUG) */
777 ori r12,r12,0x2002 /* (TEST/DEBUG) */
778 #if 1
779 dcbf 0,r12 /* (TEST/DEBUG) */
780 sync /* (TEST/DEBUG) */
781 dcbi 0,r12 /* (TEST/DEBUG) */
782 #endif
783
784 xqrw1: eieio /* (TEST/DEBUG) */
785 lbz r7,0(r12) /* (TEST/DEBUG) */
786 dcbi 0,r12 /* (TEST/DEBUG) */
787 sync /* (TEST/DEBUG) */
788 andi. r7,r7,0x04 /* (TEST/DEBUG) */
789 beq xqrw1 /* (TEST/DEBUG) */
790
791 eieio /* (TEST/DEBUG) */
792 li r7,0x36 /* (TEST/DEBUG) */
793 stb r7,4(r12) /* (TEST/DEBUG) */
794 eieio
795 dcbf 0,r12 /* (TEST/DEBUG) */
796 sync /* (TEST/DEBUG) */
797 dcbi 0,r12 /* (TEST/DEBUG) */
798 eieio /* (TEST/DEBUG) */
799
800
801 lis r7,10 /* (TEST/DEBUG) */
802 spw7: addi r7,r7,-1 /* (TEST/DEBUG) */
803 mr. r7,r7 /* (TEST/DEBUG) */
804 bne- spw7 /* (TEST/DEBUG) */
805 dcbf 0,r12 /* (TEST/DEBUG) */
806 sync /* (TEST/DEBUG) */
807 dcbi 0,r12 /* (TEST/DEBUG) */
808 eieio /* (TEST/DEBUG) */
809 mr r12,r9 /* (TEST/DEBUG) */
810 #endif
811
812 mtmsr r12 /* Smash the MSR */
813 isync /* Make it clean */
814
815
816 #if SIMPLESCC && !NOTQUITEASSIMPLE
817 ori r10,r10,0x3010 /* Assume the printer (this is the normal one) */
818 #else
819 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
820 #endif
821 beq+ dbgDprintr /* It sure are... */
822 #if SIMPLESCC && !NOTQUITEASSIMPLE
823 ori r10,r10,0x0020 /* Move it over to the modem port */
824 #else
825 ori r10,r10,0x0002 /* Move it over to the modem port */
826
827 #if !NOTQUITEASSIMPLE
828 lis r7,0xF300 /* Address of SCC rounded to 128k */
829 ori r7,r7,0x0032 /* Make it cache inhibited */
830 mtdbatl 3,r7 /* Load DBAT 3 low */
831 lis r7,0xF300 /* Address of SCC rounded to 128k */
832 ori r7,r7,0x0002 /* Make it supervisor only */
833 mtdbatu 3,r7 /* Load DBAT 3 high */
834 ori r12,r12,0x0010 /* Turn on DR */
835 mtmsr r12 /* Smash the MSR */
836 isync /* Make it clean */
837
838 #endif
839 #endif
840
841 dbgDprintr: sync
842 #if 0
843 mr r7,r10 /* (TEST/DEBUG) */
844 bl dumpr7 /* (TEST/DEBUG) */
845 #endif
846
847 dcbi 0,r10 /* Toss it */
848 eieio
849
850 #if 0
851 lis r12,0xF301 /* (TEST/DEBUG) */
852 ori r12,r12,0x2002 /* (TEST/DEBUG) */
853 dcbf 0,r12 /* (TEST/DEBUG) */
854 sync /* (TEST/DEBUG) */
855 dcbi 0,r12 /* (TEST/DEBUG) */
856 eieio /* (TEST/DEBUG) */
857 li r7,0x37 /* (TEST/DEBUG) */
858 stb r7,4(r12) /* (TEST/DEBUG) */
859
860 lis r7,12 /* (TEST/DEBUG) */
861 spw8: addi r7,r7,-1 /* (TEST/DEBUG) */
862 mr. r7,r7 /* (TEST/DEBUG) */
863 bne- spw8 /* (TEST/DEBUG) */
864 dcbf 0,r12 /* (TEST/DEBUG) */
865 sync /* (TEST/DEBUG) */
866 dcbi 0,r12 /* (TEST/DEBUG) */
867 eieio /* (TEST/DEBUG) */
868 #endif
869
870
871 /* Print the ID parameter */
872
873 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
874 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
875
876 lwarx r7,0,r12 ; ?
877
878 ddwait0: lwarx r7,0,r12 /* Get the lock */
879 mr. r7,r7 /* Is it locked? */
880 bne- ddwait0 /* Yup... */
881 stwcx. r12,0,r12 /* Try to get it */
882 bne- ddwait0 /* Nope, start all over... */
883
884 #if 0
885 dcbf 0,r10 /* (TEST/DEBUG) */
886 sync /* (TEST/DEBUG) */
887 dcbi 0,r10 /* (TEST/DEBUG) */
888 eieio /* (TEST/DEBUG) */
889 li r7,0x38 /* (TEST/DEBUG) */
890 stb r7,6(r10) /* (TEST/DEBUG) */
891
892 lis r7,10 /* (TEST/DEBUG) */
893 spwa: addi r7,r7,-1 /* (TEST/DEBUG) */
894 mr. r7,r7 /* (TEST/DEBUG) */
895 bne- spwa /* (TEST/DEBUG) */
896 dcbf 0,r10 /* (TEST/DEBUG) */
897 sync /* (TEST/DEBUG) */
898 dcbi 0,r10 /* (TEST/DEBUG) */
899 eieio /* (TEST/DEBUG) */
900 #endif
901
902 rlwinm r3,r3,8,0,31 /* Get the first character */
903 bl dbgDchar /* Print it */
904 rlwinm r3,r3,8,0,31 /* Get the second character */
905 bl dbgDchar /* Print it */
906 rlwinm r3,r3,8,0,31 /* Get the third character */
907 bl dbgDchar /* Print it */
908 rlwinm r3,r3,8,0,31 /* Get the fourth character */
909 bl dbgDchar /* Print it */
910
911 li r3,0x20 /* Get a space for a separator */
912 bl dbgDchar /* Print it */
913 bl dbg4byte /* Print register 5 in hex */
914
915 li r3,0x0A /* Linefeed */
916 bl dbgDchar /* Send it */
917 li r3,0x0D /* Carriage return */
918 bl dbgDchar /* Send it */
919
920 mtlr r11 /* Get back the return */
921 #if !SIMPLESCC && !NOTQUITEASSIMPLE
922 li r7,0 /* Get a zero */
923 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
924 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
925 #endif
926 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
927 li r7,0 /* Get a zero */
928 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
929 dcbi 0,r10 /* ? */
930 stw r7,0(r12) /* Release the display lock */
931 mtmsr r8 /* Restore the MSR */
932 isync /* Wait for it */
933 blr /* Leave... */
934
935
936 dbg4byte: mflr r12 /* Save the return */
937
938 lis r4,HIGH_ADDR(hexTab) /* Point to the top of table */
939 li r6,8 /* Set number of hex digits to dump */
940 ori r4,r4,LOW_ADDR(hexTab) /* Point to the bottom of table */
941
942 dbgDnext: rlwinm r5,r5,4,0,31 /* Rotate a nybble */
943 subi r6,r6,1 /* Back down the count */
944 rlwinm r3,r5,0,28,31 /* Isolate the last nybble */
945 lbzx r3,r4,r3 /* Convert to ascii */
946 bl dbgDchar /* Print it */
947 mr. r6,r6 /* Any more? */
948 bne+ dbgDnext /* Convert 'em all... */
949
950 li r3,0x20 /* Space */
951 bl dbgDchar /* Send it */
952 mtlr r12 /* Restore LR */
953 blr /* Return... */
954
955 /* Write to whichever serial port. Try to leave it clean, but not too hard (this is a hack) */
956
957 dbgDchar:
958 #if SIMPLESCC && !NOTQUITEASSIMPLE
959 stb r3,0(r10) /* ? */
960 dcbf 0,r10 /* Force it out */
961 sync /* Make sure it's out there */
962
963 lis r7,3 /* Get enough for about 1ms */
964
965 dbgDchar0: addi r7,r7,-1 /* Count down */
966 mr. r7,r7 /* Waited long enough? */
967 bgt+ dbgDchar0 /* Nope... */
968 #endif
969 #if NOTQUITEASSIMPLE
970 #if 0
971 li r7,0x01 /* ? */
972 stb r7,0(r10) /* ? */
973 dcbf 0,r10 /* Force it out */
974 sync /* Make sure it's out there */
975 dcbi 0,r10
976 eieio
977
978 lbz r7,0(r10) /* ? */
979 dcbi 0,r10 /* Force it out */
980 sync /* kill it off */
981 eieio
982
983 li r7,0x00 /* ? */
984 stb r7,0(r10) /* ? */
985 dcbf 0,r10 /* Force it out */
986 sync /* Make sure it's out there */
987 dcbi 0,r10
988 eieio
989
990 lbz r7,0(r10) /* ? */
991 dcbi 0,r10 /* Force it out */
992 sync /* kill it off */
993 eieio
994 #endif
995
996 qrw1: eieio /* Barricade it */
997 lbz r7,0(r10) /* ? */
998 dcbi 0,r10
999 sync
1000 andi. r7,r7,0x04 /* ? */
1001 beq qrw1 /* Nope... */
1002
1003 eieio
1004
1005 stb r3,4(r10) /* ? */
1006 dcbf 0,r10 /* Force it out */
1007 sync /* Make sure it's out there */
1008 dcbi 0,r10
1009 eieio
1010
1011 qrw2: eieio /* Barricade it */
1012 lbz r7,0(r10) /* ? */
1013 dcbi 0,r10
1014 sync
1015 andi. r7,r7,0x04 /* ? */
1016 beq qrw2 /* Nope... */
1017
1018 #if 0
1019 eieio
1020 li r7,0x10 /* ? */
1021 stb r7,0(r10) /* ? */
1022 dcbf 0,r10 /* Force it out */
1023 sync /* Make sure it's out there */
1024 dcbi 0,r10
1025 eieio
1026
1027 lbz r7,0(r10) /* ? */
1028 dcbi 0,r10 /* Force it out */
1029 sync /* kill it off */
1030 eieio
1031 #endif
1032
1033 lis r7,0x0080 /* ? */
1034 lis r9,0xF300 /* ? */
1035 ori r7,r7,0x010F /* ? */
1036 stw r7,0x28(r9) /* ? */
1037 dcbf 0,r10 /* Force it out */
1038 sync /* Make sure it's out there */
1039 dcbi 0,r10
1040 eieio
1041
1042 #endif
1043 #if !SIMPLESCC && !NOTQUITEASSIMPLE
1044 rlwinm r9,r10,0,0,29 /* Get channel a */
1045 eieio /* Barricade it */
1046
1047 li r7,0x03 /* ? */
1048 stb r7,0(r9) /* ? */
1049 eieio /* Barricade it */
1050
1051 lbz r7,0(r9) /* ? */
1052
1053 eieio /* Barricade it */
1054 lbz r7,0(r9) /* ? */
1055
1056 dchrw1: eieio /* Barricade it */
1057 lbz r7,0(r10) /* ? */
1058 andi. r7,r7,0x04 /* ? */
1059 beq dchrw1 /* Nope... */
1060
1061 stb r3,4(r10) /* ? */
1062 sync /* Make sure it's there */
1063 eieio /* Don't get confused */
1064
1065 dchrw2: eieio /* Barricade it */
1066 lbz r7,0(r10) /* ? */
1067 andi. r7,r7,0x04 /* ? */
1068 beq dchrw2 /* Nope... */
1069
1070 eieio /* Avoid confusion */
1071 lbz r7,0(r10) /* ? */
1072 andi. r7,r7,0x40 /* ? */
1073 beq+ nounder /* Nope... */
1074
1075 eieio /* Avoid confusion */
1076 li r7,0xC0 /* ? */
1077 stb r7,0(r10) /* ? */
1078
1079 nounder: eieio /* Avoid confusion */
1080 li r7,0x10 /* ? */
1081 stb r7,0(r10) /* ? */
1082
1083 eieio /* Avoid confusion */
1084 li r7,0x38 /* ? */
1085 stb r7,0(r9) /* ? */
1086
1087 eieio /* Avoid confusion */
1088 li r7,0x30 /* ? */
1089 stb r7,0(r10) /* ? */
1090
1091 eieio /* Avoid confusion */
1092 li r7,0x20 /* ? */
1093 stb r7,0(r10) /* ? */
1094 eieio /* Avoid confusion */
1095 sync
1096
1097 #endif
1098 blr /* Return */
1099
1100 .globl hexTab
1101
1102 hexTab: STRINGD "0123456789ABCDEF" /* Convert hex numbers to printable hex */
1103
1104
1105 /*
1106 * Dumps all the registers in the savearea in R13
1107 */
1108
1109
1110 .align 5
1111 .globl EXT(dbgRegsLL)
1112
1113 LEXT(dbgRegsLL)
1114
1115 b EXT(FCReturn) ; Bye dudes...
1116 #if 0
1117 li r3,0 /* ? */
1118 bl dbgRegsCm /* Join on up... */
1119 b EXT(FCReturn) ; Bye dudes...
1120
1121
1122 .align 5
1123 .globl EXT(dbgRegs)
1124
1125 LEXT(dbgRegs)
1126
1127 dbgRegsCm: mfmsr r8 /* Save the MSR */
1128 mr. r3,r3 /* ? */
1129 rlwinm r12,r8,0,28,25 /* Turn off translation */
1130 lis r10,0xF301 /* Set the top part */
1131 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
1132 mtmsr r12 /* Smash the MSR */
1133 isync /* Make it clean */
1134 #if SIMPLESCC && !NOTQUITEASSIMPLE
1135 ori r10,r10,0x3010 /* ? */
1136 #else
1137 ori r10,r10,0x2000 /* ? */
1138 #endif
1139 mflr r11 /* Save the link register */
1140 beq+ dbgDprints /* It sure are... */
1141 #if SIMPLESCC && !NOTQUITEASSIMPLE
1142 ori r10,r10,0x0020 /* ? */
1143 #else
1144 ori r10,r10,0x0002 /* ? */
1145
1146 dcbf 0,r10 /* Insure it is out */
1147 sync
1148 dcbi 0,r10 /* Toss it */
1149 #if !NOTQUITEASSIMPLE
1150 lis r7,0xF300 /* ? */
1151 ori r7,r7,0x0032 /* ? */
1152 mtdbatl 3,r7 /* ? */
1153 lis r7,0xF300 /* ? */
1154 ori r7,r7,0x0002 /* ? */
1155 mtdbatu 3,r7 /* ? */
1156 ori r12,r12,0x0010 /* ? */
1157 mtmsr r12 /* ? */
1158 isync /* ? */
1159 #endif
1160 #endif
1161
1162 dbgDprints:
1163 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1164 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1165
1166 lwarx r5,0,r3 ; ?
1167 ddwait1: lwarx r5,0,r3 /* Get the lock */
1168 mr. r5,r5 /* Is it locked? */
1169 bne- ddwait1 /* Yup... */
1170 stwcx. r3,0,r3 /* Try to get it */
1171 bne- ddwait1 /* Nope, start all over... */
1172
1173 li r3,0x52 /* Print eyecatcher */
1174 bl dbgDchar /* Send it */
1175 li r3,0x65 /* Print eyecatcher */
1176 bl dbgDchar /* Send it */
1177 li r3,0x67 /* Print eyecatcher */
1178 bl dbgDchar /* Send it */
1179 li r3,0x73 /* Print eyecatcher */
1180 bl dbgDchar /* Send it */
1181 li r3,0x20 /* Print eyecatcher */
1182 bl dbgDchar /* Send it */
1183
1184 lwz r5,saver0(r13) /* Do register */
1185 bl dbg4byte /* Print */
1186 lwz r5,saver1(r13) /* Do register */
1187 bl dbg4byte /* Print */
1188 lwz r5,saver2(r13) /* Do register */
1189 bl dbg4byte /* Print */
1190 lwz r5,saver3(r13) /* Do register */
1191 bl dbg4byte /* Print */
1192 li r3,0x0A /* Linefeed */
1193 bl dbgDchar /* Send it */
1194 li r3,0x0D /* Carriage return */
1195 bl dbgDchar /* Send it */
1196
1197 li r3,0x20 /* Print eyecatcher */
1198 bl dbgDchar /* Send it */
1199 li r3,0x20 /* Print eyecatcher */
1200 bl dbgDchar /* Send it */
1201 li r3,0x20 /* Print eyecatcher */
1202 bl dbgDchar /* Send it */
1203 li r3,0x20 /* Print eyecatcher */
1204 bl dbgDchar /* Send it */
1205 li r3,0x20 /* Print eyecatcher */
1206 bl dbgDchar /* Send it */
1207 lwz r5,saver4(r13) /* Do register */
1208 bl dbg4byte /* Print */
1209 lwz r5,saver5(r13) /* Do register */
1210 bl dbg4byte /* Print */
1211 lwz r5,saver6(r13) /* Do register */
1212 bl dbg4byte /* Print */
1213 lwz r5,saver7(r13) /* Do register */
1214 bl dbg4byte /* Print */
1215 li r3,0x0A /* Linefeed */
1216 bl dbgDchar /* Send it */
1217 li r3,0x0D /* Carriage return */
1218 bl dbgDchar /* Send it */
1219
1220 li r3,0x20 /* Print eyecatcher */
1221 bl dbgDchar /* Send it */
1222 li r3,0x20 /* Print eyecatcher */
1223 bl dbgDchar /* Send it */
1224 li r3,0x20 /* Print eyecatcher */
1225 bl dbgDchar /* Send it */
1226 li r3,0x20 /* Print eyecatcher */
1227 bl dbgDchar /* Send it */
1228 li r3,0x20 /* Print eyecatcher */
1229 bl dbgDchar /* Send it */
1230 lwz r5,saver8(r13) /* Do register */
1231 bl dbg4byte /* Print */
1232 lwz r5,saver9(r13) /* Do register */
1233 bl dbg4byte /* Print */
1234 lwz r5,saver10(r13) /* Do register */
1235 bl dbg4byte /* Print */
1236 lwz r5,saver11(r13) /* Do register */
1237 bl dbg4byte /* Print */
1238 li r3,0x0A /* Linefeed */
1239 bl dbgDchar /* Send it */
1240 li r3,0x0D /* Carriage return */
1241 bl dbgDchar /* Send it */
1242
1243 li r3,0x20 /* Print eyecatcher */
1244 bl dbgDchar /* Send it */
1245 li r3,0x20 /* Print eyecatcher */
1246 bl dbgDchar /* Send it */
1247 li r3,0x20 /* Print eyecatcher */
1248 bl dbgDchar /* Send it */
1249 li r3,0x20 /* Print eyecatcher */
1250 bl dbgDchar /* Send it */
1251 li r3,0x20 /* Print eyecatcher */
1252 bl dbgDchar /* Send it */
1253 lwz r5,saver12(r13) /* Do register */
1254 bl dbg4byte /* Print */
1255 lwz r5,saver13(r13) /* Do register */
1256 bl dbg4byte /* Print */
1257 lwz r5,saver14(r13) /* Do register */
1258 bl dbg4byte /* Print */
1259 lwz r5,saver15(r13) /* Do register */
1260 bl dbg4byte /* Print */
1261 li r3,0x0A /* Linefeed */
1262 bl dbgDchar /* Send it */
1263 li r3,0x0D /* Carriage return */
1264 bl dbgDchar /* Send it */
1265
1266 li r3,0x20 /* Print eyecatcher */
1267 bl dbgDchar /* Send it */
1268 li r3,0x20 /* Print eyecatcher */
1269 bl dbgDchar /* Send it */
1270 li r3,0x20 /* Print eyecatcher */
1271 bl dbgDchar /* Send it */
1272 li r3,0x20 /* Print eyecatcher */
1273 bl dbgDchar /* Send it */
1274 li r3,0x20 /* Print eyecatcher */
1275 bl dbgDchar /* Send it */
1276 lwz r5,saver16(r13) /* Do register */
1277 bl dbg4byte /* Print */
1278 lwz r5,saver17(r13) /* Do register */
1279 bl dbg4byte /* Print */
1280 lwz r5,saver18(r13) /* Do register */
1281 bl dbg4byte /* Print */
1282 lwz r5,saver19(r13) /* Do register */
1283 bl dbg4byte /* Print */
1284 li r3,0x0A /* Linefeed */
1285 bl dbgDchar /* Send it */
1286 li r3,0x0D /* Carriage return */
1287 bl dbgDchar /* Send it */
1288
1289 li r3,0x20 /* Print eyecatcher */
1290 bl dbgDchar /* Send it */
1291 li r3,0x20 /* Print eyecatcher */
1292 bl dbgDchar /* Send it */
1293 li r3,0x20 /* Print eyecatcher */
1294 bl dbgDchar /* Send it */
1295 li r3,0x20 /* Print eyecatcher */
1296 bl dbgDchar /* Send it */
1297 li r3,0x20 /* Print eyecatcher */
1298 bl dbgDchar /* Send it */
1299 lwz r5,saver20(r13) /* Do register */
1300 bl dbg4byte /* Print */
1301 lwz r5,saver21(r13) /* Do register */
1302 bl dbg4byte /* Print */
1303 lwz r5,saver22(r13) /* Do register */
1304 bl dbg4byte /* Print */
1305 lwz r5,saver23(r13) /* Do register */
1306 bl dbg4byte /* Print */
1307 li r3,0x0A /* Linefeed */
1308 bl dbgDchar /* Send it */
1309 li r3,0x0D /* Carriage return */
1310 bl dbgDchar /* Send it */
1311
1312 li r3,0x20 /* Print eyecatcher */
1313 bl dbgDchar /* Send it */
1314 li r3,0x20 /* Print eyecatcher */
1315 bl dbgDchar /* Send it */
1316 li r3,0x20 /* Print eyecatcher */
1317 bl dbgDchar /* Send it */
1318 li r3,0x20 /* Print eyecatcher */
1319 bl dbgDchar /* Send it */
1320 li r3,0x20 /* Print eyecatcher */
1321 bl dbgDchar /* Send it */
1322 lwz r5,saver24(r13) /* Do register */
1323 bl dbg4byte /* Print */
1324 lwz r5,saver25(r13) /* Do register */
1325 bl dbg4byte /* Print */
1326 lwz r5,saver26(r13) /* Do register */
1327 bl dbg4byte /* Print */
1328 lwz r5,saver27(r13) /* Do register */
1329 bl dbg4byte /* Print */
1330 li r3,0x0A /* Linefeed */
1331 bl dbgDchar /* Send it */
1332 li r3,0x0D /* Carriage return */
1333 bl dbgDchar /* Send it */
1334
1335 li r3,0x20 /* Print eyecatcher */
1336 bl dbgDchar /* Send it */
1337 li r3,0x20 /* Print eyecatcher */
1338 bl dbgDchar /* Send it */
1339 li r3,0x20 /* Print eyecatcher */
1340 bl dbgDchar /* Send it */
1341 li r3,0x20 /* Print eyecatcher */
1342 bl dbgDchar /* Send it */
1343 li r3,0x20 /* Print eyecatcher */
1344 bl dbgDchar /* Send it */
1345 lwz r5,saver28(r13) /* Do register */
1346 bl dbg4byte /* Print */
1347 lwz r5,saver29(r13) /* Do register */
1348 bl dbg4byte /* Print */
1349 lwz r5,saver30(r13) /* Do register */
1350 bl dbg4byte /* Print */
1351 lwz r5,saver31(r13) /* Do register */
1352 bl dbg4byte /* Print */
1353 li r3,0x0A /* Linefeed */
1354 bl dbgDchar /* Send it */
1355 li r3,0x0D /* Carriage return */
1356 bl dbgDchar /* Send it */
1357
1358 /* Segment registers */
1359
1360 li r3,0x53 /* Print eyecatcher */
1361 bl dbgDchar /* Send it */
1362 li r3,0x65 /* Print eyecatcher */
1363 bl dbgDchar /* Send it */
1364 li r3,0x67 /* Print eyecatcher */
1365 bl dbgDchar /* Send it */
1366 li r3,0x73 /* Print eyecatcher */
1367 bl dbgDchar /* Send it */
1368 li r3,0x20 /* Print eyecatcher */
1369 bl dbgDchar /* Send it */
1370
1371 lwz r5,savesr0(r13) /* Do register */
1372 bl dbg4byte /* Print */
1373 lwz r5,savesr1(r13) /* Do register */
1374 bl dbg4byte /* Print */
1375 lwz r5,savesr2(r13) /* Do register */
1376 bl dbg4byte /* Print */
1377 lwz r5,savesr3(r13) /* Do register */
1378 bl dbg4byte /* Print */
1379 li r3,0x0A /* Linefeed */
1380 bl dbgDchar /* Send it */
1381 li r3,0x0D /* Carriage return */
1382 bl dbgDchar /* Send it */
1383
1384 li r3,0x20 /* Print eyecatcher */
1385 bl dbgDchar /* Send it */
1386 li r3,0x20 /* Print eyecatcher */
1387 bl dbgDchar /* Send it */
1388 li r3,0x20 /* Print eyecatcher */
1389 bl dbgDchar /* Send it */
1390 li r3,0x20 /* Print eyecatcher */
1391 bl dbgDchar /* Send it */
1392 li r3,0x20 /* Print eyecatcher */
1393 bl dbgDchar /* Send it */
1394 lwz r5,savesr4(r13) /* Do register */
1395 bl dbg4byte /* Print */
1396 lwz r5,savesr5(r13) /* Do register */
1397 bl dbg4byte /* Print */
1398 lwz r5,savesr6(r13) /* Do register */
1399 bl dbg4byte /* Print */
1400 lwz r5,savesr7(r13) /* Do register */
1401 bl dbg4byte /* Print */
1402 li r3,0x0A /* Linefeed */
1403 bl dbgDchar /* Send it */
1404 li r3,0x0D /* Carriage return */
1405 bl dbgDchar /* Send it */
1406
1407 li r3,0x20 /* Print eyecatcher */
1408 bl dbgDchar /* Send it */
1409 li r3,0x20 /* Print eyecatcher */
1410 bl dbgDchar /* Send it */
1411 li r3,0x20 /* Print eyecatcher */
1412 bl dbgDchar /* Send it */
1413 li r3,0x20 /* Print eyecatcher */
1414 bl dbgDchar /* Send it */
1415 li r3,0x20 /* Print eyecatcher */
1416 bl dbgDchar /* Send it */
1417 lwz r5,savesr8(r13) /* Do register */
1418 bl dbg4byte /* Print */
1419 lwz r5,savesr9(r13) /* Do register */
1420 bl dbg4byte /* Print */
1421 lwz r5,savesr10(r13) /* Do register */
1422 bl dbg4byte /* Print */
1423 lwz r5,savesr11(r13) /* Do register */
1424 bl dbg4byte /* Print */
1425 li r3,0x0A /* Linefeed */
1426 bl dbgDchar /* Send it */
1427 li r3,0x0D /* Carriage return */
1428 bl dbgDchar /* Send it */
1429
1430 li r3,0x20 /* Print eyecatcher */
1431 bl dbgDchar /* Send it */
1432 li r3,0x20 /* Print eyecatcher */
1433 bl dbgDchar /* Send it */
1434 li r3,0x20 /* Print eyecatcher */
1435 bl dbgDchar /* Send it */
1436 li r3,0x20 /* Print eyecatcher */
1437 bl dbgDchar /* Send it */
1438 li r3,0x20 /* Print eyecatcher */
1439 bl dbgDchar /* Send it */
1440 lwz r5,savesr12(r13) /* Do register */
1441 bl dbg4byte /* Print */
1442 lwz r5,savesr13(r13) /* Do register */
1443 bl dbg4byte /* Print */
1444 lwz r5,savesr14(r13) /* Do register */
1445 bl dbg4byte /* Print */
1446 lwz r5,savesr15(r13) /* Do register */
1447 bl dbg4byte /* Print */
1448 li r3,0x0A /* Linefeed */
1449 bl dbgDchar /* Send it */
1450 li r3,0x0D /* Carriage return */
1451 bl dbgDchar /* Send it */
1452
1453 li r3,0x30 /* Print eyecatcher */
1454 bl dbgDchar /* Send it */
1455 li r3,0x31 /* Print eyecatcher */
1456 bl dbgDchar /* Send it */
1457 li r3,0x64 /* Print eyecatcher */
1458 bl dbgDchar /* Send it */
1459 li r3,0x64 /* Print eyecatcher */
1460 bl dbgDchar /* Send it */
1461 li r3,0x20 /* Print eyecatcher */
1462 bl dbgDchar /* Send it */
1463 lwz r5,savesrr0(r13) /* Do register */
1464 bl dbg4byte /* Print */
1465 lwz r5,savesrr1(r13) /* Do register */
1466 bl dbg4byte /* Print */
1467 lwz r5,savedar(r13) /* Do register */
1468 bl dbg4byte /* Print */
1469 lwz r5,savedsisr(r13) /* Do register */
1470 bl dbg4byte /* Print */
1471 li r3,0x0A /* Linefeed */
1472 bl dbgDchar /* Send it */
1473 li r3,0x0D /* Carriage return */
1474 bl dbgDchar /* Send it */
1475
1476 li r3,0x20 /* Print eyecatcher */
1477 bl dbgDchar /* Send it */
1478 li r3,0x6C /* Print eyecatcher */
1479 bl dbgDchar /* Send it */
1480 li r3,0x63 /* Print eyecatcher */
1481 bl dbgDchar /* Send it */
1482 li r3,0x63 /* Print eyecatcher */
1483 bl dbgDchar /* Send it */
1484 li r3,0x20 /* Print eyecatcher */
1485 bl dbgDchar /* Send it */
1486 lwz r5,savelr(r13) /* Do register */
1487 bl dbg4byte /* Print */
1488 lwz r5,savecr(r13) /* Do register */
1489 bl dbg4byte /* Print */
1490 lwz r5,savectr(r13) /* Do register */
1491 bl dbg4byte /* Print */
1492 li r3,0x0A /* Linefeed */
1493 bl dbgDchar /* Send it */
1494 li r3,0x0D /* Carriage return */
1495 bl dbgDchar /* Send it */
1496 mtlr r11 /* Get back the return */
1497 dcbi 0,r10 /* ? */
1498 #if !SIMPLESCC && !NOTQUITEASSIMPLE
1499 li r7,0 /* Get a zero */
1500 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
1501 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
1502 #endif
1503 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1504 li r7,0 /* Get a zero */
1505 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1506 stw r7,0(r3) /* Clear display lock */
1507 mtmsr r8 /* Restore the MSR */
1508 isync /* Wait for it */
1509 blr /* Leave... */
1510 #endif
1511
1512 /*
1513 * Used for debugging to leave stuff in 0x380-0x3FF (128 bytes).
1514 * Mapping is V=R. Stores and loads are real.
1515 */
1516
1517 .align 5
1518 .globl EXT(dbgCkpt)
1519
1520 LEXT(dbgCkpt)
1521
1522 mr r12,r0 /* Keep R0 pristene */
1523 lis r0,HIGH_ADDR(dbgCkptCall) /* Top half of dbgCkptCall firmware call number */
1524 ori r0,r0,LOW_ADDR(dbgCkptCall) /* Bottom half */
1525
1526 sc /* Go stash the stuff */
1527
1528 mr r0,r12 /* Restore R0 */
1529 blr /* Return... */
1530
1531 /* Here's the low-level part of dbgCkpt */
1532
1533 .align 5
1534 .globl EXT(dbgCkptLL)
1535
1536 LEXT(dbgCkptLL)
1537
1538
1539 li r12,0x380 /* Point to output area */
1540 li r1,32 /* Get line size */
1541 dcbz 0,r12 /* Make sure we don't fetch a cache line */
1542
1543 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1544
1545 dcbt r1,r3 /* Start in the next line */
1546
1547 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1548 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1549 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1550 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1551 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1552 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1553 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1554
1555 add r3,r3,r1 /* Bump input */
1556
1557 stw r4,0x00(r12) /* Store it */
1558 stw r5,0x04(r12) /* Store it */
1559 stw r6,0x08(r12) /* Store it */
1560 stw r7,0x0C(r12) /* Store it */
1561 stw r8,0x10(r12) /* Store it */
1562 stw r9,0x14(r12) /* Store it */
1563 stw r10,0x18(r12) /* Store it */
1564 stw r11,0x1C(r12) /* Store it */
1565
1566 dcbz r1,r12 /* Clear the next line */
1567 add r12,r12,r1 /* Point to next output line */
1568
1569 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1570 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1571 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1572 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1573 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1574 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1575 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1576 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1577
1578 dcbt r1,r3 /* Touch the next line */
1579 add r3,r3,r1 /* Point to next input line */
1580
1581 stw r4,0x00(r12) /* Store it */
1582 stw r5,0x04(r12) /* Store it */
1583 stw r6,0x08(r12) /* Store it */
1584 stw r7,0x0C(r12) /* Store it */
1585 stw r8,0x10(r12) /* Store it */
1586 stw r9,0x14(r12) /* Store it */
1587 stw r10,0x18(r12) /* Store it */
1588 stw r11,0x1C(r12) /* Store it */
1589
1590 dcbz r1,r12 /* Clear the next line */
1591 add r12,r12,r1 /* Point to next output line */
1592
1593 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1594 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1595 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1596 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1597 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1598 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1599 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1600 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1601
1602 dcbt r1,r3 /* Touch the next line */
1603 add r3,r3,r1 /* Point to next input line */
1604
1605 stw r4,0x00(r12) /* Store it */
1606 stw r5,0x04(r12) /* Store it */
1607 stw r6,0x08(r12) /* Store it */
1608 stw r7,0x0C(r12) /* Store it */
1609 stw r8,0x10(r12) /* Store it */
1610 stw r9,0x14(r12) /* Store it */
1611 stw r10,0x18(r12) /* Store it */
1612 stw r11,0x1C(r12) /* Store it */
1613
1614 dcbz r1,r12 /* Clear the next line */
1615 add r12,r12,r1 /* Point to next output line */
1616
1617 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1618 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1619 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1620 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1621 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1622 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1623 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1624 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1625
1626 stw r4,0x00(r12) /* Store it */
1627 stw r5,0x04(r12) /* Store it */
1628 stw r6,0x08(r12) /* Store it */
1629 stw r7,0x0C(r12) /* Store it */
1630 stw r8,0x10(r12) /* Store it */
1631 stw r9,0x14(r12) /* Store it */
1632 stw r10,0x18(r12) /* Store it */
1633 stw r11,0x1C(r12) /* Store it */
1634
1635 blr
1636
1637
1638 /*
1639 * Do Preemption. Forces a T_PREEMPT trap to allow a preemption to occur.
1640 */
1641
1642 .align 5
1643 .globl EXT(DoPreemptLL)
1644
1645 LEXT(DoPreemptLL)
1646
1647 li r3,T_PREEMPT /* Set preemption interrupt value */
1648 stw r3,saveexception(r13) /* Modify the exception type to preemption */
1649 b EXT(FCReturn) ; Bye dudes...
1650
1651
1652 /*
1653 * Force 'rupt handler to dispatch with new context
1654 * R3 at the call contains the new savearea.
1655 * R4 at the call contains a return code to pass back in R3.
1656 * Forces a T_CSWITCH
1657 */
1658
1659 .align 5
1660 .globl EXT(SwitchContextLL)
1661
1662 LEXT(SwitchContextLL)
1663
1664 li r3,T_CSWITCH /* Set context switch value */
1665 stw r3,saveexception(r13) /* Modify the exception type to switch context */
1666 b EXT(FCReturn) ; Bye dudes...
1667
1668
1669 /*
1670 * Create a fake I/O 'rupt.
1671 * Forces a T_INTERRUPT trap to pretend that an actual I/O interrupt occurred.
1672 */
1673
1674 .align 5
1675 .globl EXT(CreateFakeIOLL)
1676
1677 LEXT(CreateFakeIOLL)
1678
1679 li r3,T_INTERRUPT /* Set external interrupt value */
1680 stw r3,saveexception(r13) /* Modify the exception type to external */
1681 b EXT(FCReturn) ; Bye dudes...
1682
1683 /*
1684 * Create a shutdown context
1685 * Forces a T_SHUTDOWN trap.
1686 */
1687
1688 .align 5
1689 .globl EXT(CreateShutdownCTXLL)
1690
1691 LEXT(CreateShutdownCTXLL)
1692
1693 li r3,T_SHUTDOWN /* Set external interrupt value */
1694 stw r3,saveexception(r13) /* Modify the exception type to external */
1695 b EXT(FCReturn) ; Bye dudes...
1696
1697 /*
1698 * Create a fake decrementer 'rupt.
1699 * Forces a T_DECREMENTER trap to pretend that an actual decrementer interrupt occurred.
1700 */
1701
1702 .align 5
1703 .globl EXT(CreateFakeDECLL)
1704
1705 LEXT(CreateFakeDECLL)
1706
1707 li r3,T_DECREMENTER /* Set decrementer interrupt value */
1708 stw r3,saveexception(r13) /* Modify the exception type to external */
1709 b EXT(FCReturn) ; Bye dudes...
1710
1711 /*
1712 * Choke the system.
1713 */
1714
1715 .align 5
1716 .globl EXT(DoChokeLL)
1717
1718 LEXT(DoChokeLL)
1719
1720 li r3,T_CHOKE ; Set external interrupt value
1721 stw r3,saveexception(r13) ; Modify the exception type to external
1722 b EXT(FCReturn) ; Bye dudes...
1723
1724 /*
1725 * Null firmware call
1726 */
1727
1728 .align 5
1729 .globl EXT(NullLL)
1730
1731 LEXT(NullLL)
1732
1733 li r3,T_IN_VAIN ; Set to just ignore this one
1734 b EXT(FCReturn) ; Bye dudes...
1735
1736 ;
1737 ; Null firmware call
1738 ;
1739
1740 .align 5
1741 .globl EXT(iNullLL)
1742
1743 LEXT(iNullLL)
1744
1745 mfspr r4,pmc1 ; Get stamp
1746 stw r4,0x6100+(9*16)+0x0(0) ; Save it
1747 #if 1
1748 mfspr r4,pmc2 ; Get stamp
1749 stw r4,0x6100+(9*16)+0x4(0) ; Save it
1750 mfspr r4,pmc3 ; Get stamp
1751 stw r4,0x6100+(9*16)+0x8(0) ; Save it
1752 mfspr r4,pmc4 ; Get stamp
1753 stw r4,0x6100+(9*16)+0xC(0) ; Save it
1754 #endif
1755 li r3,T_IN_VAIN ; Set to just ignore this one
1756 b EXT(FCReturn) ; Bye dudes...
1757
1758 ;
1759 ; Set the low level trace flags
1760 ;
1761
1762 .align 5
1763 .globl EXT(LLTraceSet)
1764
1765 LEXT(LLTraceSet)
1766
1767 mr r4,r3 ; Save the new value
1768
1769 lwz r3,traceMask(0) ; Get the old trace flags to pass back
1770 stw r4,traceMask(0) ; Replace with the new ones
1771 blr ; Leave...
1772
1773 #if 0
1774
1775 /*
1776 ; ***************************************************************************
1777 ;
1778 ; ----------------- Grateful Deb ----------------
1779 ;
1780 ; Debugging: direct draw into main screen menu bar
1781 ;
1782 ; Takes R4 value, converts it to hex characters and displays it.
1783 ;
1784 ; Gotta make sure the DCBST is done to force the pixels from the cache.
1785 ;
1786 ; Position is taken as column, row (0 based) from R3.
1787 ; Characters are from hexfont, and are 16x16 pixels.
1788 ;
1789 ; Only works with two processors so far
1790 ;
1791 ;
1792 ; ***************************************************************************
1793 */
1794
1795 #define GDfromright 20
1796 #define GDfontsize 16
1797
1798 .align 5
1799 .globl EXT(GratefulDeb)
1800
1801 LEXT(GratefulDeb)
1802
1803 mfspr r6,pir /* Get the PIR */
1804 lis r5,HIGH_ADDR(EXT(GratefulDebWork)) /* Point to our work area */
1805 rlwinm r6,r6,8,23,23 /* Get part of the offset to our processors area */
1806 ori r5,r5,LOW_ADDR(EXT(GratefulDebWork)) /* Start building the address */
1807 rlwimi r6,r6,2,21,21 /* Get the rest of the offset to our processors area */
1808 add r6,r6,r5 /* Point at our CPU's work area */
1809 mfmsr r5 /* Get that MSR */
1810 stmw r0,GDsave(r6) /* Save all registers */
1811 lwz r10,GDready(r6) /* See if we're all ready to go */
1812 ori r0,r5,0x2000 /* Turn on the floating point */
1813 mr r31,r6 /* Get a more sane base register */
1814 mr. r10,r10 /* Are we all set? */
1815 mtmsr r0 /* Enable floating point */
1816 isync
1817
1818 stfd f0,GDfp0(r31) /* Save FP */
1819 stfd f1,GDfp1(r31) /* Save FP */
1820 stfd f2,GDfp2(r31) /* Save FP */
1821 stfd f3,GDfp3(r31) /* Save FP */
1822
1823 beq- GDbailout /* Go and bail... */
1824
1825 rlwinm r25,r3,0,16,31 /* Isolate just the row number */
1826 lwz r28,GDtopleft(r31) /* Get the physical address of our line 0 */
1827 rlwinm r3,r3,16,16,31 /* Isolate the column number */
1828 lwz r27,GDrowbytes(r31) /* Get the number of bytes per row */
1829 lwz r9,GDrowchar(r31) /* Get the number of bytes per row of full leaded charactrers */
1830 lwz r26,GDdepth(r31) /* Get the bit depth */
1831 mullw r25,r25,r9 /* get offset to the row to write in bytes */
1832 lwz r24,GDcollgn(r31) /* Get the size of columns in bytes */
1833 add r25,r28,r25 /* Physical address of row */
1834 mullw r3,r3,r24 /* Get byte offset to first output column */
1835
1836 li r9,32 /* Get the initial shift calc */
1837
1838 lis r20,HIGH_ADDR(hexfont) /* Point to the font */
1839
1840 li r18,GDfontsize /* Get the number of rows in the font */
1841 ori r20,r20,LOW_ADDR(hexfont) /* Point to the low part */
1842 add r21,r25,r3 /* Physical address of top left output pixel */
1843 sub r9,r9,r26 /* Get right shift justifier for pixel size */
1844 li r7,32 /* Number of bits per word */
1845
1846 startNybble:
1847 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1848 li r19,8 /* Get the number of characters in a row */
1849
1850 getNybble: rlwinm r10,r4,9,23,26 /* Get the top nybble * 32 */
1851 rlwinm r4,r4,4,0,31 /* Rotate a nybble */
1852 add r10,r20,r10 /* Point to the character in the font */
1853
1854 rlwinm r16,r26,4,0,27 /* Width of row in actual bits */
1855 lhz r15,0(r10) /* Get the next row of the font */
1856
1857 rendrow: rlwinm r17,r15,16,0,0 /* Get the next font pixel in the row */
1858 rlwinm r15,r15,1,16,31 /* Move in the next font pixel */
1859 srawi r17,r17,31 /* Fill with 1s if black and 0s if white (reversed) */
1860
1861 slw r14,r14,r26 /* Make room for our pixel in a register */
1862 srw r17,r17,r9 /* Isolate one pixels worth of black or white */
1863 sub. r7,r7,r26 /* See how may bits are left */
1864 sub r16,r16,r26 /* Count how many bits are left to store for this row */
1865 or r14,r14,r17 /* Put in the pixel */
1866 bne+ notfull /* Finish rendering this word */
1867
1868 not r14,r14 /* Invert to black on white */
1869 stw r14,0(r6) /* Write out the word */
1870 li r7,32 /* Bit per word count */
1871 addi r6,r6,4 /* Point to the next word */
1872
1873 notfull: mr. r16,r16 /* Have we finished the whole character row? */
1874 bne+ rendrow /* Finish rendering the row */
1875
1876 addic. r19,r19,-1 /* Are we finished with a whole display row yet? */
1877 bne+ getNybble /* Not yet... */
1878
1879 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1880 rlwinm r19,r26,31,0,29 /* Number of cache lines (depth/2) */
1881 mr r14,r21 /* Get the frame buffer address */
1882
1883 // BREAKPOINT_TRAP
1884
1885 blitrow: lfd f0,0(r6) /* Load a line */
1886 lfd f1,8(r6)
1887 lfd f2,16(r6)
1888 lfd f3,24(r6)
1889
1890 stfd f0,0(r14) /* Blit a line */
1891 stfd f1,8(r14)
1892 stfd f2,16(r14)
1893 stfd f3,24(r14)
1894
1895 addi r6,r6,32 /* Next buffered line */
1896
1897 dcbst 0,r14 /* Force the line to the screen */
1898 sync /* Make sure the line is on it's way */
1899 eieio /* Make sure we beat the invalidate */
1900 dcbi 0,r14 /* Make sure we leave no paradox */
1901
1902 addic. r19,r19,-1 /* Done all lines yet? */
1903 addi r14,r14,32 /* Point to the next output */
1904 bne+ blitrow /* Nope, do it some more... */
1905
1906 addic. r18,r18,-1 /* Have we done all the rows in character yet? */
1907 addi r20,r20,2 /* Offset the font to the next row */
1908 add r21,r21,r27 /* Point to start of next row */
1909 bne+ startNybble /* Nope, go through the word one more time... */
1910
1911 GDbailout: mr r1,r31 /* Move the workarea base */
1912
1913 lfd f0,GDfp0(r31) /* Restore FP */
1914 lfd f1,GDfp1(r31) /* Restore FP */
1915 lfd f2,GDfp2(r31) /* Restore FP */
1916 lfd f3,GDfp3(r31) /* Restore FP */
1917
1918 mtmsr r5 /* Disable floating point */
1919 isync
1920
1921 lmw r3,GDsave+12(r1) /* Restore most registers */
1922 lwz r0,GDsave(r1) /* Restore R0 */
1923 lwz r1,GDsave+4(r1) /* Finally, R1 */
1924 blr /* Leave... */
1925
1926
1927 /*
1928 * void GratefulDebDisp(unsigned int coord, unsigned int data);
1929 */
1930
1931
1932 .align 5
1933 .globl EXT(GratefulDebDisp)
1934
1935 LEXT(GratefulDebDisp)
1936
1937 mfmsr r9 /* Save the current MSR */
1938 mflr r7 /* Save the return */
1939 andi. r8,r9,0x7FCF /* Clear interrupt and translation */
1940 mtmsr r8 /* Turn 'em really off */
1941 isync /* Make sure about the translation part */
1942 bl EXT(GratefulDeb) /* Display it */
1943 mtmsr r9 /* Restore interrupt and translation */
1944 mtlr r7 /* Restore return */
1945 isync /* Make sure */
1946 blr
1947
1948
1949 #endif
1950
1951 /*
1952 * void checkNMI(void);
1953 */
1954
1955
1956 .align 5
1957 .globl EXT(checkNMI)
1958
1959 LEXT(checkNMI)
1960
1961 mfmsr r9 /* Save it */
1962 andi. r8,r9,0x7FCF /* Clear it */
1963 mtmsr r8 /* Disable it */
1964 isync /* Fence it */
1965 lis r7,0xF300 /* Find it */
1966 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
1967 ori r7,r7,0x0020 /* Find it */
1968 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
1969 dcbi 0,r7 /* Toss it */
1970 sync /* Sync it */
1971 andc r9,r9,r2 ; Clear VEC and FP enables
1972 eieio /* Get it */
1973 lwz r6,0x000C(r7) /* Check it */
1974 eieio /* Fence it */
1975 dcbi 0,r7 /* Toss it */
1976 rlwinm. r4,r6,0,19,19 /* Check it */
1977 rlwinm r6,r6,0,20,18 /* Clear it */
1978 sync /* Sync it */
1979 eieio /* Fence it */
1980 beq+ xnonmi /* Branch on it */
1981
1982 stw r6,0x0008(r7) /* Reset it */
1983 sync /* Sync it */
1984 dcbi 0,r6 /* Toss it */
1985 eieio /* Fence it */
1986
1987 mtmsr r9 /* Restore it */
1988 isync /* Hold it */
1989
1990 BREAKPOINT_TRAP /* Kill it */
1991 blr /* Return from it */
1992
1993 xnonmi: /* Label it */
1994 mtmsr r9 /* Restore it */
1995 isync /* Hold it */
1996 blr /* Return from it */
1997
1998 ;
1999 ; Saves floating point registers
2000 ;
2001
2002 .align 5
2003 .globl EXT(stFloat)
2004
2005 LEXT(stFloat)
2006
2007 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
2008 li r4,0
2009 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
2010 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit
2011
2012 mfmsr r0 ; Save the MSR
2013
2014 andc r4,r0,r4 ; Clear EE
2015 ori r4,r4,lo16(MASK(MSR_FP)) ; Enable floating point
2016 mtmsr r4
2017 isync
2018
2019 andc r0,r0,r2 ; Clear VEC and FP enables
2020
2021 stfd f0,0x00(r3)
2022 stfd f1,0x08(r3)
2023 stfd f2,0x10(r3)
2024 stfd f3,0x18(r3)
2025 stfd f4,0x20(r3)
2026 stfd f5,0x28(r3)
2027 stfd f6,0x30(r3)
2028 stfd f7,0x38(r3)
2029 stfd f8,0x40(r3)
2030 stfd f9,0x48(r3)
2031 stfd f10,0x50(r3)
2032 stfd f11,0x58(r3)
2033 stfd f12,0x60(r3)
2034 stfd f13,0x68(r3)
2035 stfd f14,0x70(r3)
2036 stfd f15,0x78(r3)
2037 stfd f16,0x80(r3)
2038 stfd f17,0x88(r3)
2039 stfd f18,0x90(r3)
2040 stfd f19,0x98(r3)
2041 stfd f20,0xA0(r3)
2042 stfd f21,0xA8(r3)
2043 stfd f22,0xB0(r3)
2044 stfd f23,0xB8(r3)
2045 stfd f24,0xC0(r3)
2046 stfd f25,0xC8(r3)
2047 stfd f26,0xD0(r3)
2048 stfd f27,0xD8(r3)
2049 stfd f28,0xE0(r3)
2050 stfd f29,0xE8(r3)
2051 stfd f30,0xF0(r3)
2052 stfd f31,0xF8(r3)
2053 mffs f0
2054 stfd f0,0x100(r3)
2055 lfd f0,0x00(r3)
2056 mtmsr r0
2057 isync
2058 blr
2059
2060
2061 ;
2062 ; Saves vector registers. Returns 0 if non-Altivec machine.
2063 ;
2064
2065 .align 5
2066 .globl EXT(stVectors)
2067
2068 LEXT(stVectors)
2069
2070 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
2071 li r4,0
2072 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
2073 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit
2074
2075 mfsprg r6,2 ; Get features
2076 mr r5,r3 ; Save area address
2077 rlwinm. r6,r6,0,pfAltivecb,pfAltivecb ; Do we have Altivec?
2078 li r3,0 ; Assume failure
2079 beqlr- ; No...
2080
2081 mfmsr r0 ; Save the MSR
2082
2083 andc r4,r0,r4 ; Clear EE
2084
2085 oris r4,r4,hi16(MASK(MSR_VEC)) ; Enable vectors
2086 mtmsr r4
2087 isync
2088
2089 andc r0,r0,r2 ; Clear FP and VEC
2090
2091 stvxl v0,0,r5
2092 addi r5,r5,16
2093 stvxl v1,0,r5
2094 addi r5,r5,16
2095 stvxl v2,0,r5
2096 addi r5,r5,16
2097 stvxl v3,0,r5
2098 addi r5,r5,16
2099 stvxl v4,0,r5
2100 addi r5,r5,16
2101 stvxl v5,0,r5
2102 addi r5,r5,16
2103 stvxl v6,0,r5
2104 addi r5,r5,16
2105 stvxl v7,0,r5
2106 addi r5,r5,16
2107 stvxl v8,0,r5
2108 addi r5,r5,16
2109 stvxl v9,0,r5
2110 addi r5,r5,16
2111 stvxl v10,0,r5
2112 addi r5,r5,16
2113 stvxl v11,0,r5
2114 addi r5,r5,16
2115 stvxl v12,0,r5
2116 addi r5,r5,16
2117 stvxl v13,0,r5
2118 addi r5,r5,16
2119 stvxl v14,0,r5
2120 addi r5,r5,16
2121 stvxl v15,0,r5
2122 addi r5,r5,16
2123 stvxl v16,0,r5
2124 addi r5,r5,16
2125 stvxl v17,0,r5
2126 addi r5,r5,16
2127 stvxl v18,0,r5
2128 addi r5,r5,16
2129 stvxl v19,0,r5
2130 addi r5,r5,16
2131 stvxl v20,0,r5
2132 addi r5,r5,16
2133 stvxl v21,0,r5
2134 addi r5,r5,16
2135 stvxl v22,0,r5
2136 addi r5,r5,16
2137 stvxl v23,0,r5
2138 addi r5,r5,16
2139 stvxl v24,0,r5
2140 addi r5,r5,16
2141 stvxl v25,0,r5
2142 addi r5,r5,16
2143 stvxl v26,0,r5
2144 addi r5,r5,16
2145 stvxl v27,0,r5
2146 addi r5,r5,16
2147 stvxl v28,0,r5
2148 addi r5,r5,16
2149 stvxl v29,0,r5
2150 addi r5,r5,16
2151 stvxl v30,0,r5
2152 addi r5,r5,16
2153 stvxl v31,0,r5
2154 mfvscr v31
2155 addi r6,r5,16
2156 stvxl v31,0,r6
2157 li r3,1
2158 lvxl v31,0,r5
2159 mtmsr r0
2160 isync
2161
2162 blr
2163
2164
2165 ;
2166 ; Saves yet more registers
2167 ;
2168
2169 .align 5
2170 .globl EXT(stSpecrs)
2171
2172 LEXT(stSpecrs)
2173
2174
2175 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
2176 li r4,0
2177 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
2178 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit
2179
2180
2181 mfmsr r0 ; Save the MSR
2182 andc r0,r0,r2 ; Turn of VEC and FP
2183 andc r4,r0,r4 ; And EE
2184 mtmsr r4
2185 isync
2186
2187 mfpvr r12
2188 stw r12,4(r3)
2189 rlwinm r12,r12,16,16,31
2190
2191 mfdbatu r4,0
2192 mfdbatl r5,0
2193 mfdbatu r6,1
2194 mfdbatl r7,1
2195 mfdbatu r8,2
2196 mfdbatl r9,2
2197 mfdbatu r10,3
2198 mfdbatl r11,3
2199 stw r4,8(r3)
2200 stw r5,12(r3)
2201 stw r6,16(r3)
2202 stw r7,20(r3)
2203 stw r8,24(r3)
2204 stw r9,28(r3)
2205 stw r10,32(r3)
2206 stw r11,36(r3)
2207
2208 mfibatu r4,0
2209 mfibatl r5,0
2210 mfibatu r6,1
2211 mfibatl r7,1
2212 mfibatu r8,2
2213 mfibatl r9,2
2214 mfibatu r10,3
2215 mfibatl r11,3
2216 stw r4,40(r3)
2217 stw r5,44(r3)
2218 stw r6,48(r3)
2219 stw r7,52(r3)
2220 stw r8,56(r3)
2221 stw r9,60(r3)
2222 stw r10,64(r3)
2223 stw r11,68(r3)
2224
2225 mfsprg r4,0
2226 mfsprg r5,1
2227 mfsprg r6,2
2228 mfsprg r7,3
2229 stw r4,72(r3)
2230 stw r5,76(r3)
2231 stw r6,80(r3)
2232 stw r7,84(r3)
2233
2234 mfsdr1 r4
2235 stw r4,88(r3)
2236
2237 la r4,92(r3)
2238 li r5,0
2239
2240 stSnsr: mfsrin r6,r5
2241 addis r5,r5,0x1000
2242 stw r6,0(r4)
2243 mr. r5,r5
2244 addi r4,r4,4
2245 bne+ stSnsr
2246
2247 cmplwi r12,PROCESSOR_VERSION_750
2248 mfspr r4,hid0
2249 stw r4,(39*4)(r3)
2250
2251 li r4,0
2252 li r5,0
2253 li r6,0
2254 li r7,0
2255
2256 mfspr r4,hid1
2257 mfspr r5,l2cr
2258 mfspr r6,msscr0
2259 mfspr r7,msscr1
2260
2261 stw r4,(40*4)(r3)
2262 stw r6,(42*4)(r3)
2263 stw r5,(41*4)(r3)
2264 stw r7,(43*4)(r3)
2265
2266 li r4,0
2267 beq isis750
2268
2269 mfspr r4,pir
2270 isis750: stw r4,0(r3)
2271
2272 li r4,0
2273 li r5,0
2274 li r6,0
2275 li r7,0
2276 blt- b4750
2277
2278 mfspr r4,thrm1
2279 mfspr r5,thrm2
2280 mfspr r6,thrm3
2281 mfspr r7,ictc
2282
2283 b4750: stw r4,(44*4)(r3)
2284 stw r5,(45*4)(r3)
2285 stw r6,(46*4)(r3)
2286 stw r7,(47*4)(r3)
2287
2288 li r4,0
2289 li r6,0
2290 cmplwi r12,PROCESSOR_VERSION_7400
2291 bne nnmax
2292
2293 mfspr r6,dabr
2294 mfpvr r5
2295 rlwinm r5,r5,0,16,31
2296 cmplwi r5,0x1101
2297 beq gnmax
2298 cmplwi r5,0x1102
2299 bne nnmax
2300
2301 gnmax: mfspr r4,1016
2302
2303 nnmax: stw r4,(48*4)(r3)
2304 stw r6,(49*4)(r3)
2305
2306 mtmsr r0
2307 isync
2308
2309 blr
2310
2311
2312 ;
2313 ; fwEmMck - this forces the hardware to emulate machine checks
2314 ; Only valid on 64-bit machines
2315 ; Note: we want interruptions disabled here
2316 ;
2317
2318 .globl EXT(fwEmMck)
2319
2320 .align 5
2321
2322 LEXT(fwEmMck)
2323
2324
2325 rlwinm r3,r3,0,1,0 ; Copy low of high high - scomd
2326 rlwinm r5,r5,0,1,0 ; Copy low of high high - hid1
2327 rlwinm r7,r7,0,1,0 ; Copy low of high high - hid4
2328 rlwimi r3,r4,0,0,31 ; Copy low of low low
2329 rlwimi r5,r6,0,0,31 ; Copy low of low low
2330 rlwimi r7,r8,0,0,31 ; Copy low of low low
2331
2332 lis r9,3 ; Start forming hid1 error inject mask
2333 lis r10,hi16(0x01084083) ; Start formaing hid4 error inject mask
2334 ori r9,r9,0xC000 ; Next bit
2335 ori r10,r10,lo16(0x01084083) ; Next part
2336 sldi r9,r9,32 ; Shift up high
2337 sldi r10,r10,8 ; Shift into position
2338
2339 mfspr r0,hid1 ; Get hid1
2340 mfspr r2,hid4 ; and hid4
2341
2342 and r5,r5,r9 ; Keep only error inject controls - hid1
2343 and r7,r7,r10 ; Keep only error inject controls - hid4
2344
2345 andc r0,r0,r9 ; Clear error inject controls hid1
2346 andc r2,r2,r10 ; Clear error inject controls hid4
2347
2348 or r0,r0,r5 ; Add in the new controls hid1
2349 or r2,r2,r7 ; Add in the new controls hid4
2350
2351 /* ? */
2352 #if 0
2353 lis r12,CoreErrI ; Get the error inject controls
2354 sync
2355
2356 mtspr scomd,r3 ; Set the error inject controls
2357 mtspr scomc,r12 ; Request error inject
2358 mfspr r11,scomc ; Get back the status (we just ignore it)
2359 #endif
2360 sync
2361 isync
2362
2363 mtspr hid1,r0 ; Move in hid1 controls
2364 mtspr hid1,r0 ; We need to do it twice
2365 isync
2366
2367 sync
2368 mtspr hid4,r2 ; Move in hid4 controls
2369 isync
2370
2371 blr ; Leave...
2372
2373 ;
2374 ; fwSCOMrd - read/write SCOM
2375 ;
2376 .align 5
2377 .globl EXT(fwSCOM)
2378
2379 LEXT(fwSCOM)
2380
2381 lhz r12,scomfunc(r3) ; Get the function
2382 lwz r4,scomreg(r3) ; Get the register
2383 rldicr r4,r4,8,47 ; Position for SCOM
2384
2385 mr. r12,r12 ; See if read or write
2386 bne fwSCwrite ; Go do a write
2387
2388 mfsprg r0,2 ; Get the feature flags
2389 ori r4,r4,0x8000 ; Set to read data
2390 rlwinm. r0,r0,pfSCOMFixUpb+1,31,31 ; Set shift if we need a fix me up
2391 sync
2392
2393 mtspr scomc,r4 ; Request the register
2394 mfspr r11,scomd ; Get the register contents
2395 mfspr r10,scomc ; Get back the status
2396 sync
2397 isync
2398
2399 sld r11,r11,r0 ; Fix up if needed
2400
2401 std r11,scomdata(r3) ; Save result
2402 eieio
2403 std r10,scomstat(r3) ; Save status
2404
2405 blr
2406
2407 fwSCwrite: ld r5,scomdata(r3) ; Get the data
2408
2409 sync
2410
2411 mtspr scomd,r5 ; Set the data
2412 mtspr scomc,r4 ; Set it
2413 mfspr r10,scomc ; Get back the status
2414 sync
2415 isync
2416
2417 std r10,scomstat(r3) ; Save status
2418
2419 blr
2420
2421 ;
2422 ; diagTrap - this is used to trigger checks from user space
2423 ; any "twi 31,r31,0xFFFx" will come here (x = 0 to F).
2424 ; On entry R3 points to savearea.
2425 ; R4 is the "x" from instruction;
2426 ; Pass back 1 to no-op twi and return to user
2427 ; Pass back 0 to treat as normal twi.
2428 ;
2429
2430 .globl EXT(diagTrap)
2431
2432 .align 5
2433
2434 LEXT(diagTrap)
2435
2436 li r3,0 ; Ignore TWI
2437 blr ; Leave...
2438
2439
2440
2441
2442 ;
2443 ; setPmon - this is used to manipulate MMCR0 and MMCR1
2444
2445 .globl EXT(setPmon)
2446
2447 .align 5
2448
2449 LEXT(setPmon)
2450
2451 li r0,0
2452 isync
2453 mtspr mmcr0,r0 ; Clear MMCR0
2454 mtspr mmcr1,r0 ; Clear MMCR1
2455 mtspr pmc1,r0
2456 mtspr pmc2,r0
2457 mtspr pmc3,r0
2458 mtspr pmc4,r0
2459
2460 isync
2461
2462 mtspr mmcr0,r3 ; Set MMCR0
2463 mtspr mmcr1,r4 ; Set MMCR1
2464 isync
2465 blr ; Leave...
2466
2467
mirror of XNU