osfmk/i386/cpuid.h

   1 /*
   2  * Copyright (c) 2000-2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
   7  *
   8  * This file contains Original Code and/or Modifications of Original Code
   9  * as defined in and that are subject to the Apple Public Source License
  10  * Version 2.0 (the 'License'). You may not use this file except in
  11  * compliance with the License. Please obtain a copy of the License at
  12  * http://www.opensource.apple.com/apsl/ and read it before using this
  13  * file.
  14  *
  15  * The Original Code and all software distributed under the License are
  16  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  17  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  18  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  20  * Please see the License for the specific language governing rights and
  21  * limitations under the License.
  22  *
  23  * @APPLE_LICENSE_HEADER_END@
  24  */
  25 /*
  26  * @OSF_COPYRIGHT@
  27  */
  28
  29 /*
  30  * x86 CPU identification
  31  *
  32  */
  33
  34 #ifndef _MACHINE_CPUID_H_
  35 #define _MACHINE_CPUID_H_
  36
  37 #include <sys/appleapiopts.h>
  38
  39 #ifdef __APPLE_API_PRIVATE
  40
  41 #define CPUID_VID_SIZE          12
  42 #define CPUID_VID_INTEL         "GenuineIntel"
  43 #define CPUID_VID_UMC           "UMC UMC UMC "
  44 #define CPUID_VID_AMD           "AuthenticAMD"
  45 #define CPUID_VID_CYRIX         "CyrixInstead"
  46 #define CPUID_VID_NEXTGEN       "NexGenDriven"
  47
  48 #define CPUID_FEATURE_FPU    0x00000001 /* Floating point unit on-chip */
  49 #define CPUID_FEATURE_VME    0x00000002 /* Virtual Mode Extension */
  50 #define CPUID_FEATURE_DE     0x00000004 /* Debugging Extension */
  51 #define CPUID_FEATURE_PSE    0x00000008 /* Page Size Extension */
  52 #define CPUID_FEATURE_TSC    0x00000010 /* Time Stamp Counter */
  53 #define CPUID_FEATURE_MSR    0x00000020 /* Model Specific Registers */
  54 #define CPUID_FEATURE_PAE    0x00000040 /* Physical Address Extension */
  55 #define CPUID_FEATURE_MCE    0x00000080 /* Machine Check Exception */
  56 #define CPUID_FEATURE_CX8    0x00000100 /* CMPXCHG8B */
  57 #define CPUID_FEATURE_APIC   0x00000200 /* On-chip APIC */
  58 #define CPUID_FEATURE_SEP    0x00000800 /* Fast System Call */
  59 #define CPUID_FEATURE_MTRR   0x00001000 /* Memory Type Range Register */
  60 #define CPUID_FEATURE_PGE    0x00002000 /* Page Global Enable */
  61 #define CPUID_FEATURE_MCA    0x00004000 /* Machine Check Architecture */
  62 #define CPUID_FEATURE_CMOV   0x00008000 /* Conditional Move Instruction */
  63 #define CPUID_FEATURE_PAT    0x00010000 /* Page Attribute Table */
  64 #define CPUID_FEATURE_PSE36  0x00020000 /* 36-bit Page Size Extension */
  65 #define CPUID_FEATURE_PSN    0x00040000 /* Processor Serial Number */
  66 #define CPUID_FEATURE_CLFSH  0x00080000 /* CLFLUSH Instruction supported */
  67 #define CPUID_FEATURE_DS     0x00200000 /* Debug Store */
  68 #define CPUID_FEATURE_ACPI   0x00400000 /* Thermal Monitor, SW-controlled clock */
  69 #define CPUID_FEATURE_MMX    0x00800000 /* MMX supported */
  70 #define CPUID_FEATURE_FXSR   0x01000000 /* Fast floating point save/restore */
  71 #define CPUID_FEATURE_SSE    0x02000000 /* Streaming SIMD extensions */
  72 #define CPUID_FEATURE_SSE2   0x04000000 /* Streaming SIMD extensions 2 */
  73 #define CPUID_FEATURE_SS     0x08000000 /* Self-Snoop */
  74 #define CPUID_FEATURE_HTT    0x10000000 /* Hyper-Threading Technology */
  75 #define CPUID_FEATURE_TM     0x20000000 /* Thermal Monitor */
  76
  77 #define CPUID_TYPE_OEM              0x0 /* Original processor */
  78 #define CPUID_TYPE_OVERDRIVE        0x1 /* Overdrive processor */
  79 #define CPUID_TYPE_DUAL             0x2 /* Can be used as dual processor */
  80 #define CPUID_TYPE_RESERVED         0x3 /* Reserved */
  81
  82 #define CPUID_FAMILY_386            0x3 /* Intel 386 (not part of CPUID) */
  83 #define CPUID_FAMILY_486            0x4 /* Intel 486 */
  84 #define CPUID_FAMILY_P5             0x5 /* Intel Pentium */
  85 #define CPUID_FAMILY_PPRO           0x6 /* Intel Pentium Pro, II, III */
  86 #define CPUID_FAMILY_PENTIUM4       0xF /* Intel Pentium 4 */
  87
  88 #define CPUID_MODEL_I386_DX         0x0 /* Intel 386 (not part of CPUID) */
  89
  90 #define CPUID_MODEL_I486_DX         0x0 /* Intel 486DX */
  91 #define CPUID_MODEL_I486_DX_S       0x1 /* Intel 486DX-S */
  92 #define CPUID_MODEL_I486_SX         0x2 /* Intel 486SX */
  93 #define CPUID_MODEL_I486_DX2        0x3 /* Intel 486DX2 */
  94 #define CPUID_MODEL_I486_SL         0x4 /* Intel 486SL */
  95 #define CPUID_MODEL_I486_SX2        0x5 /* Intel 486SX2 */
  96 #define CPUID_MODEL_I486_DX2WB      0x7 /* Intel 486DX2WB */
  97 #define CPUID_MODEL_I486_DX4        0x8 /* Intel 486DX4 */
  98 #define CPUID_MODEL_I486_DX4WB      0x9 /* Intel 486DX4WB */
  99
 100 #define CPUID_MODEL_AM486_DX        0x1 /* AMD 486DX */
 101 #define CPUID_MODEL_AM486_DX2       0x3 /* AMD 486DX2 */
 102 #define CPUID_MODEL_AM486_DX2WB     0x7 /* AMD 486DX2WB */
 103 #define CPUID_MODEL_AM486_DX4       0x8 /* AMD 486DX4 */
 104 #define CPUID_MODEL_AM486_DX4WB     0x9 /* AMD 486DX4WB */
 105 #define CPUID_MODEL_AM486_5X86      0xE /* AMD 5x86 */
 106 #define CPUID_MODEL_AM486_5X86WB    0xF /* AMD 5x86WB */
 107
 108 #define CPUID_MODEL_CYRIX5X86       0x9 /* CYRIX 5X86 */
 109
 110 #define CPUID_MODEL_UMC5SD          0x1 /* UMC U5SD */
 111 #define CPUID_MODEL_UMC5S           0x2 /* UMC U5S */
 112 #define CPUID_MODEL_UMC486_DX2      0x3 /* UMC U486_DX2 */
 113 #define CPUID_MODEL_UMC486_SX2      0x5 /* UMC U486_SX2 */
 114
 115 #define CPUID_MODEL_P5A             0x0 /* Intel P5 60/66 Step A */
 116 #define CPUID_MODEL_P5              0x1 /* Intel P5 60/66 */
 117 #define CPUID_MODEL_P54             0x2 /* Intel P5 75/80/100/120/133/166 */
 118 #define CPUID_MODEL_P24T            0x3 /* Intel P5 Overdrive 63/83 */
 119
 120 #define CPUID_MODEL_P6              0x1 /* Intel P6 */
 121 #define CPUID_MODEL_PII             0x3 /* Intel PII */
 122 #define CPUID_MODEL_P65             0x5 /* Intel PII/Xeon/Celeron model 5 */
 123 #define CPUID_MODEL_P66             0x6 /* Intel Celeron model 6 */
 124 #define CPUID_MODEL_P67             0x7 /* Intel PIII/Xeon model 7 */
 125 #define CPUID_MODEL_P68             0x8 /* Intel PIII/Xeon/Celeron model 8 */
 126 #define CPUID_MODEL_P6A             0xA /* Intel PIII Xeon model A */
 127 #define CPUID_MODEL_P6B             0xB /* Intel PIII model B */
 128
 129 #define CPUID_CACHE_SIZE        16      /* Number of descriptor vales */
 130
 131 #define CPUID_CACHE_NULL           0x00 /* NULL */
 132 #define CPUID_CACHE_ITLB_4K        0x01 /* Instruction TLB, 4K pages */
 133 #define CPUID_CACHE_ITLB_4M        0x02 /* Instruction TLB, 4M pages */
 134 #define CPUID_CACHE_DTLB_4K        0x03 /* Data TLB, 4K pages */
 135 #define CPUID_CACHE_DTLB_4M        0x04 /* Data TLB, 4M pages */
 136 #define CPUID_CACHE_ICACHE_8K      0x06 /* Instruction cache, 8K */
 137 #define CPUID_CACHE_ICACHE_16K     0x08 /* Instruction cache, 16K */
 138 #define CPUID_CACHE_DCACHE_8K      0x0A /* Data cache, 8K */
 139 #define CPUID_CACHE_DCACHE_16K     0x0C /* Data cache, 16K */
 140 #define CPUID_CACHE_UCACHE_128K    0x41 /* 2nd-level cache, 128K */
 141 #define CPUID_CACHE_UCACHE_256K    0x42 /* 2nd-level cache, 256K */
 142 #define CPUID_CACHE_UCACHE_512K    0x43 /* 2nd-level cache, 512K */
 143 #define CPUID_CACHE_UCACHE_1M      0x44 /* 2nd-level cache, 1M */
 144 #define CPUID_CACHE_UCACHE_2M      0x45 /* 2nd-level cache, 2M */
 145 #define CPUID_CACHE_ITLB_64        0x50 /* Instruction TLB, 64 entries */
 146 #define CPUID_CACHE_ITLB_128       0x51 /* Instruction TLB, 128 entries */
 147 #define CPUID_CACHE_ITLB_256       0x52 /* Instruction TLB, 256 entries */
 148 #define CPUID_CACHE_DTLB_64        0x5B /* Data TLB, 64 entries */
 149 #define CPUID_CACHE_DTLB_128       0x5C /* Data TLB, 128 entries */
 150 #define CPUID_CACHE_DTLB_256       0x5D /* Data TLB, 256 entries */
 151 #define CPUID_CACHE_DCACHE_8K_64   0x66 /* Data cache, 8K, 64 byte line size */
 152 #define CPUID_CACHE_DCACHE_16K_64  0x67 /* Data cache, 16K, 64 byte line size */
 153 #define CPUID_CACHE_DCACHE_32K_64  0x68 /* Data cache, 32K, 64 byte line size */
 154 #define CPUID_CACHE_TRACE_12K      0x70 /* Trace cache 12K-uop, 8-way */
 155 #define CPUID_CACHE_TRACE_16K      0x71 /* Trace cache 16K-uop, 8-way */
 156 #define CPUID_CACHE_TRACE_32K      0x72 /* Trace cache 32K-uop, 8-way */
 157 #define CPUID_CACHE_UCACHE_128K_64 0x79 /* 2nd-level, 128K, 8-way, 64 bytes */
 158 #define CPUID_CACHE_UCACHE_256K_64 0x7A /* 2nd-level, 256K, 8-way, 64 bytes */
 159 #define CPUID_CACHE_UCACHE_512K_64 0x7B /* 2nd-level, 512K, 8-way, 64 bytes */
 160 #define CPUID_CACHE_UCACHE_1M_64   0x7C /* 2nd-level, 1M, 8-way, 64 bytes */
 161 #define CPUID_CACHE_UCACHE_256K_32 0x82 /* 2nd-level, 256K, 8-way, 32 bytes */
 162 #define CPUID_CACHE_UCACHE_512K_32 0x83 /* 2nd-level, 512K, 8-way, 32 bytes */
 163 #define CPUID_CACHE_UCACHE_1M_32   0x84 /* 2nd-level, 1M, 8-way, 32 bytes */
 164 #define CPUID_CACHE_UCACHE_2M_32   0x85 /* 2nd-level, 2M, 8-way, 32 bytes */
 165
 166 #ifndef ASSEMBLER
 167 #include <stdint.h>
 168 #include <mach/mach_types.h>
 169 #include <kern/kern_types.h>
 170 #include <mach/machine.h>
 171
 172
 173 static inline void
 174 do_cpuid(uint32_t selector, uint32_t *data)
 175 {
 176         asm("cpuid"
 177                 : "=a" (data[0]),
 178                   "=b" (data[1]),
 179                   "=c" (data[2]),
 180                   "=d" (data[3])
 181                 : "a"(selector));
 182 }
 183
 184 /*
 185  * Cache ID descriptor structure.
 186  * Note: description string absent in kernel.
 187  */
 188 typedef enum { Lnone, L1I, L1D, L2U, LCACHE_MAX } cache_type_t ;
 189 typedef struct {
 190         unsigned char   value;          /* Descriptor value */
 191         cache_type_t    type;           /* Cache type */
 192         unsigned int    size;           /* Cache size */
 193         unsigned int    linesize;       /* Cache line size */
 194 #ifdef KERNEL
 195         char            *description;   /* Cache description */
 196 #endif /* KERNEL */
 197 } cpuid_cache_desc_t;
 198
 199 #ifdef KERNEL
 200 #define CACHE_DESC(value,type,size,linesize,text) \
 201         { value, type, size, linesize, text }
 202 #else
 203 #define CACHE_DESC(value,type,size,linesize,text) \
 204         { value, type, size, linesize }
 205 #endif /* KERNEL */
 206
 207 /* Physical CPU info */
 208 typedef struct {
 209         char            cpuid_vendor[16];
 210         char            cpuid_brand_string[48];
 211
 212         uint32_t        cpuid_value;
 213         cpu_type_t      cpuid_type;
 214         uint8_t         cpuid_family;
 215         uint8_t         cpuid_model;
 216         uint8_t         cpuid_extmodel;
 217         uint8_t         cpuid_extfamily;
 218         uint8_t         cpuid_stepping;
 219         uint32_t        cpuid_features;
 220         uint32_t        cpuid_signature;
 221         uint8_t         cpuid_brand;
 222
 223         uint32_t        cache_size[LCACHE_MAX];
 224         uint32_t        cache_linesize;
 225
 226         char            model_string[64];  /* sanitized model string */
 227         uint8_t         cache_info[64];    /* list of cache descriptors */
 228
 229 } i386_cpu_info_t;
 230
 231
 232 /*
 233  * External declarations
 234  */
 235 extern cpu_type_t       cpuid_cputype(int);
 236 extern void             cpuid_cpu_display(char *, int);
 237 extern void             cpuid_features_display(char *, int);
 238 extern char *           cpuid_get_feature_names(uint32_t, char *, unsigned);
 239
 240 extern uint32_t         cpuid_features(void);
 241 extern uint32_t         cpuid_family(void);
 242
 243 extern char *           cpuid_intel_get_model_name(uint8_t, uint8_t,
 244                                                    uint8_t, uint32_t);
 245
 246 extern i386_cpu_info_t  *cpuid_info(void);
 247
 248 extern uint32_t         cpuid_feature;  /* XXX obsolescent */
 249 #endif /* ASSEMBLER */
 250
 251 #endif /* __APPLE_API_PRIVATE */
 252 #endif /* _MACHINE_CPUID_H_ */