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27 * Low-memory exception vector code for PowerPC MACH
29 * These are the only routines that are ever run with
30 * VM instruction translation switched off.
32 * The PowerPC is quite strange in that rather than having a set
33 * of exception vectors, the exception handlers are installed
34 * in well-known addresses in low memory. This code must be loaded
35 * at ZERO in physical memory. The simplest way of doing this is
36 * to load the kernel at zero, and specify this as the first file
37 * on the linker command line.
39 * When this code is loaded into place, it is loaded at virtual
40 * address KERNELBASE, which is mapped to zero (physical).
42 * This code handles all powerpc exceptions and is always entered
43 * in supervisor mode with translation off. It saves the minimum
44 * processor state before switching back on translation and
45 * jumping to the approprate routine.
47 * Vectors from 0x100 to 0x3fff occupy 0x100 bytes each (64 instructions)
49 * We use some of this space to decide which stack to use, and where to
50 * save the context etc, before jumping to a generic handler.
56 #include <db_machine_commands.h>
59 #include <mach_debug.h>
61 #include <ppc/proc_reg.h>
62 #include <ppc/exception.h>
63 #include <ppc/Performance.h>
64 #include <mach/ppc/vm_param.h>
65 #include <ppc/POWERMAC/mp/MPPlugIn.h>
73 #error The TRCSAVE option is broken.... Fix it
78 #define featAltivec 26
82 #define VECTOR_SEGMENT .section __VECTORS, __interrupts
87 .globl EXT(ExceptionVectorsStart)
89 EXT(ExceptionVectorsStart): /* Used if relocating the exception vectors */
90 baseR: /* Used so we have more readable code */
93 * System reset - call debugger
96 .globl EXT(ResetHandler)
104 mtsprg 2,r13 /* Save R13 */
105 mtsprg 3,r11 /* Save R11 */
106 lwz r13,lo16(EXT(ResetHandler)-EXT(ExceptionVectorsStart)+RESETHANDLER_TYPE)(br0) ; Get reset type
108 cmpi cr0,r13,RESET_HANDLER_START
111 li r11,RESET_HANDLER_NULL
112 stw r11,lo16(EXT(ResetHandler)-EXT(ExceptionVectorsStart)+RESETHANDLER_TYPE)(br0) ; Clear reset type
114 lwz r4,lo16(EXT(ResetHandler)-EXT(ExceptionVectorsStart)+RESETHANDLER_CALL)(br0)
115 lwz r3,lo16(EXT(ResetHandler)-EXT(ExceptionVectorsStart)+RESETHANDLER_ARG)(br0)
121 mfsprg r13,1 /* Get the exception save area */
122 li r11,T_RESET /* Set 'rupt code */
123 b .L_exception_entry /* Join common... */
131 mtsprg 2,r13 /* Save R13 */
132 mtsprg 3,r11 /* Save R11 */
133 mfsprg r13,1 /* Get the exception save area */
134 li r11,T_MACHINE_CHECK /* Set 'rupt code */
135 b .L_exception_entry /* Join common... */
138 * Data access - page fault, invalid memory rights for operation
143 mtsprg 2,r13 /* Save R13 */
144 mtsprg 3,r11 /* Save R11 */
145 mfsprg r13,1 /* Get the exception save area */
146 li r11,T_DATA_ACCESS /* Set 'rupt code */
147 b .L_exception_entry /* Join common... */
150 * Instruction access - as for data access
155 mtsprg 2,r13 /* Save R13 */
156 mtsprg 3,r11 /* Save R11 */
157 mfsprg r13,1 /* Get the exception save area */
158 li r11,T_INSTRUCTION_ACCESS /* Set 'rupt code */
159 b .L_exception_entry /* Join common... */
167 mtsprg 2,r13 /* Save R13 */
168 mtsprg 3,r11 /* Save R11 */
169 mfsprg r13,1 /* Get the exception save area */
170 li r11,T_INTERRUPT /* Set 'rupt code */
171 b .L_exception_entry /* Join common... */
174 * Alignment - many reasons
179 mtsprg 2,r13 /* Save R13 */
180 mtsprg 3,r11 /* Save R11 */
181 mfsprg r13,1 /* Get the exception save area */
182 li r11,T_ALIGNMENT /* Set 'rupt code */
183 b .L_exception_entry /* Join common... */
186 * Program - floating point exception, illegal inst, priv inst, user trap
191 mtsprg 2,r13 /* Save R13 */
192 mtsprg 3,r11 /* Save R11 */
193 mfsprg r13,1 /* Get the exception save area */
194 li r11,T_PROGRAM /* Set 'rupt code */
195 b .L_exception_entry /* Join common... */
198 * Floating point disabled
203 mtsprg 2,r13 /* Save R13 */
204 mtsprg 3,r11 /* Save R11 */
205 mfsprg r13,1 /* Get the exception save area */
206 li r11,T_FP_UNAVAILABLE /* Set 'rupt code */
207 b .L_exception_entry /* Join common... */
211 * Decrementer - DEC register has passed zero.
216 mtsprg 2,r13 /* Save R13 */
217 mtsprg 3,r11 /* Save R11 */
218 mfsprg r13,1 /* Get the exception save area */
219 li r11,T_DECREMENTER /* Set 'rupt code */
220 b .L_exception_entry /* Join common... */
223 * I/O controller interface error - MACH does not use this
228 mtsprg 2,r13 /* Save R13 */
229 mtsprg 3,r11 /* Save R11 */
230 mfsprg r13,1 /* Get the exception save area */
231 li r11,T_IO_ERROR /* Set 'rupt code */
232 b .L_exception_entry /* Join common... */
240 mtsprg 2,r13 /* Save R13 */
241 mtsprg 3,r11 /* Save R11 */
242 mfsprg r13,1 /* Get the exception save area */
243 li r11,T_RESERVED /* Set 'rupt code */
244 b .L_exception_entry /* Join common... */
270 ; System call - generated by the sc instruction
272 ; We handle the ultra-fast traps right here. They are:
274 ; 0xFFFFFFFF - BlueBox only - MKIsPreemptiveTask
275 ; 0xFFFFFFFE - BlueBox only - kcNKIsPreemptiveTaskEnv
276 ; 0x00007FF2 - User state only - thread info
277 ; 0x00007FF3 - User state only - floating point / vector facility status
278 ; 0x00007FF4 - Kernel only - loadMSR
280 ; Note: none handled if virtual machine is running
285 mtsprg 2,r13 ; Save R13
286 mfsrr1 r13 ; Get SRR1 for loadMSR
287 mtsprg 3,r11 ; Save R11
288 mfcr r11 ; Save the CR
289 rlwinm. r13,r13,0,MSR_PR_BIT,MSR_PR_BIT ; From problem state?
290 mfsprg r13,0 ; Get the per_proc_area
291 beq- uftInKern ; We are in the kernel...
293 cmplwi cr5,r0,0x7FF2 ; Ultra fast path cthread info call?
294 cmpwi cr6,r0,0x7FF3 ; Ultra fast path facility status?
295 cror cr1_eq,cr5_lt,cr6_gt ; Set true if not 0x7FF2 and not 0x7FF3 and not negative
296 lwz r13,spcFlags(r13) ; Get the special flags
297 bt- cr1_eq,notufp ; Exit if we can not be ultra fast...
299 rlwimi r13,r13,runningVMbit+1,31,31 ; Move VM flag after the 3 blue box flags
300 not. r0,r0 ; Flip bits and kind of subtract 1
301 mtcrf 1,r13 ; Set BB and VMM flags in CR7
303 cmplwi cr1,r0,1 ; Is this a bb fast path?
304 not r0,r0 ; Restore to entry state
305 bt- 31,notufp ; No fast paths if running VM (assume not)...
306 bf- bbNoMachSCbit,ufpUSuft ; We are not running BlueBox...
307 bgt cr1,notufp ; This can not be a bb ufp...
313 rlwimi r11,r13,bbPreemptivebit-cr0_eq,cr0_eq,cr0_eq ; Copy preemptive task flag into user cr0_eq
314 mfsprg r13,0 ; Get back pre_proc
317 bne cr1,ufpIsBBpre ; This is the "isPreemptiveTask" call...
319 lwz r0,ppbbTaskEnv(r13) ; Get the shadowed taskEnv from per_proc_area
322 mtcrf 0xFF,r11 ; Restore CR
323 mfsprg r11,3 ; Restore R11
324 mfsprg r13,2 ; Restore R13
325 rfi ; All done, go back...
328 ; Normal fast path...
331 ufpUSuft: bge+ notufp ; Bail if negative... (ARRRGGG -- BRANCH TO A BRANCH!!!!!)
332 mfsprg r11,3 ; Restore R11
333 mfsprg r3,0 ; Get the per_proc_area
334 mfsprg r13,2 ; Restore R13
335 bne- cr5,isvecfp ; This is the facility stat call
336 lwz r3,UAW(r3) ; Get the assist word
337 rfi ; All done, scream back... (no need to restore CR or R11, they are volatile)
339 isvecfp: lwz r3,spcFlags(r3) ; Get the facility status
342 notufp: mtcrf 0xFF,r11 ; Restore the used CRs
343 li r11,T_SYSTEM_CALL ; Set interrupt code
344 mfsprg r13,1 ; Get the exception save area
345 b .L_exception_entry ; Join common...
347 uftInKern: cmplwi r0,0x7FF4 ; Ultra fast path loadMSR?
348 bne- notufp ; Someone is trying to cheat...
350 mtcrf 0xFF,r11 ; Restore CR
351 lwz r11,pfAvailable(r13) ; Pick up the feature flags
352 mtsrr1 r3 ; Set new MSR
353 mfsprg r13,2 ; Restore R13
354 mtsprg 2,r11 ; Set the feature flags into sprg2
355 mfsprg r11,3 ; Restore R11
360 * Trace - generated by single stepping
361 * performance monitor BE branch enable tracing/logging
362 * is also done here now. while this is permanently in the
363 * system the impact is completely unnoticable as this code is
364 * only executed when (a) a single step or branch exception is
365 * hit, (b) in the single step debugger case there is so much
366 * overhead already the few extra instructions for testing for BE
367 * are not even noticable, (c) the BE logging code is *only* run
368 * when it is enabled by the tool which will not happen during
369 * normal system usage
371 * Note that this trace is available only to user state so we do not
372 * need to set sprg2 before returning.
377 mtsprg 2,r13 ; Save R13
378 mtsprg 3,r11 ; Save R11
379 mfsrr1 r13 ; Get the old MSR
380 mfcr r11 ; Get the CR
381 rlwinm. r13,r13,0,MSR_PR_BIT,MSR_PR_BIT ; Are we in supervisor state?
382 beq- notspectr ; Yes, not special trace...
383 mfsprg r13,0 ; Get the per_proc area
384 lhz r13,PP_CPU_FLAGS(r13) ; Get the flags
385 rlwinm. r13,r13,0,traceBEb+16,traceBEb+16 ; Special trace enabled?
386 bne+ specbrtr ; Yeah...
388 notspectr: mtcr r11 ; Restore CR
389 mfsprg r13,1 ; Get the savearea
390 li r11,T_TRACE ; Set interrupt code
391 b .L_exception_entry ; Join common...
394 ; We are doing the special branch trace
397 specbrtr: mfsprg r13,0 ; Get the per_proc area
398 stw r1,emfp0(r13) ; Save in a scratch area
399 stw r2,emfp0+4(r13) ; Save in a scratch area
400 stw r3,emfp0+8(r13) ; Save in a scratch area
402 lis r2,hi16(EXT(pc_trace_buf)) ; Get the top of the buffer
403 lwz r3,spcTRp(r13) ; Pick up buffer position
404 mr. r1,r1 ; Is it time to count?
405 ori r2,r2,lo16(EXT(pc_trace_buf)) ; Get the bottom of the buffer
406 cmplwi cr1,r3,4092 ; Set cr1_eq if we should take exception
407 mfsrr0 r1 ; Get the pc
408 stwx r1,r2,r3 ; Save it in the buffer
409 addi r3,r3,4 ; Point to the next slot
410 rlwinm r3,r3,0,20,31 ; Wrap the slot at one page
411 stw r3,spcTRp(r13) ; Save the new slot
412 lwz r1,emfp0(r13) ; Restore work register
413 lwz r2,emfp0+4(r13) ; Restore work register
414 lwz r3,emfp0+8(r13) ; Restore work register
415 beq cr1,notspectr ; Buffer filled, make a rupt...
417 mtcr r11 ; Restore the CR
418 mfsprg r13,2 ; Restore R13
419 mfsprg r11,3 ; Restore R11
423 * Floating point assist
428 mtsprg 2,r13 /* Save R13 */
429 mtsprg 3,r11 /* Save R11 */
430 mfsprg r13,1 /* Get the exception save area */
431 li r11,T_FP_ASSIST /* Set 'rupt code */
432 b .L_exception_entry /* Join common... */
436 * Performance monitor interruption
441 mtsprg 2,r13 /* Save R13 */
442 mtsprg 3,r11 /* Save R11 */
443 mfsprg r13,1 /* Get the exception save area */
444 li r11,T_PERF_MON /* Set 'rupt code */
445 b .L_exception_entry /* Join common... */
454 mtsprg 2,r13 /* Save R13 */
455 mtsprg 3,r11 /* Save R11 */
456 mfsprg r13,1 /* Get the exception save area */
457 li r11,T_VMX /* Set 'rupt code */
458 b .L_exception_entry /* Join common... */
463 * Instruction translation miss - we inline this code.
464 * Upon entry (done for us by the machine):
465 * srr0 : addr of instruction that missed
466 * srr1 : bits 0-3 = saved CR0
469 * msr[tgpr] = 1 (so gpr0-3 become our temporary variables)
470 * imiss: ea that missed
471 * icmp : the compare value for the va that missed
472 * hash1: pointer to first hash pteg
473 * hash2: pointer to 2nd hash pteg
476 * tmp0: saved counter
478 * tmp2: pointer to pteg
479 * tmp3: current compare value
481 * This code is taken from the 603e User's Manual with
482 * some bugfixes and minor improvements to save bytes and cycles
484 * NOTE: Do not touch sprg2 in here
490 mfctr tmp0 /* use tmp0 to save ctr */
493 .L_imiss_find_pte_in_pteg:
494 li tmp1, 8 /* count */
495 subi tmp2, tmp2, 8 /* offset for lwzu */
496 mtctr tmp1 /* count... */
499 lwz tmp1, 8(tmp2) /* check pte0 for match... */
503 bdnzf+ cr0, .L_imiss_pteg_loop
505 bc 0,2, .L_imiss_pteg_loop
507 beq+ cr0, .L_imiss_found_pte
509 /* Not found in PTEG, we must scan 2nd then give up */
511 andi. tmp1, tmp3, MASK(PTE0_HASH_ID)
512 bne- .L_imiss_do_no_hash_exception /* give up */
515 ori tmp3, tmp3, MASK(PTE0_HASH_ID)
516 b .L_imiss_find_pte_in_pteg
520 lwz tmp1, 4(tmp2) /* get pte1_t */
521 andi. tmp3, tmp1, MASK(PTE1_WIMG_GUARD) /* Fault? */
522 bne- .L_imiss_do_prot_exception /* Guarded - illegal */
524 /* Ok, we've found what we need to, restore and rfi! */
526 mtctr tmp0 /* restore ctr */
529 mtcrf 0x80, tmp3 /* Restore CR0 */
530 mtspr rpa, tmp1 /* set the pte */
531 ori tmp1, tmp1, MASK(PTE1_REFERENCED) /* set referenced */
536 .L_imiss_do_prot_exception:
537 /* set up srr1 to indicate protection exception... */
539 andi. tmp2, tmp3, 0xffff
540 addis tmp2, tmp2, MASK(SRR1_TRANS_PROT) >> 16
541 b .L_imiss_do_exception
543 .L_imiss_do_no_hash_exception:
544 /* clean up registers for protection exception... */
546 andi. tmp2, tmp3, 0xffff
547 addis tmp2, tmp2, MASK(SRR1_TRANS_HASH) >> 16
549 /* And the entry into the usual instruction fault handler ... */
550 .L_imiss_do_exception:
552 mtctr tmp0 /* Restore ctr */
553 mtsrr1 tmp2 /* Set up srr1 */
555 xoris tmp0, tmp0, MASK(MSR_TGPR)>>16 /* no TGPR */
556 mtcrf 0x80, tmp3 /* Restore CR0 */
557 mtmsr tmp0 /* reset MSR[TGPR] */
558 b .L_handler400 /* Instr Access */
561 * Data load translation miss
563 * Upon entry (done for us by the machine):
564 * srr0 : addr of instruction that missed
565 * srr1 : bits 0-3 = saved CR0
569 * msr[tgpr] = 1 (so gpr0-3 become our temporary variables)
570 * dmiss: ea that missed
571 * dcmp : the compare value for the va that missed
572 * hash1: pointer to first hash pteg
573 * hash2: pointer to 2nd hash pteg
576 * tmp0: saved counter
578 * tmp2: pointer to pteg
579 * tmp3: current compare value
581 * This code is taken from the 603e User's Manual with
582 * some bugfixes and minor improvements to save bytes and cycles
584 * NOTE: Do not touch sprg2 in here
590 mfctr tmp0 /* use tmp0 to save ctr */
593 .L_dlmiss_find_pte_in_pteg:
594 li tmp1, 8 /* count */
595 subi tmp2, tmp2, 8 /* offset for lwzu */
596 mtctr tmp1 /* count... */
599 lwz tmp1, 8(tmp2) /* check pte0 for match... */
602 #if 0 /* How to write this correctly? */
603 bdnzf+ cr0, .L_dlmiss_pteg_loop
605 bc 0,2, .L_dlmiss_pteg_loop
607 beq+ cr0, .L_dmiss_found_pte
609 /* Not found in PTEG, we must scan 2nd then give up */
611 andi. tmp1, tmp3, MASK(PTE0_HASH_ID) /* already at 2nd? */
612 bne- .L_dmiss_do_no_hash_exception /* give up */
615 ori tmp3, tmp3, MASK(PTE0_HASH_ID)
616 b .L_dlmiss_find_pte_in_pteg
620 lwz tmp1, 4(tmp2) /* get pte1_t */
622 /* Ok, we've found what we need to, restore and rfi! */
624 mtctr tmp0 /* restore ctr */
627 mtcrf 0x80, tmp3 /* Restore CR0 */
628 mtspr rpa, tmp1 /* set the pte */
629 ori tmp1, tmp1, MASK(PTE1_REFERENCED) /* set referenced */
630 tlbld tmp0 /* load up tlb */
631 sth tmp1, 6(tmp2) /* sth is faster? */
634 /* This code is shared with data store translation miss */
636 .L_dmiss_do_no_hash_exception:
637 /* clean up registers for protection exception... */
639 /* prepare to set DSISR_WRITE_BIT correctly from srr1 info */
640 rlwinm tmp1, tmp3, 9, 6, 6
641 addis tmp1, tmp1, MASK(DSISR_HASH) >> 16
643 /* And the entry into the usual data fault handler ... */
645 mtctr tmp0 /* Restore ctr */
646 andi. tmp2, tmp3, 0xffff /* Clean up srr1 */
647 mtsrr1 tmp2 /* Set srr1 */
652 xoris tmp0, tmp0, MASK(MSR_TGPR)>>16 /* no TGPR */
653 mtcrf 0x80, tmp3 /* Restore CR0 */
654 sync /* Needed on some */
655 mtmsr tmp0 /* reset MSR[TGPR] */
656 b .L_handler300 /* Data Access */
659 * Data store translation miss (similar to data load)
661 * Upon entry (done for us by the machine):
662 * srr0 : addr of instruction that missed
663 * srr1 : bits 0-3 = saved CR0
667 * msr[tgpr] = 1 (so gpr0-3 become our temporary variables)
668 * dmiss: ea that missed
669 * dcmp : the compare value for the va that missed
670 * hash1: pointer to first hash pteg
671 * hash2: pointer to 2nd hash pteg
674 * tmp0: saved counter
676 * tmp2: pointer to pteg
677 * tmp3: current compare value
679 * This code is taken from the 603e User's Manual with
680 * some bugfixes and minor improvements to save bytes and cycles
682 * NOTE: Do not touch sprg2 in here
688 mfctr tmp0 /* use tmp0 to save ctr */
691 .L_dsmiss_find_pte_in_pteg:
692 li tmp1, 8 /* count */
693 subi tmp2, tmp2, 8 /* offset for lwzu */
694 mtctr tmp1 /* count... */
697 lwz tmp1, 8(tmp2) /* check pte0 for match... */
701 #if 0 /* I don't know how to write this properly */
702 bdnzf+ cr0, .L_dsmiss_pteg_loop
704 bc 0,2, .L_dsmiss_pteg_loop
706 beq+ cr0, .L_dsmiss_found_pte
708 /* Not found in PTEG, we must scan 2nd then give up */
710 andi. tmp1, tmp3, MASK(PTE0_HASH_ID) /* already at 2nd? */
711 bne- .L_dmiss_do_no_hash_exception /* give up */
714 ori tmp3, tmp3, MASK(PTE0_HASH_ID)
715 b .L_dsmiss_find_pte_in_pteg
719 lwz tmp1, 4(tmp2) /* get pte1_t */
720 andi. tmp3, tmp1, MASK(PTE1_CHANGED) /* unchanged, check? */
721 beq- .L_dsmiss_check_prot /* yes, check prot */
724 /* Ok, we've found what we need to, restore and rfi! */
726 mtctr tmp0 /* restore ctr */
729 mtcrf 0x80, tmp3 /* Restore CR0 */
730 mtspr rpa, tmp1 /* set the pte */
731 tlbld tmp0 /* load up tlb */
734 .L_dsmiss_check_prot:
735 /* PTE is unchanged, we must check that we can write */
736 rlwinm. tmp3, tmp1, 30, 0, 1 /* check PP[1] */
737 bge- .L_dsmiss_check_prot_user_kern
738 andi. tmp3, tmp1, 1 /* check PP[0] */
739 beq+ .L_dsmiss_check_prot_ok
741 .L_dmiss_do_prot_exception:
742 /* clean up registers for protection exception... */
744 /* prepare to set DSISR_WRITE_BIT correctly from srr1 info */
745 rlwinm tmp1, tmp3, 9, 6, 6
746 addis tmp1, tmp1, MASK(DSISR_PROT) >> 16
748 /* And the entry into the usual data fault handler ... */
750 mtctr tmp0 /* Restore ctr */
751 andi. tmp2, tmp3, 0xffff /* Clean up srr1 */
752 mtsrr1 tmp2 /* Set srr1 */
757 xoris tmp0, tmp0, MASK(MSR_TGPR)>>16 /* no TGPR */
758 mtcrf 0x80, tmp3 /* Restore CR0 */
759 sync /* Needed on some */
760 mtmsr tmp0 /* reset MSR[TGPR] */
761 b .L_handler300 /* Data Access */
763 /* NB - if we knew we were on a 603e we could test just the MSR_KEY bit */
764 .L_dsmiss_check_prot_user_kern:
766 andi. tmp3, tmp3, MASK(MSR_PR)
767 beq+ .L_dsmiss_check_prot_kern
768 mfspr tmp3, dmiss /* check user privs */
769 mfsrin tmp3, tmp3 /* get excepting SR */
770 andis. tmp3, tmp3, 0x2000 /* Test SR ku bit */
771 beq+ .L_dsmiss_check_prot_ok
772 b .L_dmiss_do_prot_exception
774 .L_dsmiss_check_prot_kern:
775 mfspr tmp3, dmiss /* check kern privs */
777 andis. tmp3, tmp3, 0x4000 /* Test SR Ks bit */
778 bne- .L_dmiss_do_prot_exception
780 .L_dsmiss_check_prot_ok:
781 /* Ok, mark as referenced and changed before resolving the fault */
782 ori tmp1, tmp1, (MASK(PTE1_REFERENCED)|MASK(PTE1_CHANGED))
787 * Instruction address breakpoint
792 mtsprg 2,r13 /* Save R13 */
793 mtsprg 3,r11 /* Save R11 */
794 mfsprg r13,1 /* Get the exception save area */
795 li r11,T_INSTRUCTION_BKPT /* Set 'rupt code */
796 b .L_exception_entry /* Join common... */
799 * System management interrupt
804 mtsprg 2,r13 /* Save R13 */
805 mtsprg 3,r11 /* Save R11 */
806 mfsprg r13,1 /* Get the exception save area */
807 li r11,T_SYSTEM_MANAGEMENT /* Set 'rupt code */
808 b .L_exception_entry /* Join common... */
811 ; Altivec Java Mode Assist interrupt
816 mtsprg 2,r13 /* Save R13 */
817 mtsprg 3,r11 /* Save R11 */
818 mfsprg r13,1 /* Get the exception save area */
819 li r11,T_ALTIVEC_ASSIST /* Set 'rupt code */
820 b .L_exception_entry /* Join common... */
823 ; Thermal interruption
828 mtsprg 2,r13 /* Save R13 */
829 mtsprg 3,r11 /* Save R11 */
830 mfsprg r13,1 /* Get the exception save area */
831 li r11,T_THERMAL /* Set 'rupt code */
832 b .L_exception_entry /* Join common... */
835 * There is now a large gap of reserved traps
839 * Run mode/ trace exception - single stepping on 601 processors
844 mtsprg 2,r13 /* Save R13 */
845 mtsprg 3,r11 /* Save R11 */
846 mfsprg r13,1 /* Get the exception save area */
847 li r11,T_RUNMODE_TRACE /* Set 'rupt code */
848 b .L_exception_entry /* Join common... */
851 * .L_exception_entry(type)
853 * This is the common exception handling routine called by any
854 * type of system exception.
856 * ENTRY: via a system exception handler, thus interrupts off, VM off.
857 * r3 has been saved in sprg3 and now contains a number
858 * representing the exception's origins
864 .globl EXT(exception_entry)
865 EXT(exception_entry):
866 .long .L_exception_entry-EXT(ExceptionVectorsStart) /* phys addr of fn */
875 * Here we will save off a mess of registers, the special ones and R0-R12. We use the DCBZ
876 * instruction to clear and allcoate a line in the cache. This way we won't take any cache
877 * misses, so these stores won't take all that long. Except the first line that is because
878 * we can't do a DCBZ if the L1 D-cache is off. The rest we will skip if they are
881 * Note that if we are attempting to sleep (as opposed to nap or doze) all interruptions
885 stw r1,saver1(r13) ; Save register 1
886 stw r0,saver0(r13) ; Save register 0
887 mfspr r1,hid0 ; Get HID0
888 mfcr r0 ; Save the CR
889 mtcrf 255,r1 ; Get set to test for cache and sleep
890 bf sleep,notsleep ; Skip if we are not trying to sleep
892 mtcrf 255,r0 ; Restore the CR
893 lwz r0,saver0(r13) ; Restore R0
894 lwz r1,saver1(r13) ; Restore R1
895 mfsprg r13,0 ; Get the per_proc
896 lwz r11,pfAvailable(r13) ; Get back the feature flags
897 mfsprg r13,2 ; Restore R13
898 mtsprg 2,r11 ; Set sprg2 to the features
899 mfsprg r11,3 ; Restore R11
900 rfi ; Jump back into sleep code...
901 .long 0 ; Leave these here please...
912 notsleep: stw r2,saver2(r13) ; Save this one
913 crmove featL1ena,dce ; Copy the cache enable bit
914 rlwinm r2,r1,0,nap+1,doze-1 ; Clear any possible nap and doze bits
915 mtspr hid0,r2 ; Clear the nap/doze bits
916 cmplw r2,r1 ; See if we were napping
917 li r1,32 ; Point to the next line in case we need it
918 crnot wasNapping,cr0_eq ; Remember if we were napping
919 mfsprg r2,0 ; Get the per_proc area
920 bf- featL1ena,skipz1 ; L1 cache is disabled...
921 dcbz r1,r13 ; Reserve our line in cache
924 ; Remember, we are setting up CR6 with feature flags
926 skipz1: lwz r1,pfAvailable(r2) ; Get the CPU features flags
927 stw r3,saver3(r13) ; Save this one
928 mtcrf 0xE0,r1 ; Put the features flags (that we care about) in the CR
929 stw r4,saver4(r13) ; Save this one
930 stw r6,saver6(r13) ; Save this one
931 crmove featSMP,pfSMPcapb ; See if we have a PIR
932 stw r8,saver8(r13) ; Save this one
933 crmove featAltivec,pfAltivecb ; Set the Altivec flag
934 mfsrr0 r6 /* Get the interruption SRR0 */
935 stw r8,saver8(r13) /* Save this one */
936 crmove featFP,pfFloatb ; Remember that we have floating point
937 stw r7,saver7(r13) /* Save this one */
938 lhz r8,PP_CPU_FLAGS(r2) ; Get the flags
939 mfsrr1 r7 /* Get the interrupt SRR1 */
940 rlwinm r8,r8,(((31-MSR_BE_BIT)+(traceBEb+16+1))&31),MSR_BE_BIT,MSR_BE_BIT ; Set BE bit if special trace is on
941 stw r6,savesrr0(r13) /* Save the SRR0 */
942 rlwinm r6,r7,(((31-MSR_BE_BIT)+(MSR_PR_BIT+1))&31),MSR_BE_BIT,MSR_BE_BIT ; Move PR bit to BE bit
943 stw r5,saver5(r13) /* Save this one */
944 and r8,r6,r8 ; Remove BE bit only if problem state and special tracing on
945 mfsprg r6,2 ; Get interrupt time R13
946 mtsprg 2,r1 ; Set the feature flags
947 andc r7,r7,r8 ; Clear BE bit if special trace is on and PR is set
948 mfsprg r8,3 /* Get 'rupt time R11 */
949 stw r7,savesrr1(r13) /* Save SRR1 */
950 stw r6,saver13(r13) /* Save 'rupt R1 */
951 stw r8,saver11(r13) /* Save 'rupt time R11 */
953 getTB: mftbu r6 ; Get the upper timebase
954 mftb r7 ; Get the lower timebase
955 mftbu r8 ; Get the upper one again
956 cmplw r6,r8 ; Did the top tick?
957 bne- getTB ; Yeah, need to get it again...
959 stw r8,ruptStamp(r2) ; Save the top of time stamp
960 la r6,saver14(r13) ; Point to the next cache line
961 stw r7,ruptStamp+4(r2) ; Save the bottom of time stamp
962 bf- featL1ena,skipz2 ; L1 cache is disabled...
963 dcbz 0,r6 /* Allocate in cache */
965 stw r9,saver9(r13) /* Save this one */
967 la r9,saver30(r13) /* Point to the trailing end */
968 stw r10,saver10(r13) /* Save this one */
969 mflr r4 /* Get the LR */
970 mfxer r10 ; Get the XER
972 bf+ wasNapping,notNapping ; Skip if not waking up from nap...
974 lwz r6,napStamp+4(r2) ; Pick up low order nap stamp
975 lis r3,hi16(EXT(machine_idle_ret)) ; Get high part of nap/doze return
976 lwz r5,napStamp(r2) ; and high order
977 subfc r7,r6,r7 ; Subtract low stamp from now
978 lwz r6,napTotal+4(r2) ; Pick up low total
979 subfe r5,r5,r8 ; Subtract high stamp and borrow from now
980 lwz r8,napTotal(r2) ; Pick up the high total
981 addc r6,r6,r7 ; Add low to total
982 ori r3,r3,lo16(EXT(machine_idle_ret)) ; Get low part of nap/doze return
983 adde r8,r8,r5 ; Add high and carry to total
984 stw r6,napTotal+4(r2) ; Save the low total
985 stw r8,napTotal(r2) ; Save the high total
986 stw r3,savesrr0(r13) ; Modify to return to nap/doze exit
989 notNapping: stw r12,saver12(r13) /* Save this one */
991 bf- featL1ena,skipz3 ; L1 cache is disabled...
992 dcbz 0,r9 /* Allocate the last in the area */
994 stw r14,saver14(r13) /* Save this one */
995 stw r15,saver15(r13) /* Save this one */
996 la r14,saver22(r13) /* Point to the next block to save into */
997 stw r0,savecr(r13) ; Save rupt CR
998 mfctr r6 /* Get the CTR */
999 stw r16,saver16(r13) /* Save this one */
1000 stw r4,savelr(r13) /* Save 'rupt LR */
1002 bf- featL1ena,skipz4 ; L1 cache is disabled...
1003 dcbz 0,r14 /* Allocate next save area line */
1005 stw r17,saver17(r13) /* Save this one */
1006 stw r18,saver18(r13) /* Save this one */
1007 stw r6,savectr(r13) /* Save 'rupt CTR */
1008 stw r19,saver19(r13) /* Save this one */
1009 lis r12,HIGH_ADDR(KERNEL_SEG_REG0_VALUE) /* Get the high half of the kernel SR0 value */
1010 mfdar r6 /* Get the 'rupt DAR */
1011 stw r20,saver20(r13) /* Save this one */
1013 mfsr r14,sr0 ; (TEST/DEBUG)
1014 stw r14,savesr0(r13) ; (TEST/DEBUG)
1015 mfsr r14,sr1 ; (TEST/DEBUG)
1016 stw r14,savesr1(r13) ; (TEST/DEBUG)
1017 mfsr r14,sr2 ; (TEST/DEBUG)
1018 stw r14,savesr2(r13) ; (TEST/DEBUG)
1019 mfsr r14,sr3 ; (TEST/DEBUG)
1020 stw r14,savesr3(r13) ; (TEST/DEBUG)
1021 mfsr r14,sr4 ; (TEST/DEBUG)
1022 stw r14,savesr4(r13) ; (TEST/DEBUG)
1023 mfsr r14,sr5 ; (TEST/DEBUG)
1024 stw r14,savesr5(r13) ; (TEST/DEBUG)
1025 mfsr r14,sr6 ; (TEST/DEBUG)
1026 stw r14,savesr6(r13) ; (TEST/DEBUG)
1027 mfsr r14,sr7 ; (TEST/DEBUG)
1028 stw r14,savesr7(r13) ; (TEST/DEBUG)
1029 mfsr r14,sr8 ; (TEST/DEBUG)
1030 stw r14,savesr8(r13) ; (TEST/DEBUG)
1031 mfsr r14,sr9 ; (TEST/DEBUG)
1032 stw r14,savesr9(r13) ; (TEST/DEBUG)
1033 mfsr r14,sr10 ; (TEST/DEBUG)
1034 stw r14,savesr10(r13) ; (TEST/DEBUG)
1035 mfsr r14,sr11 ; (TEST/DEBUG)
1036 stw r14,savesr11(r13) ; (TEST/DEBUG)
1037 mfsr r14,sr12 ; (TEST/DEBUG)
1038 stw r14,savesr12(r13) ; (TEST/DEBUG)
1039 mfsr r14,sr13 ; (TEST/DEBUG)
1040 stw r14,savesr13(r13) ; (TEST/DEBUG)
1041 mfsr r14,sr15 ; (TEST/DEBUG)
1042 stw r14,savesr15(r13) ; (TEST/DEBUG)
1045 mtsr sr0,r12 /* Set the kernel SR0 */
1046 stw r21,saver21(r13) /* Save this one */
1047 addis r12,r12,0x0010 ; Point to the second segment of kernel
1048 stw r10,savexer(r13) ; Save the rupt XER
1049 mtsr sr1,r12 /* Set the kernel SR1 */
1050 stw r30,saver30(r13) /* Save this one */
1051 addis r12,r12,0x0010 ; Point to the third segment of kernel
1052 stw r31,saver31(r13) /* Save this one */
1053 mtsr sr2,r12 /* Set the kernel SR2 */
1054 stw r22,saver22(r13) /* Save this one */
1055 addis r12,r12,0x0010 ; Point to the third segment of kernel
1056 la r10,savedar(r13) /* Point to exception info block */
1057 stw r23,saver23(r13) /* Save this one */
1058 mtsr sr3,r12 /* Set the kernel SR3 */
1059 stw r24,saver24(r13) /* Save this one */
1060 stw r25,saver25(r13) /* Save this one */
1061 mfdsisr r7 /* Get the 'rupt DSISR */
1062 stw r26,saver26(r13) /* Save this one */
1064 bf- featL1ena,skipz5 ; L1 cache is disabled...
1065 dcbz 0,r10 /* Allocate exception info line */
1068 stw r27,saver27(r13) /* Save this one */
1069 li r10,emfp0 ; Point to floating point save
1070 stw r28,saver28(r13) /* Save this one */
1071 stw r29,saver29(r13) /* Save this one */
1072 mfsr r14,sr14 ; Get the copyin/out segment register
1073 stw r6,savedar(r13) /* Save the 'rupt DAR */
1074 bf- featL1ena,skipz5a ; Do not do this if no L1...
1075 dcbz r10,r2 ; Clear and allocate an L1 slot
1077 skipz5a: stw r7,savedsisr(r13) /* Save the 'rupt code DSISR */
1078 stw r11,saveexception(r13) /* Save the exception code */
1079 stw r14,savesr14(r13) ; Save copyin/copyout
1081 lis r8,HIGH_ADDR(EXT(saveanchor)) /* Get the high part of the anchor */
1082 li r19,0 ; Assume no Altivec
1083 ori r8,r8,LOW_ADDR(EXT(saveanchor)) /* Bottom half of the anchor */
1085 bf featAltivec,noavec ; No Altivec on this CPU...
1086 li r9,0 ; Get set to clear VRSAVE
1087 mfspr r19,vrsave ; Get the VRSAVE register
1088 mtspr vrsave,r9 ; Clear VRSAVE for each interrupt level
1090 ; We need to save the FPSCR as if it is normal context.
1091 ; This is because pending exceptions will cause an exception even if
1092 ; FP is disabled. We need to clear the FPSCR when we first start running in the
1095 noavec: stw r19,savevrsave(r13) ; Save the vector register usage flags
1097 bf- featFP,nofpexe ; No possible floating point exceptions...
1099 mfmsr r9 ; Get the MSR value
1100 ori r7,r9,lo16(MASK(MSR_FP)) ; Enable floating point
1103 stfd f0,emfp0(r2) ; Save FPR0
1104 stfd f1,emfp1(r2) ; Save FPR1
1105 mffs f0 ; Get the FPSCR
1106 fsub f1,f1,f1 ; Make a 0
1107 stfd f0,savexfpscrpad(r13) ; Save the FPSCR
1108 mtfsf 0xFF,f1 ; Clear it
1109 lfd f0,emfp0(r2) ; Restore FPR0
1110 lfd f1,emfp1(r2) ; Restore FPR1
1111 mtmsr r9 ; Turn off FP
1116 * Everything is saved at this point, except for FPRs, and VMX registers
1118 * Time for a new save area. Allocate the trace table entry now also
1119 * Note that we haven't touched R0-R5 yet. Except for R0 & R1, that's in the save
1123 lllck: lwarx r9,0,r8 /* Grab the lock value */
1124 li r7,1 /* Use part of the delay time */
1125 mr. r9,r9 /* Is it locked? */
1126 bne- lllcks /* Yeah, wait for it to clear... */
1127 stwcx. r7,0,r8 /* Try to seize that there durn lock */
1128 beq+ lllckd /* Got it... */
1129 b lllck /* Collision, try again... */
1131 lllcks: lwz r9,SVlock(r8) /* Get that lock in here */
1132 mr. r9,r9 /* Is it free yet? */
1133 beq+ lllck /* Yeah, try for it again... */
1134 b lllcks /* Sniff away... */
1136 lllckd: isync /* Purge any speculative executions here */
1137 lis r23,hi16(EXT(trcWork)) ; Get the work area address
1138 rlwinm r7,r11,30,0,31 /* Save 'rupt code shifted right 2 */
1139 ori r23,r23,lo16(EXT(trcWork)) ; Get the rest
1141 lwz r14,traceMask(r23) /* Get the trace mask */
1143 li r14,-1 /* (TEST/DEBUG) */
1145 addi r7,r7,10 /* Adjust for CR5_EQ position */
1146 lwz r15,SVfree(r8) /* Get the head of the save area list */
1147 lwz r25,SVinuse(r8) /* Get the in use count */
1148 rlwnm r7,r14,r7,22,22 /* Set CR5_EQ bit position to 0 if tracing allowed */
1149 lwz r20,traceCurr(r23) /* Pick up the current trace entry */
1150 mtcrf 0x04,r7 /* Set CR5 to show trace or not */
1152 lwz r14,SACalloc(r15) /* Pick up the allocation bits */
1153 addi r25,r25,1 /* Bump up the in use count for the new savearea */
1154 lwz r21,traceEnd(r23) /* Grab up the end of it all */
1155 mr. r14,r14 /* Can we use the first one? */
1156 blt use1st /* Yeah... */
1158 andis. r14,r14,0x8000 /* Show we used the second and remember if it was the last */
1159 addi r10,r15,0x0800 /* Point to the first one */
1160 b gotsave /* We have the area now... */
1162 use1st: andis. r14,r14,0x4000 /* Mark first gone and remember if empty */
1163 mr r10,r15 /* Set the save area */
1165 gotsave: stw r14,SACalloc(r15) /* Put back the allocation bits */
1166 bne nodqsave /* There's still an empty slot, don't dequeue... */
1168 lwz r16,SACnext(r15) /* Get the next in line */
1169 stw r16,SVfree(r8) /* Dequeue our now empty save area block */
1171 nodqsave: addi r22,r20,LTR_size /* Point to the next trace entry */
1172 stw r25,SVinuse(r8) /* Set the in use count */
1173 li r17,0 /* Clear this for the lock */
1174 cmplw r22,r21 /* Do we need to wrap the trace table? */
1175 stw r17,SAVprev(r10) /* Clear back pointer for the newly allocated guy */
1176 mtsprg 1,r10 /* Get set for the next 'rupt */
1177 bne+ gotTrcEnt /* We got a trace entry... */
1179 lwz r22,traceStart(r23) /* Wrap back to the top */
1181 gotTrcEnt: bne- cr5,skipTrace1 /* Don't want to trace this kind... */
1183 stw r22,traceCurr(r23) /* Set the next entry for the next guy */
1186 dcbst br0,r23 ; (TEST/DEBUG)
1190 bf- featL1ena,skipz6 ; L1 cache is disabled...
1191 dcbz 0,r20 /* Allocate cache for the entry */
1194 skipTrace1: sync /* Make sure all stores are done */
1195 stw r17,SVlock(r8) /* Unlock both save and trace areas */
1199 * At this point, we can take another exception and lose nothing.
1201 * We still have the current savearea pointed to by R13, the next by R10 and
1202 * sprg1. R20 contains the pointer to a trace entry and CR5_eq says
1203 * to do the trace or not.
1205 * Note that R13 was chosen as the save area pointer because the SIGP,
1206 * firmware, and DSI/ISI handlers aren't supposed to touch anything
1207 * over R12. But, actually, the DSI/ISI stuff does.
1210 * Let's cut that trace entry now.
1213 lwz r0,saver0(r13) ; Get back interrupt time R0
1214 bne- cr5,skipTrace2 /* Don't want to trace this kind... */
1216 mfsprg r2,0 ; Get the per_proc
1217 li r14,32 /* Second line of entry */
1219 lwz r16,ruptStamp(r2) ; Get top of time base
1220 lwz r17,ruptStamp+4(r2) ; Get the bottom of time stamp
1222 bf- featL1ena,skipz7 ; L1 cache is disabled...
1223 dcbz r14,r20 /* Zap the second half */
1225 skipz7: stw r16,LTR_timeHi(r20) /* Set the upper part of TB */
1226 bf featSMP,nopir4 ; Is there a processor ID register on this guy?
1227 mfspr r19,pir /* Get the processor address */
1228 b gotpir4 /* Got it... */
1229 nopir4: li r19,0 /* Assume processor 0 for those underprivileged folks */
1231 lwz r1,saver1(r13) ; Get back interrupt time R1
1232 stw r17,LTR_timeLo(r20) /* Set the lower part of TB */
1233 rlwinm r19,r19,0,27,31 /* Cut the junk */
1234 lwz r2,saver2(r13) ; Get back interrupt time R2
1235 stw r0,LTR_r0(r20) /* Save off register 0 */
1236 lwz r3,saver3(r13) ; Restore this one
1237 sth r19,LTR_cpu(r20) /* Stash the cpu address */
1238 stw r1,LTR_r1(r20) /* Save off register 1 */
1239 lwz r4,saver4(r13) ; Restore this one
1240 stw r2,LTR_r2(r20) /* Save off register 2 */
1241 lwz r5,saver5(r13) ; Restore this one
1242 stw r3,LTR_r3(r20) /* Save off register 3 */
1243 lwz r16,savecr(r13) /* We don't remember the CR anymore, get it */
1244 stw r4,LTR_r4(r20) /* Save off register 4 */
1245 mfsrr0 r17 /* Get this back, it's still good */
1246 stw r5,LTR_r5(r20) /* Save off register 5 */
1247 mfsrr1 r18 /* This is still good in here also */
1249 stw r16,LTR_cr(r20) /* Save the CR (or dec) */
1250 stw r17,LTR_srr0(r20) /* Save the SSR0 */
1251 stw r18,LTR_srr1(r20) /* Save the SRR1 */
1252 mfdar r17 /* Get this back */
1254 mflr r16 /* Get the LR */
1255 stw r17,LTR_dar(r20) /* Save the DAR */
1256 mfctr r17 /* Get the CTR */
1257 stw r16,LTR_lr(r20) /* Save the LR */
1259 lis r17,HIGH_ADDR(EXT(saveanchor)) ; (TEST/DEBUG)
1260 ori r17,r17,LOW_ADDR(EXT(saveanchor)) ; (TEST/DEBUG)
1261 lwz r16,SVcount(r17) ; (TEST/DEBUG)
1262 lwz r17,SVinuse(r17) ; (TEST/DEBUG)
1263 rlwimi r17,r16,16,0,15 ; (TEST/DEBUG)
1265 stw r17,LTR_ctr(r20) /* Save off the CTR */
1266 stw r13,LTR_save(r20) /* Save the savearea */
1267 sth r11,LTR_excpt(r20) /* Save the exception type */
1269 addi r17,r20,32 ; (TEST/DEBUG)
1270 dcbst br0,r20 ; (TEST/DEBUG)
1271 dcbst br0,r17 ; (TEST/DEBUG)
1276 * We're done with the trace, except for maybe modifying the exception
1277 * code later on. So, that means that we need to save R20 and CR5, but
1278 * R0 to R5 are clear now.
1280 * So, let's finish setting up the kernel registers now.
1285 #if PERFTIMES && DEBUG
1286 li r3,68 ; Indicate interrupt
1287 mr r4,r11 ; Get code to log
1288 mr r5,r13 ; Get savearea to log
1290 bl EXT(dbgLog2) ; Cut log entry
1291 mr r0,r8 ; Restore R0
1294 mfsprg r2,0 /* Get the per processor block */
1298 lis r4,0x7FFF /* (TEST/DEBUG) */
1299 mfdec r12 /* (TEST/DEBUG) */
1300 or r4,r4,r12 /* (TEST/DEBUG) */
1301 mtdec r4 /* (TEST/DEBUG) */
1302 li r4,0x20 /* (TEST/DEBUG) */
1306 mpwait2: lwarx r8,0,r4 /* (TEST/DEBUG) */
1307 mr. r8,r8 /* (TEST/DEBUG) */
1308 bne- mpwait2 /* (TEST/DEBUG) */
1309 stwcx. r4,0,r4 /* (TEST/DEBUG) */
1310 bne- mpwait2 /* (TEST/DEBUG) */
1312 isync /* (TEST/DEBUG) */
1313 lwz r4,0xE80(br0) /* (TEST/DEBUG) */
1314 mr. r4,r4 /* (TEST/DEBUG) */
1315 li r4,1 /* (TEST/DEBUG) */
1316 bne- doncheksv /* (TEST/DEBUG) */
1318 lis r8,HIGH_ADDR(EXT(saveanchor)) /* (TEST/DEBUG) */
1319 ori r8,r8,LOW_ADDR(EXT(saveanchor)) /* (TEST/DEBUG) */
1321 stw r4,0xE80(br0) /* (TEST/DEBUG) */
1325 mpwait2x: lwarx r4,0,r8 /* (TEST/DEBUG) */
1326 mr. r4,r4 /* (TEST/DEBUG) */
1327 bne- mpwait2x /* (TEST/DEBUG) */
1328 stwcx. r8,0,r8 /* (TEST/DEBUG) */
1329 bne- mpwait2x /* (TEST/DEBUG) */
1331 isync /* (TEST/DEBUG) */
1333 rlwinm r4,r13,0,0,19 /* (TEST/DEBUG) */
1334 lwz r21,SACflags(r4) /* (TEST/DEBUG) */
1335 rlwinm r22,r21,24,24,31 /* (TEST/DEBUG) */
1336 cmplwi r22,0x00EE /* (TEST/DEBUG) */
1337 lwz r22,SACvrswap(r4) /* (TEST/DEBUG) */
1338 bnel- currbad /* (TEST/DEBUG) */
1339 andis. r21,r21,hi16(sac_perm) /* (TEST/DEBUG) */
1340 bne- currnotbad /* (TEST/DEBUG) */
1341 mr. r22,r22 /* (TEST/DEBUG) */
1342 bne+ currnotbad /* (TEST/DEBUG) */
1344 currbad: lis r23,hi16(EXT(debugbackpocket)) /* (TEST/DEBUG) */
1345 ori r23,r23,lo16(EXT(debugbackpocket)) /* (TEST/DEBUG) */
1346 lwz r23,0(r23) ; (TEST/DEBUG)
1347 stw r23,SVfree(r8) /* (TEST/DEBUG) */
1349 mfsprg r25,1 /* (TEST/DEBUG) */
1350 mtsprg 1,r23 /* (TEST/DEBUG) */
1351 lwz r26,SACalloc(r23) /* (TEST/DEBUG) */
1352 rlwinm r26,r26,0,1,31 /* (TEST/DEBUG) */
1353 stw r26,SACalloc(r23) /* (TEST/DEBUG) */
1355 sync /* (TEST/DEBUG) */
1357 li r3,0 /* (TEST/DEBUG) */
1358 stw r3,0x20(br0) /* (TEST/DEBUG) */
1359 stw r3,0(r8) /* (TEST/DEBUG) */
1360 lis r0,hi16(Choke) ; (TEST/DEBUG)
1361 ori r0,r0,lo16(Choke) ; (TEST/DEBUG)
1365 lwz r28,SVcount(r8) /* (TEST/DEBUG) */
1366 lwz r21,SVinuse(r8) /* (TEST/DEBUG) */
1367 lwz r23,SVmin(r8) /* (TEST/DEBUG) */
1368 sub r22,r28,r21 /* (TEST/DEBUG) */
1369 cmpw r22,r23 /* (TEST/DEBUG) */
1370 bge+ cksave0 /* (TEST/DEBUG) */
1372 bl currbad ; (TEST/DEBUG)
1374 cksave0: lwz r28,SVfree(r8) /* (TEST/DEBUG) */
1375 li r24,0 /* (TEST/DEBUG) */
1376 li r29,1 /* (TEST/SAVE) */
1378 cksave0a: mr. r28,r28 /* (TEST/DEBUG) */
1379 beq- cksave3 /* (TEST/DEBUG) */
1381 rlwinm. r21,r28,0,4,19 /* (TEST/DEBUG) */
1382 bne+ cksave1 /* (TEST/DEBUG) */
1384 bl currbad ; (TEST/DEBUG)
1386 cksave1: rlwinm. r21,r28,0,21,3 /* (TEST/DEBUG) */
1387 beq+ cksave2 /* (TEST/DEBUG) */
1389 bl currbad ; (TEST/DEBUG)
1391 cksave2: lwz r25,SACalloc(r28) /* (TEST/DEBUG) */
1392 lbz r26,SACflags+2(r28) /* (TEST/DEBUG) */
1393 lbz r21,SACflags+3(r28) /* (TEST/DEBUG) */
1394 cmplwi r26,0x00EE /* (TEST/DEBUG) */
1395 stb r29,SACflags+3(r28) /* (TEST/DEBUG) */
1398 bl currbad ; (TEST/DEBUG)
1400 cksave2z: mr. r21,r21 /* (TEST/DEBUG) */
1401 beq+ cksave2a /* (TEST/DEBUG) */
1403 bl currbad ; (TEST/DEBUG)
1405 cksave2a: rlwinm r26,r25,1,31,31 /* (TEST/DEBUG) */
1406 rlwinm r27,r25,2,31,31 /* (TEST/DEBUG) */
1407 add r24,r24,r26 /* (TEST/DEBUG) */
1408 add r24,r24,r27 /* (TEST/DEBUG) */
1409 lwz r28,SACnext(r28) /* (TEST/DEBUG) */
1410 b cksave0a /* (TEST/DEBUG) */
1412 cksave3: cmplw r24,r22 /* (TEST/DEBUG) */
1413 beq+ cksave4 /* (TEST/DEBUG) */
1415 bl currbad ; (TEST/DEBUG)
1417 cksave4: lwz r28,SVfree(r8) /* (TEST/DEBUG) */
1418 li r24,0 /* (TEST/DEBUG) */
1420 cksave5: mr. r28,r28 /* (TEST/DEBUG) */
1421 beq- cksave6 /* (TEST/DEBUG) */
1422 stb r24,SACflags+3(r28) /* (TEST/DEBUG) */
1423 lwz r28,SACnext(r28) /* (TEST/DEBUG) */
1424 b cksave5 /* (TEST/DEBUG) */
1428 li r4,0 /* (TEST/DEBUG) */
1429 stw r4,0xE80(br0) /* (TEST/DEBUG) */
1430 stw r4,0(r8) /* (TEST/DEBUG) */
1433 li r4,0 /* (TEST/DEBUG) */
1434 stw r4,0x20(br0) /* (TEST/DEBUG) */
1435 mtdec r12 /* (TEST/DEBUG) */
1438 lis r4,HIGH_ADDR(EXT(MPspec)) /* Get the MP control block */
1439 dcbt 0,r2 /* We'll need the per_proc in a sec */
1440 cmplwi cr0,r11,T_INTERRUPT /* Do we have an external interrupt? */
1441 ori r4,r4,LOW_ADDR(EXT(MPspec)) /* Get the bottom half of the MP control block */
1442 bne+ notracex /* Not an external... */
1445 * Here we check to see if there was a interprocessor signal
1448 lwz r4,MPSSIGPhandler(r4) /* Get the address of the SIGP interrupt filter */
1449 lhz r3,PP_CPU_FLAGS(r2) /* Get the CPU flags */
1450 cmplwi cr1,r4,0 /* Check if signal filter is initialized yet */
1451 andi. r3,r3,LOW_ADDR(SIGPactive) /* See if this processor has started up */
1452 mtlr r4 /* Load up filter address */
1453 beq- cr1,notracex /* We don't have a filter yet... */
1454 beq- notracex /* This processor hasn't started filtering yet... */
1456 blrl /* Filter the interrupt */
1458 mfsprg r2,0 /* Make sure we have the per processor block */
1459 cmplwi cr0,r3,kMPIOInterruptPending /* See what the filter says */
1460 li r11,T_INTERRUPT /* Assume we have a regular external 'rupt */
1461 beq+ modRupt /* Yeah, we figured it would be... */
1462 li r11,T_SIGP /* Assume we had a signal processor interrupt */
1463 bgt+ modRupt /* Yeah, at this point we would assume so... */
1464 li r11,T_IN_VAIN /* Nothing there actually, so eat it */
1466 modRupt: stw r11,PP_SAVE_EXCEPTION_TYPE(r2) /* Set that it was either in vain or a SIGP */
1467 stw r11,saveexception(r13) /* Save the exception code here also */
1468 bne- cr5,notracex /* Jump if no tracing... */
1469 sth r11,LTR_excpt(r20) /* Save the exception type */
1474 bf featSMP,nopir6 /* (TEST/DEBUG) */
1475 mfspr r7,pir /* (TEST/DEBUG) */
1476 b gotpir6 /* (TEST/DEBUG) */
1477 nopir6: li r7,0 /* (TEST/DEBUG) */
1478 gotpir6: /* (TEST/DEBUG) */
1479 lis r6,HIGH_ADDR(EXT(RuptCtrs)) /* (TEST/DEBUG) */
1480 rlwinm r7,r7,8,23,23 /* (TEST/DEBUG) */
1481 lis r12,HIGH_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1482 rlwimi r7,r7,1,22,22 /* (TEST/DEBUG) */
1483 ori r6,r6,LOW_ADDR(EXT(RuptCtrs)) /* (TEST/DEBUG) */
1484 rlwinm r1,r11,2,0,29 /* (TEST/DEBUG) */
1485 add r6,r6,r7 /* (TEST/DEBUG) */
1486 ori r12,r12,LOW_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1487 lwz r21,(47*16)+8(r6) /* (TEST/DEBUG) */
1488 lwz r22,(47*16)+12(r6) /* (TEST/DEBUG) */
1489 add r1,r1,r6 /* (TEST/DEBUG) */
1490 mftb r24 /* (TEST/DEBUG) */
1491 sub r22,r24,r22 /* (TEST/DEBUG) */
1492 lwz r4,4(r6) /* (TEST/DEBUG) */
1493 cmplw cr2,r22,r21 /* (TEST/DEBUG) */
1494 lwz r7,4(r1) /* (TEST/DEBUG) */
1495 lwz r21,8(r6) /* (TEST/DEBUG) */
1496 blt+ cr2,nottime /* (TEST/DEBUG) */
1497 stw r24,(47*16)+12(r6) /* (TEST/DEBUG) */
1499 nottime: addi r4,r4,1 /* (TEST/DEBUG) */
1500 lwz r22,8(r1) /* (TEST/DEBUG) */
1501 addi r7,r7,1 /* (TEST/DEBUG) */
1502 stw r4,4(r6) /* (TEST/DEBUG) */
1503 lwz r3,0(r6) /* (TEST/DEBUG) */
1504 mr. r21,r21 /* (TEST/DEBUG) */
1505 stw r7,4(r1) /* (TEST/DEBUG) */
1506 mtlr r12 /* (TEST/DEBUG) */
1507 lwz r1,0(r1) /* (TEST/DEBUG) */
1508 beq- nottimed1 /* (TEST/DEBUG) */
1509 blt+ cr2,isnttime1 /* (TEST/DEBUG) */
1511 nottimed1: mr. r3,r3 /* (TEST/DEBUG) */
1512 bgelrl+ /* (TEST/DEBUG) */
1514 isnttime1: mr. r22,r22 /* (TEST/DEBUG) */
1515 beq- nottimed2 /* (TEST/DEBUG) */
1516 blt+ cr2,isnttime2 /* (TEST/DEBUG) */
1518 nottimed2: mr. r3,r1 /* (TEST/DEBUG) */
1519 mtlr r12 /* (TEST/DEBUG) */
1520 mr r4,r7 /* (TEST/DEBUG) */
1521 bgelrl+ /* (TEST/DEBUG) */
1522 mr r3,r11 /* (TEST/DEBUG) */
1524 isnttime2: cmplwi r11,T_DATA_ACCESS /* (TEST/DEBUG) */
1525 lis r12,HIGH_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1526 bne+ nodsidisp /* (TEST/DEBUG) */
1527 mr. r22,r22 /* (TEST/DEBUG) */
1528 beq- nottimed3 /* (TEST/DEBUG) */
1529 blt+ cr2,nodsidisp /* (TEST/DEBUG) */
1531 nottimed3: li r3,5 /* (TEST/DEBUG) */
1532 ori r12,r12,LOW_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1533 lwz r4,savesrr0(r13) /* (TEST/DEBUG) */
1534 mtlr r12 /* (TEST/DEBUG) */
1535 blrl /* (TEST/DEBUG) */
1537 lis r12,HIGH_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1538 ori r12,r12,LOW_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1539 lis r3,9 /* (TEST/DEBUG) */
1540 ori r3,r3,5 /* (TEST/DEBUG) */
1541 mtlr r12 /* (TEST/DEBUG) */
1542 lwz r4,savedar(r13) /* (TEST/DEBUG) */
1543 blrl /* (TEST/DEBUG) */
1545 nodsidisp: cmplwi r11,T_INSTRUCTION_ACCESS /* (TEST/DEBUG) */
1546 lis r12,HIGH_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1547 bne+ noisidisp /* (TEST/DEBUG) */
1548 mr. r22,r22 /* (TEST/DEBUG) */
1549 beq- nottimed4 /* (TEST/DEBUG) */
1550 blt+ cr2,noisidisp /* (TEST/DEBUG) */
1552 nottimed4: li r3,6 /* (TEST/DEBUG) */
1553 ori r12,r12,LOW_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1554 lwz r4,savesrr0(r13) /* (TEST/DEBUG) */
1555 mtlr r12 /* (TEST/DEBUG) */
1556 blrl /* (TEST/DEBUG) */
1558 noisidisp: mr r3,r11 /* (TEST/DEBUG) */
1562 cmplwi r11,T_PROGRAM /* (TEST/DEBUG) */
1563 lis r12,HIGH_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1564 bne+ nopgmdisp /* (TEST/DEBUG) */
1565 li r3,7 /* (TEST/DEBUG) */
1566 ori r12,r12,LOW_ADDR(EXT(GratefulDeb)) /* (TEST/DEBUG) */
1567 lwz r4,savesrr0(r13) /* (TEST/DEBUG) */
1568 mtlr r12 /* (TEST/DEBUG) */
1569 blrl /* (TEST/DEBUG) */
1571 nopgmdisp: mr r3,r11 /* (TEST/DEBUG) */
1574 li r21,0 ; Assume no processor register for now
1575 lis r12,hi16(EXT(hw_counts)) ; Get the high part of the interrupt counters
1576 bf featSMP,nopirhere ; Jump if this processor does not have a PIR...
1577 mfspr r21,pir ; Get the PIR
1579 nopirhere: ori r12,r12,lo16(EXT(hw_counts)) ; Get the low part of the interrupt counters
1580 lwz r7,savesrr1(r13) ; Get the entering MSR
1581 rlwinm r21,r21,8,20,23 ; Get index to processor counts
1582 mtcrf 0x80,r0 /* Set our CR0 to the high nybble of the request code */
1583 rlwinm r6,r0,1,0,31 /* Move sign bit to the end */
1584 cmplwi cr1,r11,T_SYSTEM_CALL /* Did we get a system call? */
1585 crandc cr0_lt,cr0_lt,cr0_gt /* See if we have R0 equal to 0b10xx...x */
1586 add r12,r12,r21 ; Point to the processor count area
1587 cmplwi cr3,r11,T_IN_VAIN /* Was this all in vain? All for nothing? */
1588 lwzx r22,r12,r11 ; Get the old value
1589 cmplwi cr2,r6,1 /* See if original R0 had the CutTrace request code in it */
1590 addi r22,r22,1 ; Count this one
1591 cmplwi cr4,r11,T_SIGP /* Indicate if we had a SIGP 'rupt */
1592 stwx r22,r12,r11 ; Store it back
1594 beq- cr3,EatRupt /* Interrupt was all for nothing... */
1595 cmplwi cr3,r11,T_MACHINE_CHECK ; Did we get a machine check?
1596 bne+ cr1,noCutT /* Not a system call... */
1597 bnl+ cr0,noCutT /* R0 not 0b10xxx...x, can't be any kind of magical system call... */
1598 rlwinm. r7,r7,0,MSR_PR_BIT,MSR_PR_BIT ; Did we come from user state?
1599 lis r1,hi16(EXT(dgWork)) ; Get the diagnostics flags
1600 beq+ FCisok ; From supervisor state...
1602 ori r1,r1,lo16(EXT(dgWork)) ; Again
1603 lwz r1,dgFlags(r1) ; Get the flags
1604 rlwinm. r1,r1,0,enaUsrFCallb,enaUsrFCallb ; Are they valid?
1607 FCisok: beq- cr2,isCutTrace /* This is a CutTrace system call */
1610 * Here's where we call the firmware. If it returns T_IN_VAIN, that means
1611 * that it has handled the interruption. Remember: thou shalt not trash R13
1612 * or R20 while you are away. Anything else is ok.
1615 lis r1,hi16(EXT(FirmwareCall)) /* Top half of firmware call handler */
1616 ori r1,r1,lo16(EXT(FirmwareCall)) /* Bottom half of it */
1617 lwz r3,saver3(r13) /* Restore the first parameter, the rest are ok already */
1618 mtlr r1 /* Get it in the link register */
1619 blrl /* Call the handler */
1621 cmplwi r3,T_IN_VAIN /* Was it handled? */
1622 mfsprg r2,0 /* Restore the per_processor area */
1623 beq+ EatRupt /* Interrupt was handled... */
1624 mr r11,r3 /* Put the 'rupt code in the right register */
1625 b noSIGP /* Go to the normal system call handler */
1628 li r7,-32768 /* Get a 0x8000 for the exception code */
1629 bne- cr5,EatRupt /* Tracing is disabled... */
1630 sth r7,LTR_excpt(r20) /* Modify the exception type to a CutTrace */
1631 b EatRupt /* Time to go home... */
1633 /* We are here 'cause we didn't have a CutTrace system call */
1635 noCutT: beq- cr3,MachineCheck ; Whoa... Machine check...
1636 bne+ cr4,noSIGP /* Skip away if we didn't get a SIGP... */
1638 lis r6,HIGH_ADDR(EXT(MPsignalFW)) /* Top half of SIGP handler */
1639 ori r6,r6,LOW_ADDR(EXT(MPsignalFW)) /* Bottom half of it */
1640 mtlr r6 /* Get it in the link register */
1642 blrl /* Call the handler - we'll only come back if this is an AST, */
1643 /* 'cause FW can't handle that */
1644 mfsprg r2,0 /* Restore the per_processor area */
1646 ; The following interrupts are the only ones that can be redriven
1647 ; by the higher level code or emulation routines.
1650 Redrive: cmplwi cr0,r3,T_IN_VAIN /* Did the signal handler eat the signal? */
1651 mr r11,r3 /* Move it to the right place */
1652 beq+ cr0,EatRupt /* Bail now if the signal handler processed the signal... */
1656 * Here's where we check for the other fast-path exceptions: translation exceptions,
1657 * emulated instructions, etc.
1660 noSIGP: cmplwi cr3,r11,T_ALTIVEC_ASSIST ; Check for an Altivec denorm assist
1661 cmplwi cr1,r11,T_PROGRAM /* See if we got a program exception */
1662 cmplwi cr2,r11,T_INSTRUCTION_ACCESS /* Check on an ISI */
1663 bne+ cr3,noAltivecAssist ; It is not an assist...
1664 b EXT(AltivecAssist) ; It is an assist...
1667 bne+ cr1,noEmulate ; No emulation here...
1668 b EXT(Emulate) ; Go try to emulate...
1670 noEmulate: cmplwi cr3,r11,T_CSWITCH /* Are we context switching */
1671 cmplwi r11,T_DATA_ACCESS /* Check on a DSI */
1672 beq- cr2,DSIorISI /* It's a PTE fault... */
1673 beq- cr3,conswtch /* It's a context switch... */
1674 bne+ PassUp /* It's not a PTE fault... */
1677 * This call will either handle the fault, in which case it will not
1678 * return, or return to pass the fault up the line.
1682 lis r7,HIGH_ADDR(EXT(handlePF)) /* Top half of DSI handler */
1683 ori r7,r7,LOW_ADDR(EXT(handlePF)) /* Bottom half of it */
1684 mtlr r7 /* Get it in the link register */
1685 mr r3,r11 /* Move the 'rupt code */
1687 blrl /* See if we can handle this fault */
1689 lwz r0,savesrr1(r13) ; Get the MSR in use at exception time
1690 mfsprg r2, 0 /* Get back per_proc */
1691 cmplwi cr1,r3,T_IN_VAIN ; Was it handled?
1692 andi. r4,r0,lo16(MASK(MSR_RI)) ; See if the recover bit is on
1693 mr r11,r3 /* Make sure we can find this later */
1694 beq+ cr1,EatRupt ; Yeah, just blast back to the user...
1695 andc r0,r0,r4 ; Remove the recover bit
1696 beq+ PassUp ; Not on, normal case...
1697 lwz r4,savesrr0(r13) ; Get the failing instruction address
1698 lwz r5,savecr(r13) ; Get the condition register
1699 stw r0,savesrr1(r13) ; Save the result MSR
1700 addi r4,r4,4 ; Skip failing instruction
1701 rlwinm r5,r5,0,3,1 ; Clear CR0_EQ to let emulation code know we failed
1702 stw r4,savesrr0(r13) ; Save instruction address
1703 stw r4,savecr(r13) ; And the resume CR
1704 b EatRupt ; Resume emulated code
1707 * Here is where we handle the context switch firmware call. The old
1708 * context has been saved, and the new savearea in in saver3. We'll just
1709 * muck around with the savearea pointers, and then join the exit routine
1711 conswtch: lwz r28,SAVflags(r13) /* The the flags of the current */
1712 mr r29,r13 /* Save the save */
1713 rlwinm r30,r13,0,0,19 /* Get the start of the savearea block */
1714 lwz r5,saver3(r13) /* Switch to the new savearea */
1715 oris r28,r28,HIGH_ADDR(SAVattach) /* Turn on the attached flag */
1716 lwz r30,SACvrswap(r30) /* get real to virtual translation */
1717 mr r13,r5 /* Switch saveareas */
1718 xor r27,r29,r30 /* Flip to virtual */
1719 stw r28,SAVflags(r29) /* Stash it back */
1720 stw r27,saver3(r5) /* Push the new savearea to the switch to routine */
1721 b EatRupt /* Start 'er up... */
1724 ; Handle machine check here.
1729 lwz r27,savesrr1(r13) ; ?
1730 rlwinm. r11,r27,0,dcmck,dcmck ; ?
1733 mfspr r11,msscr0 ; ?
1737 lwz r27,savesrr1(r13) ; ?
1739 hiccup: cmplw r27,r27 ; ?
1743 oris r11,r11,hi16(dl1hwfm) ; ?
1744 mtspr msscr0,r11 ; ?
1746 rstbsy: mfspr r11,msscr0 ; ?
1748 rlwinm. r11,r11,0,dl1hwf,dl1hwf ; ?
1753 li r11,T_IN_VAIN ; ?
1759 ; Check if the failure was in
1760 ; ml_probe_read. If so, this is expected, so modify the PC to
1761 ; ml_proble_read_mck and then eat the exception.
1763 lwz r30,savesrr0(r13) ; Get the failing PC
1764 lis r28,hi16(EXT(ml_probe_read_mck)) ; High order part
1765 lis r27,hi16(EXT(ml_probe_read)) ; High order part
1766 ori r28,r28,lo16(EXT(ml_probe_read_mck)) ; Get the low part
1767 ori r27,r27,lo16(EXT(ml_probe_read)) ; Get the low part
1768 cmplw r30,r28 ; Check highest possible
1769 cmplw cr1,r30,r27 ; Check lowest
1770 bge- PassUp ; Outside of range
1771 blt- cr1,PassUp ; Outside of range
1773 ; We need to fix up the BATs here because the probe
1774 ; routine messed them all up... As long as we are at it,
1775 ; fix up to return directly to caller of probe.
1778 lis r11,hi16(EXT(shadow_BAT)+shdDBAT) ; Get shadow address
1779 ori r11,r11,lo16(EXT(shadow_BAT)+shdDBAT) ; Get shadow address
1781 lwz r30,0(r11) ; Pick up DBAT 0 high
1782 lwz r28,4(r11) ; Pick up DBAT 0 low
1783 lwz r27,8(r11) ; Pick up DBAT 1 high
1784 lwz r18,16(r11) ; Pick up DBAT 2 high
1785 lwz r11,24(r11) ; Pick up DBAT 3 high
1788 mtdbatu 0,r30 ; Restore DBAT 0 high
1789 mtdbatl 0,r28 ; Restore DBAT 0 low
1790 mtdbatu 1,r27 ; Restore DBAT 1 high
1791 mtdbatu 2,r18 ; Restore DBAT 2 high
1792 mtdbatu 3,r11 ; Restore DBAT 3 high
1795 lwz r27,saver6(r13) ; Get the saved R6 value
1796 mtspr hid0,r27 ; Restore HID0
1799 lwz r28,savelr(r13) ; Get return point
1800 lwz r27,saver0(r13) ; Get the saved MSR
1801 li r30,0 ; Get a failure RC
1802 stw r28,savesrr0(r13) ; Set the return point
1803 stw r27,savesrr1(r13) ; Set the continued MSR
1804 stw r30,saver3(r13) ; Set return code
1805 li r11,T_IN_VAIN ; Set new interrupt code
1806 b EatRupt ; Yum, yum, eat it all up...
1809 * Here's where we come back from some instruction emulator. If we come back with
1810 * T_IN_VAIN, the emulation is done and we should just reload state and directly
1811 * go back to the interrupted code. Otherwise, we'll check to see if
1812 * we need to redrive with a different interrupt, i.e., DSI.
1816 .globl EXT(EmulExit)
1820 cmplwi r11,T_IN_VAIN /* Was it emulated? */
1821 lis r1,hi16(SAVredrive) ; Get redrive request
1822 mfsprg r2,0 ; Restore the per_proc area
1823 beq+ EatRupt /* Yeah, just blast back to the user... */
1824 lwz r4,SAVflags(r13) ; Pick up the flags
1826 and. r0,r4,r1 ; Check if redrive requested
1827 andc r4,r4,r1 ; Clear redrive
1829 beq+ PassUp ; No redrive, just keep on going...
1831 lwz r3,saveexception(r13) ; Restore exception code
1832 stw r4,SAVflags(r13) ; Set the flags
1833 b Redrive ; Redrive the exception...
1835 /* Jump into main handler code switching on VM at the same time */
1837 /* We assume kernel data is mapped contiguously in physical
1838 * memory, otherwise we'd need to switch on (at least) virtual data.
1839 * SRs are already set up.
1841 PassUp: lis r2,hi16(EXT(exception_handlers)) ; Get exception vector address
1842 ori r2,r2,lo16(EXT(exception_handlers)) ; And low half
1843 lwzx r6,r2,r11 /* Get the actual exception handler address */
1845 PassUpDeb: lwz r8,SAVflags(r13) /* Get the flags */
1846 mtsrr0 r6 /* Set up the handler address */
1847 oris r8,r8,HIGH_ADDR(SAVattach) /* Since we're passing it up, attach it */
1848 rlwinm r5,r13,0,0,19 /* Back off to the start of savearea block */
1850 mfmsr r3 /* Get our MSR */
1851 stw r8,SAVflags(r13) /* Pass up the flags */
1852 rlwinm r3,r3,0,MSR_BE_BIT+1,MSR_SE_BIT-1 /* Clear all but the trace bits */
1853 li r2,MSR_SUPERVISOR_INT_OFF /* Get our normal MSR value */
1854 lwz r5,SACvrswap(r5) /* Get real to virtual conversion */
1855 or r2,r2,r3 /* Keep the trace bits if they're on */
1856 mr r3,r11 /* Pass the exception code in the paramter reg */
1857 mtsrr1 r2 /* Set up our normal MSR value */
1858 xor r4,r13,r5 /* Pass up the virtual address of context savearea */
1860 rfi /* Launch the exception handler */
1862 .long 0 /* Leave these here gol durn it! */
1872 * This routine is the only place where we return from an interruption.
1873 * Anyplace else is wrong. Even if I write the code, it's still wrong.
1874 * Feel free to come by and slap me if I do do it--even though I may
1875 * have had a good reason to do it.
1877 * All we need to remember here is that R13 must point to the savearea
1878 * that has the context we need to load up. Translation and interruptions
1881 * This code always loads the context in the savearea pointed to
1882 * by R13. In the process, it throws away the savearea. If there
1883 * is any tomfoolery with savearea stacks, it must be taken care of
1884 * before we get here.
1886 * Speaking of tomfoolery, this is where we synthesize interruptions
1887 * if any need to be.
1892 EatRupt: mr r31,r13 /* Move the savearea pointer to the far end of the register set */
1894 EatRupt2: mfsprg r2,0 /* Get the per_proc block */
1895 dcbt 0,r31 ; Get this because we need it very soon
1898 lwz r30,saver0(r31) ; (TEST/DEBUG) Get users R0
1899 lwz r20,saveexception(r31) ; (TEST/DEBUG) Returning from trace?
1900 xor r30,r20,r30 ; (TEST/DEBUG) Make code
1901 rlwinm r30,r30,1,0,31 ; (TEST/DEBUG) Make an easy test
1902 cmplwi cr5,r30,0x61 ; (TEST/DEBUG) See if this is a trace
1906 * First we see if we are able to free the new savearea.
1907 * If it is not attached to anything, put it on the free list.
1908 * This is real dangerous, we haven't restored context yet...
1909 * So, the free savearea chain lock must stay until the bitter end!
1913 * It's dangerous here. We haven't restored anything from the current savearea yet.
1914 * And, we mark it the active one. So, if we get an exception in here, it is
1915 * unrecoverable. Unless we mess up, we can't get any kind of exception. So,
1916 * it is important to assay this code as only the purest of gold.
1918 * But first, see if there is a savearea hanging off of quickfret. If so,
1919 * we release that one first and then come back for the other. We should rarely
1920 * see one, they appear when FPU or VMX context is discarded by either returning
1921 * to a higher exception level, or explicitly.
1923 * A word about QUICKFRET: Multiple saveareas may be queued for release. It is
1924 * the responsibility of the queuer to insure that the savearea is not multiply
1925 * queued and that the appropriate inuse bits are reset.
1930 mfsprg r27,2 ; Get the processor features
1931 lwz r1,savesrr1(r31) ; Get destination MSR
1932 mtcrf 0x60,r27 ; Set CRs with thermal facilities
1933 mr r18,r31 ; Save the savearea pointer
1934 rlwinm. r0,r1,0,MSR_EE_BIT,MSR_EE_BIT ; Are interruptions going to be enabled?
1935 lwz r19,PP_QUICKFRET(r2) ; Get the quick release savearea
1936 crandc 31,pfThermalb,pfThermIntb ; See if we have both thermometer and not interrupt facility
1937 li r0,0 ; Get a zero
1938 crandc 31,31,cr0_eq ; Factor in enablement
1939 la r21,savesr0(r18) ; Point to the first thing we restore
1940 bf 31,tempisok ; No thermal checking needed...
1943 ; We get to here if 1) there is a thermal facility, and 2) the hardware
1944 ; will or cannot interrupt, and 3) the interrupt will be enabled after this point.
1947 mfspr r16,thrm3 ; Get thermal 3
1948 mfspr r14,thrm1 ; Get thermal 2
1949 rlwinm. r16,r16,0,thrme,thrme ; Is the themometer enabled?
1950 mfspr r15,thrm2 ; Get thermal 2
1951 beq- tempisok ; No thermometer...
1952 rlwinm r16,r14,2,28,31 ; Cluster THRM1s TIE, V, TIN, and TIV at bottom 4 bits
1953 srawi r0,r15,31 ; Make a mask of 1s if temprature over
1954 rlwinm r30,r15,2,28,31 ; Cluster THRM2s TIE, V, TIN, and TIV at bottom 4 bits
1956 ; Note that the following compare check that V, TIN, and TIV are set and that TIE is cleared.
1957 ; This insures that we only emulate when the hardware is not set to interrupt.
1959 cmplwi cr0,r16,7 ; Is there a valid pending interruption for THRM1?
1960 cmplwi cr1,r30,7 ; Is there a valid pending interruption for THRM2?
1961 and r15,r15,r0 ; Keep high temp if that interrupted, zero if not
1962 cror cr0_eq,cr0_eq,cr1_eq ; Merge both
1963 andc r14,r14,r0 ; Keep low if high did not interrupt, zero if it did
1964 bne+ tempisok ; Nope, temprature is in range
1966 li r3,T_THERMAL ; Time to emulate a thermal interruption
1967 or r14,r14,r15 ; Get contents of interrupting register
1968 mr r13,r31 ; Make sure savearea is pointed to correctly
1969 stw r3,saveexception(r31) ; Restore exception code
1970 stw r14,savedar(r31) ; Set the contents of the interrupting register into the dar
1971 b Redrive ; Go process this new interruption...
1974 tempisok: lis r30,HIGH_ADDR(EXT(saveanchor)) /* Get the high part of the anchor */
1975 stw r0,PP_QUICKFRET(r2) /* Clear quickfret pointer */
1976 ori r30,r30,LOW_ADDR(EXT(saveanchor)) /* Bottom half of the anchor */
1977 dcbt 0,r21 /* Touch in the first thing */
1980 li r23,0 ; (TEST/DEBUG)
1981 rlwinm r14,r31,0,0,19 ; (TEST/DEBUG)
1982 lwz r21,SACflags(r14) ; (TEST/DEBUG)
1983 rlwinm r22,r21,24,24,31 ; (TEST/DEBUG)
1984 cmplwi r22,0x00EE ; (TEST/DEBUG)
1985 beq+ nodienodie1 ; (TEST/DEBUG)
1987 dodiedodie: li r1,0x666 ; (TEST/DEBUG)
1988 BREAKPOINT_TRAP ; (TEST/DEBUG)
1991 mr r23,r19 ; (TEST/DEBUG)
1993 chkitagain: mr. r23,r23 ; (TEST/DEBUG)
1994 beq nodienodie2 ; (TEST/DEBUG)
1995 rlwinm r14,r23,0,0,19 ; (TEST/DEBUG)
1996 lwz r21,SACflags(r14) ; (TEST/DEBUG)
1997 rlwinm r22,r21,24,24,31 ; (TEST/DEBUG)
1998 cmplwi r22,0x00EE ; (TEST/DEBUG)
1999 bne- dodiedodie ; (TEST/DEBUG)
2000 lwz r23,SAVqfret(r23) ; (TEST/DEBUG)
2001 b chkitagain ; (TEST/DEBUG)
2007 beq- cr5,trkill0 ; (TEST/DEBUG) Do not trace this type
2008 lwz r14,LOW_ADDR(traceMask-EXT(ExceptionVectorsStart))(br0) ; (TEST/DEBUG) Get the trace mask
2009 mr. r14,r14 ; (TEST/DEBUG) Is it stopped?
2010 beq- trkill0 ; (TEST/DEBUG) yes...
2011 bl cte ; (TEST/DEBUG) Trace this
2012 stw r18,LTR_r1(r20) ; (TEST/DEBUG) Normal savearea
2013 stw r19,LTR_r2(r20) ; (TEST/DEBUG) Quickfret savearea
2017 rtlck: lwarx r22,0,r30 /* Grab the lock value */
2018 li r23,1 /* Use part of the delay time */
2019 mr. r22,r22 /* Is it locked? */
2020 bne- rtlcks /* Yeah, wait for it to clear... */
2021 stwcx. r23,0,r30 /* Try to seize that there durn lock */
2022 beq+ fretagain ; Got it...
2023 b rtlck /* Collision, try again... */
2025 rtlcks: lwz r22,SVlock(r30) /* Get that lock in here */
2026 mr. r22,r22 /* Is it free yet? */
2027 beq+ rtlck /* Yeah, try for it again... */
2028 b rtlcks /* Sniff away... */
2031 ; Lock gotten, toss the saveareas
2033 fretagain: isync ; Toss those prefetches
2035 beq- cr5,trkill1 ; (TEST/DEBUG) Do not trace this type
2036 lwz r14,LOW_ADDR(traceMask-EXT(ExceptionVectorsStart))(br0) ; (TEST/DEBUG) Get the trace mask
2037 mr. r14,r14 ; (TEST/DEBUG) Is it stopped?
2038 beq- trkill1 ; (TEST/DEBUG) yes...
2039 li r0,1 ; (TEST/DEBUG) ID number
2040 bl cte ; (TEST/DEBUG) Trace this
2041 stw r18,LTR_r1(r20) ; (TEST/DEBUG) Normal savearea
2042 stw r19,LTR_r2(r20) ; (TEST/DEBUG) Quickfret savearea
2046 mr. r18,r18 ; Are we actually done here?
2047 beq- donefret ; Yeah...
2048 mr. r31,r19 ; Is there a quickfret to do?
2049 beq+ noqfrt ; Nope...
2050 lwz r19,SAVqfret(r19) ; Yes, get the next in line
2052 beq- cr5,trkill2 ; (TEST/DEBUG) Do not trace this type
2053 lwz r14,LOW_ADDR(traceMask-EXT(ExceptionVectorsStart))(br0) ; (TEST/DEBUG) Get the trace mask
2054 mr. r14,r14 ; (TEST/DEBUG) Is it stopped?
2055 beq- trkill2 ; (TEST/DEBUG) yes...
2056 li r0,2 ; (TEST/DEBUG) ID number
2057 bl cte ; (TEST/DEBUG) Trace this
2058 stw r18,LTR_r1(r20) ; (TEST/DEBUG) Normal savearea
2059 stw r19,LTR_r2(r20) ; (TEST/DEBUG) next quickfret savearea
2060 stw r31,LTR_r3(r20) ; (TEST/DEBUG) Current one to toss
2063 b doqfrt ; Go do it...
2065 noqfrt: mr r31,r18 ; Set the area to release
2066 li r18,0 ; Show we have done it
2068 beq- cr5,trkill3 ; (TEST/DEBUG) Do not trace this type
2069 lwz r14,LOW_ADDR(traceMask-EXT(ExceptionVectorsStart))(br0) ; (TEST/DEBUG) Get the trace mask
2070 mr. r14,r14 ; (TEST/DEBUG) Is it stopped?
2071 beq- trkill3 ; (TEST/DEBUG) yes...
2072 li r0,3 ; (TEST/DEBUG) ID number
2073 bl cte ; (TEST/DEBUG) Trace this
2074 stw r18,LTR_r1(r20) ; (TEST/DEBUG) Normal savearea
2075 stw r19,LTR_r2(r20) ; (TEST/DEBUG) next quickfret savearea
2076 stw r31,LTR_r3(r20) ; (TEST/DEBUG) Current one to toss
2080 doqfrt: li r0,0 ; Get a constant 0
2081 lis r26,0x8000 /* Build a bit mask and assume first savearea */
2082 stw r0,SAVqfret(r31) ; Make sure back chain is unlinked
2083 lwz r28,SAVflags(r31) ; Get the flags for the old active one
2085 beq- cr5,trkill4 ; (TEST/DEBUG) Do not trace this type
2086 lwz r14,LOW_ADDR(traceMask-EXT(ExceptionVectorsStart))(br0) ; (TEST/DEBUG) Get the trace mask
2087 mr. r14,r14 ; (TEST/DEBUG) Is it stopped?
2088 beq- trkill4 ; (TEST/DEBUG) yes...
2089 li r0,4 ; (TEST/DEBUG) ID number
2090 bl cte ; (TEST/DEBUG) Trace this
2091 stw r18,LTR_r1(r20) ; (TEST/DEBUG) Normal savearea
2092 stw r19,LTR_r2(r20) ; (TEST/DEBUG) next quickfret savearea
2093 stw r31,LTR_r3(r20) ; (TEST/DEBUG) Current one to toss
2094 stw r28,LTR_r4(r20) ; (TEST/DEBUG) Save current flags
2097 rlwinm r25,r31,21,31,31 /* Get position of savearea in block */
2098 andis. r28,r28,HIGH_ADDR(SAVinuse) /* See if we need to free it */
2099 srw r26,r26,r25 /* Get bit position to deallocate */
2100 rlwinm r29,r31,0,0,19 /* Round savearea pointer to even page address */
2102 bne- fretagain /* Still in use, we can't free this one... */
2104 lwz r23,SACalloc(r29) /* Get the allocation for this block */
2105 lwz r24,SVinuse(r30) /* Get the in use count */
2106 mr r28,r23 ; (TEST/DEBUG) save for trace
2107 or r23,r23,r26 /* Turn on our bit */
2108 subi r24,r24,1 /* Show that this one is free */
2109 cmplw r23,r26 /* Is our's the only one free? */
2110 stw r23,SACalloc(r29) /* Save it out */
2111 bne+ rstrest /* Nope, then the block is already on the free list */
2113 lwz r22,SVfree(r30) /* Get the old head of the free list */
2114 stw r29,SVfree(r30) /* Point the head at us now */
2115 stw r22,SACnext(r29) ; Point us to the old last
2117 rstrest: stw r24,SVinuse(r30) /* Set the in use count */
2119 beq- cr5,trkill5 ; (TEST/DEBUG) Do not trace this type
2120 lwz r14,LOW_ADDR(traceMask-EXT(ExceptionVectorsStart))(br0) ; (TEST/DEBUG) Get the trace mask
2121 mr. r14,r14 ; (TEST/DEBUG) Is it stopped?
2122 beq- trkill5 ; (TEST/DEBUG) yes...
2123 li r0,5 ; (TEST/DEBUG) ID number
2124 bl cte ; (TEST/DEBUG) Trace this
2125 stw r18,LTR_r1(r20) ; (TEST/DEBUG) Normal savearea
2126 stw r19,LTR_r2(r20) ; (TEST/DEBUG) Next quickfret savearea
2127 stw r31,LTR_r3(r20) ; (TEST/DEBUG) Current one to toss
2128 stw r28,LTR_srr1(r20) ; (TEST/DEBUG) Save the original allocation
2129 stw r23,LTR_dar(r20) ; (TEST/DEBUG) Save the new allocation
2130 stw r24,LTR_save(r20) ; (TEST/DEBUG) Save the new in use count
2131 stw r22,LTR_lr(r20) ; (TEST/DEBUG) Save the old top of free list
2132 stw r29,LTR_ctr(r20) ; (TEST/DEBUG) Save the new top of free list
2135 b fretagain ; Go finish up the rest...
2138 ; Build the SR values depending upon destination. If we are going to the kernel,
2139 ; the SRs are almost all the way set up. SR14 (or the currently used copyin/out register)
2140 ; must be set to whatever it was at the last exception because it varies. All the rest
2141 ; have been set up already.
2143 ; If we are going into user space, we need to check a bit more. SR0, SR1, SR2, and
2144 ; SR14 (current implementation) must be restored always. The others must be set if
2145 ; they are different that what was loaded last time (i.e., tasks have switched).
2146 ; We check the last loaded address space ID and if the same, we skip the loads.
2147 ; This is a performance gain because SR manipulations are slow.
2152 donefret: lwz r26,savesrr1(r31) ; Get destination state flags
2153 lwz r7,PP_USERPMAP(r2) ; Pick up the user pmap we may launch
2154 cmplw cr3,r14,r14 ; Set that we do not need to stop streams
2155 rlwinm. r17,r26,0,MSR_PR_BIT,MSR_PR_BIT ; See if we are going to user or system
2156 li r14,PMAP_SEGS ; Point to segments
2157 bne+ gotouser ; We are going into user state...
2159 lwz r14,savesr14(r31) ; Get the copyin/out register at interrupt time
2160 mtsr sr14,r14 ; Set SR14
2161 b segsdone ; We are all set up now...
2165 gotouser: dcbt r14,r7 ; Touch the segment register contents
2166 lwz r9,spcFlags(r2) ; Pick up the special flags
2167 lwz r16,PP_LASTPMAP(r2) ; Pick up the last loaded pmap
2168 addi r14,r14,32 ; Second half of pmap segments
2169 rlwinm r9,r9,userProtKeybit-2,2,2 ; Isolate the user state protection key
2170 lwz r15,PMAP_SPACE(r7) ; Get the primary space
2171 lwz r13,PMAP_VFLAGS(r7) ; Get the flags
2172 dcbt r14,r7 ; Touch second page
2173 oris r15,r15,hi16(SEG_REG_PROT) ; Set segment 0 SR value
2174 mtcrf 0x0F,r13 ; Set CRs to correspond to the subordinate spaces
2175 xor r15,r15,r9 ; Flip to proper segment register key
2176 lhz r9,PP_CPU_FLAGS(r2) ; Get the processor flags
2178 addis r13,r15,0x0000 ; Get SR0 value
2179 bf 16,nlsr0 ; No alternate here...
2180 lwz r13,PMAP_SEGS+(0*4)(r7) ; Get SR0 value
2182 nlsr0: mtsr sr0,r13 ; Load up the SR
2183 rlwinm r9,r9,(((31-MSR_BE_BIT)+(traceBEb+16+1))&31),MSR_BE_BIT,MSR_BE_BIT ; Set BE bit if special trace is on
2185 addis r13,r15,0x0010 ; Get SR1 value
2186 bf 17,nlsr1 ; No alternate here...
2187 lwz r13,PMAP_SEGS+(1*4)(r7) ; Get SR1 value
2189 nlsr1: mtsr sr1,r13 ; Load up the SR
2190 or r26,r26,r9 ; Flip on the BE bit for special trace if needed
2192 cmplw r7,r16 ; Are we running the same segs as last time?
2194 addis r13,r15,0x0020 ; Get SR2 value
2195 bf 18,nlsr2 ; No alternate here...
2196 lwz r13,PMAP_SEGS+(2*4)(r7) ; Get SR2 value
2198 nlsr2: mtsr sr2,r13 ; Load up the SR
2200 addis r13,r15,0x0030 ; Get SR3 value
2201 bf 19,nlsr3 ; No alternate here...
2202 lwz r13,PMAP_SEGS+(3*4)(r7) ; Get SR3 value
2204 nlsr3: mtsr sr3,r13 ; Load up the SR
2206 addis r13,r15,0x00E0 ; Get SR14 value
2207 bf 30,nlsr14 ; No alternate here...
2208 lwz r13,PMAP_SEGS+(14*4)(r7) ; Get SR14 value
2210 nlsr14: mtsr sr14,r13 ; Load up the SR
2212 beq+ segsdone ; All done if same pmap as last time...
2214 stw r7,PP_LASTPMAP(r2) ; Remember what we just loaded
2216 addis r13,r15,0x0040 ; Get SR4 value
2217 bf 20,nlsr4 ; No alternate here...
2218 lwz r13,PMAP_SEGS+(4*4)(r7) ; Get SR4 value
2220 nlsr4: mtsr sr4,r13 ; Load up the SR
2222 addis r13,r15,0x0050 ; Get SR5 value
2223 bf 21,nlsr5 ; No alternate here...
2224 lwz r13,PMAP_SEGS+(5*4)(r7) ; Get SR5 value
2226 nlsr5: mtsr sr5,r13 ; Load up the SR
2228 addis r13,r15,0x0060 ; Get SR6 value
2229 bf 22,nlsr6 ; No alternate here...
2230 lwz r13,PMAP_SEGS+(6*4)(r7) ; Get SR6 value
2232 nlsr6: mtsr sr6,r13 ; Load up the SR
2234 addis r13,r15,0x0070 ; Get SR7 value
2235 bf 23,nlsr7 ; No alternate here...
2236 lwz r13,PMAP_SEGS+(7*4)(r7) ; Get SR7 value
2238 nlsr7: mtsr sr7,r13 ; Load up the SR
2240 addis r13,r15,0x0080 ; Get SR8 value
2241 bf 24,nlsr8 ; No alternate here...
2242 lwz r13,PMAP_SEGS+(8*4)(r7) ; Get SR8 value
2244 nlsr8: mtsr sr8,r13 ; Load up the SR
2246 addis r13,r15,0x0090 ; Get SR9 value
2247 bf 25,nlsr9 ; No alternate here...
2248 lwz r13,PMAP_SEGS+(9*4)(r7) ; Get SR9 value
2250 nlsr9: mtsr sr9,r13 ; Load up the SR
2252 addis r13,r15,0x00A0 ; Get SR10 value
2253 bf 26,nlsr10 ; No alternate here...
2254 lwz r13,PMAP_SEGS+(10*4)(r7) ; Get SR10 value
2256 nlsr10: mtsr sr10,r13 ; Load up the SR
2258 addis r13,r15,0x00B0 ; Get SR11 value
2259 bf 27,nlsr11 ; No alternate here...
2260 lwz r13,PMAP_SEGS+(11*4)(r7) ; Get SR11 value
2262 nlsr11: mtsr sr11,r13 ; Load up the SR
2264 addis r13,r15,0x00C0 ; Get SR12 value
2265 bf 28,nlsr12 ; No alternate here...
2266 lwz r13,PMAP_SEGS+(12*4)(r7) ; Get SR12 value
2268 nlsr12: mtsr sr12,r13 ; Load up the SR
2270 addis r13,r15,0x00D0 ; Get SR13 value
2271 bf 29,nlsr13 ; No alternate here...
2272 lwz r13,PMAP_SEGS+(13*4)(r7) ; Get SR13 value
2274 nlsr13: mtsr sr13,r13 ; Load up the SR
2276 addis r13,r15,0x00F0 ; Get SR15 value
2277 bf 31,nlsr15 ; No alternate here...
2278 lwz r13,PMAP_SEGS+(15*4)(r7) ; Get SR15 value
2280 nlsr15: mtsr sr15,r13 ; Load up the SR
2282 segsdone: li r1,emfp0 ; Point to the fp savearea
2283 lwz r25,savesrr0(r31) ; Get the SRR0 to use
2284 la r28,saver6(r31) /* Point to the next line to use */
2285 dcbt r1,r2 ; Start moving in a work area
2286 lwz r0,saver0(r31) /* Restore */
2287 dcbt 0,r28 /* Touch it in */
2288 mr r29,r2 ; Save the per_proc
2289 lwz r1,saver1(r31) /* Restore */
2290 lwz r2,saver2(r31) /* Restore */
2291 la r28,saver14(r31) /* Point to the next line to get */
2292 lwz r3,saver3(r31) /* Restore */
2293 mtcrf 0x80,r27 ; Get facility availability flags (do not touch CR1-7)
2294 lwz r4,saver4(r31) /* Restore */
2295 mtsrr0 r25 /* Restore the SRR0 now */
2296 lwz r5,saver5(r31) /* Restore */
2297 mtsrr1 r26 /* Restore the SRR1 now */
2298 lwz r6,saver6(r31) /* Restore */
2300 dcbt 0,r28 /* Touch that next line on in */
2301 la r28,savexfpscrpad(r31) ; Point to the saved fpscr
2303 lwz r7,saver7(r31) /* Restore */
2304 dcbt 0,r28 ; Touch saved fpscr
2305 lwz r8,saver8(r31) /* Restore */
2306 lwz r9,saver9(r31) /* Restore */
2307 lwz r10,saver10(r31) /* Restore */
2308 lwz r11,saver11(r31) /* Restore */
2309 lwz r12,saver12(r31) /* Restore */
2310 lwz r13,saver13(r31) /* Restore */
2311 la r28,saver22(r31) /* Point to the next line to do */
2312 lwz r14,saver14(r31) /* Restore */
2313 lwz r15,saver15(r31) /* Restore */
2316 ; Note that floating point will be enabled from here on until the RFI
2319 bf- pfFloatb,nofphere ; Skip if no floating point...
2320 mfmsr r27 ; Save the MSR
2321 ori r27,r27,lo16(MASK(MSR_FP)) ; Enable floating point
2322 mtmsr r27 ; Really enable
2324 stfd f0,emfp0(r29) ; Save FP0
2325 lfd f0,savexfpscrpad(r31) ; Get the fpscr
2326 mtfsf 0xFF,f0 ; Restore fpscr
2327 lfd f0,emfp0(r29) ; Restore the used register
2329 nofphere: dcbt 0,r28 /* Touch in another line of context */
2331 lwz r16,saver16(r31) /* Restore */
2332 lwz r17,saver17(r31) /* Restore */
2333 lwz r18,saver18(r31) /* Restore */
2334 lwz r19,saver19(r31) /* Restore */
2335 lwz r20,saver20(r31) /* Restore */
2336 lwz r21,saver21(r31) /* Restore */
2337 la r28,saver30(r31) /* Point to the final line */
2338 lwz r22,saver22(r31) /* Restore */
2340 dcbt 0,r28 /* Suck it in */
2342 lwz r23,saver23(r31) /* Restore */
2343 lwz r24,saver24(r31) /* Restore */
2344 lwz r25,saver25(r31) /* Restore */
2345 lwz r26,saver26(r31) /* Restore */
2346 lwz r27,saver27(r31) /* Restore */
2348 lwz r28,savecr(r31) /* Get CR to restore */
2349 bf pfAltivecb,noavec4 ; No vector on this machine
2350 lwz r29,savevrsave(r31) ; Get the vrsave
2351 beq+ cr3,noavec3 ; SRs have not changed, no need to stop the streams...
2352 dssall ; Kill all data streams
2353 ; The streams should be suspended
2354 ; already, and we do a bunch of
2355 ; dependent loads and a sync later
2356 ; so we should be cool.
2358 noavec3: mtspr vrsave,r29 ; Set the vrsave
2360 noavec4: lwz r29,savexer(r31) /* Get XER to restore */
2361 mtcr r28 /* Restore the CR */
2362 lwz r28,savelr(r31) /* Get LR to restore */
2363 mtxer r29 /* Restore the XER */
2364 lwz r29,savectr(r31) /* Get the CTR to restore */
2365 mtlr r28 /* Restore the LR */
2366 lwz r28,saver30(r31) /* Restore */
2367 mtctr r29 /* Restore the CTR */
2368 lwz r29,saver31(r31) /* Restore */
2369 mtsprg 2,r28 /* Save R30 */
2370 lwz r28,saver28(r31) /* Restore */
2371 mtsprg 3,r29 /* Save R31 */
2372 lwz r29,saver29(r31) /* Restore */
2374 #if PERFTIMES && DEBUG
2375 stmw r1,0x280(br0) ; Save all registers
2376 mfcr r20 ; Save the CR
2377 mflr r21 ; Save the LR
2378 mfsrr0 r9 ; Save SRR0
2379 mfsrr1 r11 ; Save SRR1
2381 li r3,69 ; Indicate interrupt
2382 mr r4,r11 ; Set MSR to log
2383 mr r5,r31 ; Get savearea to log
2384 bl EXT(dbgLog2) ; Cut log entry
2385 mr r0,r8 ; Restore R0
2386 mtsrr0 r9 ; Restore SRR0
2387 mtsrr1 r11 ; Restore SRR1
2388 mtlr r21 ; Restore the LR
2389 mtcr r20 ; Restore the CR
2390 lmw r1,0x280(br0) ; Restore all the rest
2393 li r31,0 /* Get set to clear lock */
2394 sync /* Make sure it's all out there */
2395 stw r31,SVlock(r30) /* Unlock it */
2396 mfsprg r30,2 /* Restore R30 */
2397 mfsprg r31,0 ; Get per_proc
2398 lwz r31,pfAvailable(r31) ; Get the feature flags
2399 mtsprg 2,r31 ; Set the feature flags
2400 mfsprg r31,3 /* Restore R31 */
2402 rfi /* Click heels three times and think very hard that there's no place like home */
2404 .long 0 /* For old 601 bug */
2417 * exception_exit(savearea *)
2420 * ENTRY : IR and/or DR and/or interruptions can be on
2421 * R3 points to the physical address of a savearea
2425 .globl EXT(exception_exit)
2427 LEXT(exception_exit)
2429 mfsprg r29,2 ; Get feature flags
2430 mfmsr r30 /* Get the current MSR */
2431 mtcrf 0x04,r29 ; Set the features
2432 mr r31,r3 /* Get the savearea in the right register */
2433 andi. r30,r30,0x7FCF /* Turn off externals, IR, and DR */
2434 lis r1,hi16(SAVredrive) ; Get redrive request
2436 bt pfNoMSRirb,eeNoMSR ; No MSR...
2438 mtmsr r30 ; Translation and all off
2439 isync ; Toss prefetch
2442 eeNoMSR: li r0,loadMSR ; Get the MSR setter SC
2443 mr r3,r30 ; Get new MSR
2447 mfsprg r2,0 ; Get the per_proc block
2448 lwz r4,SAVflags(r31) ; Pick up the flags
2449 mr r13,r31 ; Put savearea here also
2451 and. r0,r4,r1 ; Check if redrive requested
2452 andc r4,r4,r1 ; Clear redrive
2454 dcbt br0,r2 ; We will need this in just a sec
2456 beq+ EatRupt ; No redrive, just exit...
2458 lwz r3,saveexception(r13) ; Restore exception code
2459 stw r4,SAVflags(r13) ; Set the flags
2460 b Redrive ; Redrive the exception...
2463 ; Make trace entry for lowmem_vectors internal debug
2467 lwz r20,LOW_ADDR(EXT(traceCurr)-EXT(ExceptionVectorsStart))(br0) ; Pick up the current trace entry
2468 lwz r16,LOW_ADDR(EXT(traceEnd)-EXT(ExceptionVectorsStart))(br0) ; Grab up the end of it all
2469 addi r17,r20,LTR_size ; Point to the next trace entry
2470 cmplw r17,r16 ; Do we need to wrap the trace table?
2471 li r15,32 ; Second line of entry
2472 bne+ ctenwrap ; We got a trace entry...
2473 lwz r17,LOW_ADDR(EXT(traceStart)-EXT(ExceptionVectorsStart))(br0) ; Wrap back to the top
2475 ctenwrap: stw r17,LOW_ADDR(EXT(traceCurr)-EXT(ExceptionVectorsStart))(br0) ; Set the next entry for the next guy
2477 bf- featL1ena,skipz8 ; L1 cache is disabled...
2478 dcbz 0,r20 ; Allocate cache for the entry
2479 dcbz r15,r20 ; Zap the second half
2482 ctegetTB: mftbu r16 ; Get the upper timebase
2483 mftb r17 ; Get the lower timebase
2484 mftbu r15 ; Get the upper one again
2485 cmplw r16,r15 ; Did the top tick?
2486 bne- ctegetTB ; Yeah, need to get it again...
2488 li r15,0x111 ; Get the special trace ID code
2489 stw r0,LTR_r0(r20) ; Save R0 (usually used as an ID number
2490 stw r16,LTR_timeHi(r20) ; Set the upper part of TB
2491 mflr r16 ; Get the return point
2492 stw r17,LTR_timeLo(r20) ; Set the lower part of TB
2493 sth r15,LTR_excpt(r20) ; Save the exception type
2494 stw r16,LTR_srr0(r20) ; Save the return point
2499 * Start of the trace table
2502 .align 12 /* Align to 4k boundary */
2504 .globl EXT(traceTableBeg)
2505 EXT(traceTableBeg): /* Start of trace table */
2506 /* .fill 2048,4,0 Make an 8k trace table for now */
2507 .fill 13760,4,0 /* Make an .trace table for now */
2508 /* .fill 240000,4,0 Make an .trace table for now */
2509 .globl EXT(traceTableEnd)
2510 EXT(traceTableEnd): /* End of trace table */
2512 .globl EXT(ExceptionVectorsEnd)
2513 EXT(ExceptionVectorsEnd): /* Used if relocating the exception vectors */
2514 #ifndef HACKALERTHACKALERT
2516 * This .long needs to be here because the linker gets confused and tries to
2517 * include the final label in a section in the next section if there is nothing
2520 .long 0 /* (HACK/HACK/HACK) */
2525 .globl EXT(exception_end)
2527 .long EXT(ExceptionVectorsEnd) -EXT(ExceptionVectorsStart) /* phys fn */
projects / apple / xnu.git / blob