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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_COPYRIGHT@
24 */
25
26 /* Miscellaneous constants and structures used by the exception
27 * handlers
28 */
29
30 #ifndef _PPC_EXCEPTION_H_
31 #define _PPC_EXCEPTION_H_
32
33 #ifndef ASSEMBLER
34
35 #include <cpus.h>
36 #include <mach_kdb.h>
37 #include <mach_kdp.h>
38
39 #include <mach/machine/vm_types.h>
40 #include <mach/boolean.h>
41 #include <pexpert/pexpert.h>
42 #include <IOKit/IOInterrupts.h>
43 #include <ppc/machine_routines.h>
44
45 /* Per processor CPU features */
46 struct procFeatures {
47 unsigned int Available;
48 #define pfFloat 0x80000000
49 #define pfFloatb 0
50 #define pfAltivec 0x40000000
51 #define pfAltivecb 1
52 #define pfAvJava 0x20000000
53 #define pfAvJavab 2
54 #define pfSMPcap 0x10000000
55 #define pfSMPcapb 3
56 #define pfCanSleep 0x08000000
57 #define pfCanSleepb 4
58 #define pfCanNap 0x04000000
59 #define pfCanNapb 5
60 #define pfCanDoze 0x02000000
61 #define pfCanDozeb 6
62 #define pfThermal 0x01000000
63 #define pfThermalb 7
64 #define pfThermInt 0x00800000
65 #define pfThermIntb 8
66 #define pfSlowNap 0x00004000
67 #define pfSlowNapb 17
68 #define pfNoMuMMCK 0x00002000
69 #define pfNoMuMMCKb 18
70 #define pfLClck 0x00001000
71 #define pfLClckb 19
72 #define pfWillNap 0x00000800
73 #define pfWillNapb 20
74 #define pfNoMSRir 0x00000400
75 #define pfNoMSRirb 21
76 #define pfL3pdet 0x00000200
77 #define pfL3pdetb 22
78 #define pfL1i 0x00000100
79 #define pfL1ib 23
80 #define pfL1d 0x00000080
81 #define pfL1db 24
82 #define pfL1fa 0x00000040
83 #define pfL1fab 25
84 #define pfL2 0x00000020
85 #define pfL2b 26
86 #define pfL2fa 0x00000010
87 #define pfL2fab 27
88 #define pfL2i 0x00000008
89 #define pfL2ib 28
90 #define pfL3 0x00000004
91 #define pfL3b 29
92 #define pfL3fa 0x00000002
93 #define pfL3fab 30
94 #define pfValid 0x00000001
95 #define pfValidb 31
96 unsigned short rptdProc;
97 unsigned short lineSize;
98 unsigned int l1iSize;
99 unsigned int l1dSize;
100 unsigned int l2cr;
101 unsigned int l2Size;
102 unsigned int l3cr;
103 unsigned int l3Size;
104 unsigned int pfHID0;
105 unsigned int pfHID1;
106 unsigned int pfHID2;
107 unsigned int pfHID3;
108 unsigned int pfMSSCR0;
109 unsigned int pfMSSCR1;
110 unsigned int pfICTRL;
111 unsigned int pfLDSTCR;
112 unsigned int pfLDSTDB;
113 unsigned int l2crOriginal;
114 unsigned int l3crOriginal;
115 unsigned int pfBootConfig;
116 unsigned int reserved[4];
117 };
118
119 typedef struct procFeatures procFeatures;
120
121 struct thrmControl {
122 unsigned int maxTemp; /* Maximum temprature before damage */
123 unsigned int throttleTemp; /* Temprature at which to throttle down */
124 unsigned int lowTemp; /* Interrupt when temprature drops below */
125 unsigned int highTemp; /* Interrupt when temprature exceeds this */
126 unsigned int thrm3val; /* Value for thrm3 register */
127 unsigned int rsvd[3]; /* Pad to cache line */
128 };
129
130 typedef struct thrmControl thrmControl;
131
132 /* When an exception is taken, this info is accessed via sprg0 */
133 /* We should always have this one on a cache line boundary */
134 struct per_proc_info {
135 unsigned short cpu_number;
136 unsigned short cpu_flags; /* Various low-level flags */
137 vm_offset_t istackptr;
138 vm_offset_t intstack_top_ss;
139
140 vm_offset_t debstackptr;
141 vm_offset_t debstack_top_ss;
142
143 unsigned int tempwork1; /* Temp work area - monitor use carefully */
144 unsigned int save_exception_type;
145 unsigned int old_thread;
146
147 /* PPC cache line boundary here - 020 */
148
149 unsigned int active_kloaded; /* pointer to active_kloaded[CPU_NO] */
150 unsigned int cpu_data; /* pointer to cpu_data[CPU_NO] */
151 unsigned int need_ast; /* pointer to need_ast[CPU_NO] */
152 /*
153 * Note: the following two pairs of words need to stay in order and each pair must
154 * be in the same reservation (line) granule
155 */
156 unsigned int FPU_thread; /* Thread owning the FPU on this cpu.*/
157 unsigned int FPU_vmmCtx; /* Owing virtual machine context */
158 unsigned int VMX_thread; /* Thread owning the VMX on this cpu */
159 unsigned int VMX_vmmCtx; /* Owing virtual machine context */
160 unsigned int active_stacks; /* pointer to active_stacks[CPU_NO] */
161
162 /* PPC cache line boundary here - 040 */
163 unsigned int quickfret; /* Pointer to savearea for exception exit to free */
164 unsigned int Lastpmap; /* Last user pmap loaded */
165 unsigned int userspace; /* Last loaded user memory space ID */
166 unsigned int userpmap; /* User pmap - real address */
167 unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
168 unsigned int spcFlags; /* Special thread flags */
169 unsigned int liveFPSCR; /* FPSCR which is for the live context */
170 unsigned int ppbbTaskEnv; /* BlueBox Task Environment */
171
172 /* PPC cache line boundary here - 060 */
173 boolean_t interrupts_enabled;
174 unsigned int rsrvd064;
175 IOInterruptHandler interrupt_handler;
176 void * interrupt_nub;
177 unsigned int interrupt_source;
178 void * interrupt_target;
179 void * interrupt_refCon;
180 unsigned int savedSave; /* Savearea saved across sleep - must be 0 at boot */
181
182 /* PPC cache line boundary here - 080 */
183 unsigned int MPsigpStat; /* Signal Processor status (interlocked update for this one) */
184 #define MPsigpMsgp 0xC0000000 /* Message pending (busy + pass) */
185 #define MPsigpBusy 0x80000000 /* Processor area busy, i.e., locked */
186 #define MPsigpPass 0x40000000 /* Busy lock passed to receiving processor */
187 #define MPsigpSrc 0x000000FF /* Processor that owns busy, i.e., the ID of */
188 /* whomever set busy. When a busy is passed, */
189 /* this is the requestor of the function. */
190 #define MPsigpFunc 0x0000FF00 /* Current function */
191 #define MPsigpIdle 0x00 /* No function pending */
192 #define MPsigpSigp 0x04 /* Signal a processor */
193 #define SIGPast 0 /* Requests an ast on target processor */
194 #define SIGPcpureq 1 /* Requests CPU specific function */
195 #define SIGPdebug 2 /* Requests a debugger entry */
196 #define SIGPwake 3 /* Wake up a sleeping processor */
197 #define CPRQtemp 0 /* Get temprature of processor */
198 #define CPRQtimebase 1 /* Get timebase of processor */
199 unsigned int MPsigpParm0; /* SIGP parm 0 */
200 unsigned int MPsigpParm1; /* SIGP parm 1 */
201 unsigned int MPsigpParm2; /* SIGP parm 2 */
202 cpu_id_t cpu_id;
203 vm_offset_t start_paddr;
204 unsigned int ruptStamp[2]; /* Timebase at last interruption */
205
206 /* PPC cache line boundary here - 0A0 */
207 procFeatures pf; /* Processor features */
208
209 /* PPC cache line boundary here - 100 */
210 thrmControl thrm; /* Thermal controls */
211
212 /* PPC cache line boundary here - 120 */
213 unsigned int napStamp[2]; /* Time base when we napped */
214 unsigned int napTotal[2]; /* Total nap time in ticks */
215 unsigned int numSIGPast; /* Number of SIGP asts recieved */
216 unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
217 unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
218 unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
219
220 /* PPC cache line boundary here - 140 */
221 unsigned int spcTRc; /* Special trace count */
222 unsigned int spcTRp; /* Special trace buffer pointer */
223 unsigned int Uassist; /* User Assist Word */
224 unsigned int rsrvd14C[5]; /* Reserved slots */
225
226 /* PPC cache line boundary here - 160 */
227 time_base_enable_t time_base_enable;
228 unsigned int rsrvd164[7]; /* Reserved slots */
229
230 /* PPC cache line boundary here - 180 */
231 unsigned int rsrvd180[8]; /* Reserved slots */
232
233 /* PPC cache line boundary here - 1A0 */
234 unsigned int rsrvd1A0[8]; /* Reserved slots */
235
236 /* PPC cache line boundary here - 1C0 */
237 unsigned int rsrvd1C0[8]; /* Reserved slots */
238
239 /* PPC cache line boundary here - 1E0 */
240 double emfp0; /* Copies of floating point registers */
241 double emfp1; /* Used for emulation purposes */
242 double emfp2;
243 double emfp3;
244
245 double emfp4;
246 double emfp5;
247 double emfp6;
248 double emfp7;
249
250 double emfp8;
251 double emfp9;
252 double emfp10;
253 double emfp11;
254
255 double emfp12;
256 double emfp13;
257 double emfp14;
258 double emfp15;
259
260 double emfp16;
261 double emfp17;
262 double emfp18;
263 double emfp19;
264
265 double emfp20;
266 double emfp21;
267 double emfp22;
268 double emfp23;
269
270 double emfp24;
271 double emfp25;
272 double emfp26;
273 double emfp27;
274
275 double emfp28;
276 double emfp29;
277 double emfp30;
278 double emfp31;
279
280 /* - 2E0 */
281 unsigned int emfpscr_pad;
282 unsigned int emfpscr;
283 unsigned int empadfp[6];
284
285 /* - 300 */
286 unsigned int emvr0[4]; /* Copies of vector registers used both */
287 unsigned int emvr1[4]; /* for full vector emulation or */
288 unsigned int emvr2[4]; /* as saveareas while assisting denorms */
289 unsigned int emvr3[4];
290 unsigned int emvr4[4];
291 unsigned int emvr5[4];
292 unsigned int emvr6[4];
293 unsigned int emvr7[4];
294 unsigned int emvr8[4];
295 unsigned int emvr9[4];
296 unsigned int emvr10[4];
297 unsigned int emvr11[4];
298 unsigned int emvr12[4];
299 unsigned int emvr13[4];
300 unsigned int emvr14[4];
301 unsigned int emvr15[4];
302 unsigned int emvr16[4];
303 unsigned int emvr17[4];
304 unsigned int emvr18[4];
305 unsigned int emvr19[4];
306 unsigned int emvr20[4];
307 unsigned int emvr21[4];
308 unsigned int emvr22[4];
309 unsigned int emvr23[4];
310 unsigned int emvr24[4];
311 unsigned int emvr25[4];
312 unsigned int emvr26[4];
313 unsigned int emvr27[4];
314 unsigned int emvr28[4];
315 unsigned int emvr29[4];
316 unsigned int emvr30[4];
317 unsigned int emvr31[4];
318 unsigned int emvscr[4];
319 unsigned int empadvr[4];
320 /* - 520 */
321
322 unsigned int patcharea[56];
323 /* - 600 */
324
325 };
326
327
328 extern struct per_proc_info per_proc_info[NCPUS];
329
330 typedef struct savearea {
331
332 /* The following area corresponds to ppc_saved_state and ppc_thread_state */
333
334 /* offset 0x0000 */
335 unsigned int save_srr0;
336 unsigned int save_srr1;
337 unsigned int save_r0;
338 unsigned int save_r1;
339 unsigned int save_r2;
340 unsigned int save_r3;
341 unsigned int save_r4;
342 unsigned int save_r5;
343
344 unsigned int save_r6;
345 unsigned int save_r7;
346 unsigned int save_r8;
347 unsigned int save_r9;
348 unsigned int save_r10;
349 unsigned int save_r11;
350 unsigned int save_r12;
351 unsigned int save_r13;
352
353 unsigned int save_r14;
354 unsigned int save_r15;
355 unsigned int save_r16;
356 unsigned int save_r17;
357 unsigned int save_r18;
358 unsigned int save_r19;
359 unsigned int save_r20;
360 unsigned int save_r21;
361
362 unsigned int save_r22;
363 unsigned int save_r23;
364 unsigned int save_r24;
365 unsigned int save_r25;
366 unsigned int save_r26;
367 unsigned int save_r27;
368 unsigned int save_r28;
369 unsigned int save_r29;
370
371 unsigned int save_r30;
372 unsigned int save_r31;
373 unsigned int save_cr;
374 unsigned int save_xer;
375 unsigned int save_lr;
376 unsigned int save_ctr;
377 unsigned int save_mq;
378 unsigned int save_vrsave;
379
380 unsigned int save_sr_copyin;
381 unsigned int save_space;
382 unsigned int save_xfpscrpad;
383 unsigned int save_xfpscr;
384 unsigned int save_pad2[4];
385
386
387 /* The following corresponds to ppc_exception_state */
388
389 /* offset 0x00C0 */
390 unsigned int save_dar;
391 unsigned int save_dsisr;
392 unsigned int save_exception;
393 unsigned int save_pad3[5];
394
395 /* The following corresponds to ppc_float_state */
396
397 /* offset 0x00E0 */
398 double save_fp0;
399 double save_fp1;
400 double save_fp2;
401 double save_fp3;
402
403 double save_fp4;
404 double save_fp5;
405 double save_fp6;
406 double save_fp7;
407
408 double save_fp8;
409 double save_fp9;
410 double save_fp10;
411 double save_fp11;
412
413 double save_fp12;
414 double save_fp13;
415 double save_fp14;
416 double save_fp15;
417
418 double save_fp16;
419 double save_fp17;
420 double save_fp18;
421 double save_fp19;
422
423 double save_fp20;
424 double save_fp21;
425 double save_fp22;
426 double save_fp23;
427
428 double save_fp24;
429 double save_fp25;
430 double save_fp26;
431 double save_fp27;
432
433 double save_fp28;
434 double save_fp29;
435 double save_fp30;
436 double save_fp31;
437
438 unsigned int save_fpscr_pad;
439 unsigned int save_fpscr;
440 unsigned int save_pad4[6];
441
442 /* The following is the save area for the VMX registers */
443
444 /* offset 0x0200 */
445 unsigned int save_vr0[4];
446 unsigned int save_vr1[4];
447 unsigned int save_vr2[4];
448 unsigned int save_vr3[4];
449 unsigned int save_vr4[4];
450 unsigned int save_vr5[4];
451 unsigned int save_vr6[4];
452 unsigned int save_vr7[4];
453 unsigned int save_vr8[4];
454 unsigned int save_vr9[4];
455 unsigned int save_vr10[4];
456 unsigned int save_vr11[4];
457 unsigned int save_vr12[4];
458 unsigned int save_vr13[4];
459 unsigned int save_vr14[4];
460 unsigned int save_vr15[4];
461 unsigned int save_vr16[4];
462 unsigned int save_vr17[4];
463 unsigned int save_vr18[4];
464 unsigned int save_vr19[4];
465 unsigned int save_vr20[4];
466 unsigned int save_vr21[4];
467 unsigned int save_vr22[4];
468 unsigned int save_vr23[4];
469 unsigned int save_vr24[4];
470 unsigned int save_vr25[4];
471 unsigned int save_vr26[4];
472 unsigned int save_vr27[4];
473 unsigned int save_vr28[4];
474 unsigned int save_vr29[4];
475 unsigned int save_vr30[4];
476 unsigned int save_vr31[4];
477 unsigned int save_vscr[4]; /* Note that this is always valid if VMX has been used */
478 unsigned int save_pad5[4]; /* Insures that vrvalid is on a cache line */
479 unsigned int save_vrvalid; /* VRs that have been saved */
480 unsigned int save_pad6[7];
481
482 /* The following is the save area for the segment registers */
483
484 /* offset 0x0440 */
485
486 unsigned int save_sr0;
487 unsigned int save_sr1;
488 unsigned int save_sr2;
489 unsigned int save_sr3;
490 unsigned int save_sr4;
491 unsigned int save_sr5;
492 unsigned int save_sr6;
493 unsigned int save_sr7;
494
495 unsigned int save_sr8;
496 unsigned int save_sr9;
497 unsigned int save_sr10;
498 unsigned int save_sr11;
499 unsigned int save_sr12;
500 unsigned int save_sr13;
501 unsigned int save_sr14;
502 unsigned int save_sr15;
503
504 /* The following are the control area for this save area */
505
506 /* offset 0x0480 */
507
508 struct savearea *save_prev; /* The address of the previous normal savearea */
509 struct savearea *save_prev_float; /* The address of the previous floating point savearea */
510 struct savearea *save_prev_vector; /* The address of the previous vector savearea */
511 struct savearea *save_qfret; /* The "quick release" chain */
512 struct savearea *save_phys; /* The physical address of this savearea */
513 struct thread_activation *save_act; /* Pointer to the associated activation */
514 unsigned int save_flags; /* Various flags */
515 #define save_perm 0x80000000 /* Permanent area, cannot be released */
516 unsigned int save_level_fp; /* Level that floating point state belongs to */
517 unsigned int save_level_vec; /* Level that vector state belongs to */
518
519 } savearea;
520
521 typedef struct savectl { /* Savearea control */
522
523 unsigned int *sac_next; /* Points to next savearea page that has a free slot - real */
524 unsigned int sac_vrswap; /* XOR mask to swap V to R or vice versa */
525 unsigned int sac_alloc; /* Bitmap of allocated slots */
526 unsigned int sac_flags; /* Various flags */
527 } savectl;
528
529 struct Saveanchor {
530 unsigned int savelock; /* Lock word for savearea manipulation */
531 int savecount; /* The total number of save areas allocated */
532 int saveinuse; /* Number of areas in use */
533 int savemin; /* We abend if lower than this */
534 int saveneghyst; /* The negative hysteresis value */
535 int savetarget; /* The target point for free save areas */
536 int saveposhyst; /* The positive hysteresis value */
537 unsigned int savefree; /* Anchor for the freelist queue */
538 /* Cache line (32-byte) boundary */
539 int savextnd; /* Free list extention count */
540 int saveneed; /* Number of savearea's needed. So far, we assume we need 3 per activation */
541 int savemaxcount;
542 int savespare[5]; /* Spare */
543 };
544
545
546 extern char *trap_type[];
547
548 #endif /* ndef ASSEMBLER */
549
550 #define sac_empty 0xC0000000 /* Mask with all entries empty */
551 #define sac_cnt 2 /* Number of entries per page */
552 #define sac_busy 0x80000000 /* This page is busy - used during initial allocation */
553 #define sac_perm 0x40000000 /* Page permanently assigned */
554
555 #define SAVattach 0x80000000 /* Savearea is attached to a thread */
556 #define SAVfpuvalid 0x40000000 /* Savearea contains FPU context */
557 #define SAVvmxvalid 0x20000000 /* Savearea contains VMX context */
558 #define SAVinuse 0xE0000000 /* Save area is inuse */
559 #define SAVrststk 0x00010000 /* Indicates that the current stack should be reset to empty */
560 #define SAVsyscall 0x00020000 /* Indicates that the savearea is associated with a syscall */
561 #define SAVredrive 0x00040000 /* Indicates that the low-level fault handler associated */
562 /* with this savearea should be redriven */
563
564 /* cpu_flags defs */
565 #define SIGPactive 0x8000
566 #define needSRload 0x4000
567 #define turnEEon 0x2000
568 #define traceBE 0x1000 /* user mode BE tracing in enabled */
569 #define traceBEb 3 /* bit number for traceBE */
570 #define BootDone 0x0100
571 #define SignalReady 0x0200
572 #define loadMSR 0x7FF4
573
574 #define T_VECTOR_SIZE 4 /* function pointer size */
575 #define InitialSaveMin 4 /* The initial value for the minimum number of saveareas */
576 #define InitialNegHysteresis 5 /* The number off from target before we adjust upwards */
577 #define InitialPosHysteresis 10 /* The number off from target before we adjust downwards */
578 #define InitialSaveTarget 20 /* The number of saveareas for an initial target */
579 #define InitialSaveAreas 20 /* The number of saveareas to allocate at boot */
580 #define InitialSaveBloks (InitialSaveAreas+sac_cnt-1)/sac_cnt /* The number of savearea blocks to allocate at boot */
581
582 /* Hardware exceptions */
583
584 #define T_IN_VAIN (0x00 * T_VECTOR_SIZE)
585 #define T_RESET (0x01 * T_VECTOR_SIZE)
586 #define T_MACHINE_CHECK (0x02 * T_VECTOR_SIZE)
587 #define T_DATA_ACCESS (0x03 * T_VECTOR_SIZE)
588 #define T_INSTRUCTION_ACCESS (0x04 * T_VECTOR_SIZE)
589 #define T_INTERRUPT (0x05 * T_VECTOR_SIZE)
590 #define T_ALIGNMENT (0x06 * T_VECTOR_SIZE)
591 #define T_PROGRAM (0x07 * T_VECTOR_SIZE)
592 #define T_FP_UNAVAILABLE (0x08 * T_VECTOR_SIZE)
593 #define T_DECREMENTER (0x09 * T_VECTOR_SIZE)
594 #define T_IO_ERROR (0x0a * T_VECTOR_SIZE)
595 #define T_RESERVED (0x0b * T_VECTOR_SIZE)
596 #define T_SYSTEM_CALL (0x0c * T_VECTOR_SIZE)
597 #define T_TRACE (0x0d * T_VECTOR_SIZE)
598 #define T_FP_ASSIST (0x0e * T_VECTOR_SIZE)
599 #define T_PERF_MON (0x0f * T_VECTOR_SIZE)
600 #define T_VMX (0x10 * T_VECTOR_SIZE)
601 #define T_INVALID_EXCP0 (0x11 * T_VECTOR_SIZE)
602 #define T_INVALID_EXCP1 (0x12 * T_VECTOR_SIZE)
603 #define T_INVALID_EXCP2 (0x13 * T_VECTOR_SIZE)
604 #define T_INSTRUCTION_BKPT (0x14 * T_VECTOR_SIZE)
605 #define T_SYSTEM_MANAGEMENT (0x15 * T_VECTOR_SIZE)
606 #define T_ALTIVEC_ASSIST (0x16 * T_VECTOR_SIZE)
607 #define T_THERMAL (0x17 * T_VECTOR_SIZE)
608 #define T_INVALID_EXCP5 (0x18 * T_VECTOR_SIZE)
609 #define T_INVALID_EXCP6 (0x19 * T_VECTOR_SIZE)
610 #define T_INVALID_EXCP7 (0x1A * T_VECTOR_SIZE)
611 #define T_INVALID_EXCP8 (0x1B * T_VECTOR_SIZE)
612 #define T_INVALID_EXCP9 (0x1C * T_VECTOR_SIZE)
613 #define T_INVALID_EXCP10 (0x1D * T_VECTOR_SIZE)
614 #define T_INVALID_EXCP11 (0x1E * T_VECTOR_SIZE)
615 #define T_INVALID_EXCP12 (0x1F * T_VECTOR_SIZE)
616 #define T_INVALID_EXCP13 (0x20 * T_VECTOR_SIZE)
617
618 #define T_RUNMODE_TRACE (0x21 * T_VECTOR_SIZE) /* 601 only */
619
620 #define T_SIGP (0x22 * T_VECTOR_SIZE)
621 #define T_PREEMPT (0x23 * T_VECTOR_SIZE)
622 #define T_CSWITCH (0x24 * T_VECTOR_SIZE)
623 #define T_SHUTDOWN (0x25 * T_VECTOR_SIZE)
624 #define T_CHOKE (0x26 * T_VECTOR_SIZE)
625
626 #define T_AST (0x100 * T_VECTOR_SIZE)
627 #define T_MAX T_CHOKE /* Maximum exception no */
628
629 #define EXCEPTION_VECTOR(exception) (exception * 0x100 /T_VECTOR_SIZE )
630
631 /*
632 * System choke (failure) codes
633 */
634
635 #define failDebug 0
636 #define failStack 1
637 #define failMapping 2
638 #define failContext 3
639
640 /* Always must be last - update failNames table in model_dep.c as well */
641 #define failUnknown 4
642
643 #ifndef ASSEMBLER
644
645 typedef struct resethandler {
646 unsigned int type;
647 vm_offset_t call_paddr;
648 vm_offset_t arg__paddr;
649 } resethandler_t;
650
651 extern resethandler_t ResetHandler;
652
653 #endif
654
655 #define RESET_HANDLER_NULL 0x0
656 #define RESET_HANDLER_START 0x1
657
658 #endif /* _PPC_EXCEPTION_H_ */
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