osfmk/i386/proc_reg.h

   1 /*
   2  * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31 /* CMU_ENDHIST */
  32 /*
  33  * Mach Operating System
  34  * Copyright (c) 1991,1990 Carnegie Mellon University
  35  * All Rights Reserved.
  36  *
  37  * Permission to use, copy, modify and distribute this software and its
  38  * documentation is hereby granted, provided that both the copyright
  39  * notice and this permission notice appear in all copies of the
  40  * software, derivative works or modified versions, and any portions
  41  * thereof, and that both notices appear in supporting documentation.
  42  *
  43  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  44  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  45  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  46  *
  47  * Carnegie Mellon requests users of this software to return to
  48  *
  49  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  50  *  School of Computer Science
  51  *  Carnegie Mellon University
  52  *  Pittsburgh PA 15213-3890
  53  *
  54  * any improvements or extensions that they make and grant Carnegie Mellon
  55  * the rights to redistribute these changes.
  56  */
  57
  58 /*
  59  */
  60
  61 /*
  62  * Processor registers for i386 and i486.
  63  */
  64 #ifndef _I386_PROC_REG_H_
  65 #define _I386_PROC_REG_H_
  66
  67 /*
  68  * Model Specific Registers
  69  */
  70 #define MSR_P5_TSC              0x10    /* Time Stamp Register */
  71 #define MSR_P5_CESR             0x11    /* Control and Event Select Register */
  72 #define MSR_P5_CTR0             0x12    /* Counter #0 */
  73 #define MSR_P5_CTR1             0x13    /* Counter #1 */
  74
  75 #define MSR_P5_CESR_PC          0x0200  /* Pin Control */
  76 #define MSR_P5_CESR_CC          0x01C0  /* Counter Control mask */
  77 #define MSR_P5_CESR_ES          0x003F  /* Event Control mask */
  78
  79 #define MSR_P5_CESR_SHIFT       16              /* Shift to get Counter 1 */
  80 #define MSR_P5_CESR_MASK        (MSR_P5_CESR_PC|\
  81                                  MSR_P5_CESR_CC|\
  82                                  MSR_P5_CESR_ES) /* Mask Counter */
  83
  84 #define MSR_P5_CESR_CC_CLOCK    0x0100  /* Clock Counting (otherwise Event) */
  85 #define MSR_P5_CESR_CC_DISABLE  0x0000  /* Disable counter */
  86 #define MSR_P5_CESR_CC_CPL012   0x0040  /* Count if the CPL == 0, 1, 2 */
  87 #define MSR_P5_CESR_CC_CPL3     0x0080  /* Count if the CPL == 3 */
  88 #define MSR_P5_CESR_CC_CPL      0x00C0  /* Count regardless of the CPL */
  89
  90 #define MSR_P5_CESR_ES_DATA_READ       0x000000 /* Data Read */
  91 #define MSR_P5_CESR_ES_DATA_WRITE      0x000001 /* Data Write */
  92 #define MSR_P5_CESR_ES_DATA_RW         0x101000 /* Data Read or Write */
  93 #define MSR_P5_CESR_ES_DATA_TLB_MISS   0x000010 /* Data TLB Miss */
  94 #define MSR_P5_CESR_ES_DATA_READ_MISS  0x000011 /* Data Read Miss */
  95 #define MSR_P5_CESR_ES_DATA_WRITE_MISS 0x000100 /* Data Write Miss */
  96 #define MSR_P5_CESR_ES_DATA_RW_MISS    0x101001 /* Data Read or Write Miss */
  97 #define MSR_P5_CESR_ES_HIT_EM          0x000101 /* Write (hit) to M|E state */
  98 #define MSR_P5_CESR_ES_DATA_CACHE_WB   0x000110 /* Cache lines written back */
  99 #define MSR_P5_CESR_ES_EXTERNAL_SNOOP  0x000111 /* External Snoop */
 100 #define MSR_P5_CESR_ES_CACHE_SNOOP_HIT 0x001000 /* Data cache snoop hits */
 101 #define MSR_P5_CESR_ES_MEM_ACCESS_PIPE 0x001001 /* Mem. access in both pipes */
 102 #define MSR_P5_CESR_ES_BANK_CONFLICTS  0x001010 /* Bank conflicts */
 103 #define MSR_P5_CESR_ES_MISALIGNED      0x001011 /* Misaligned Memory or I/O */
 104 #define MSR_P5_CESR_ES_CODE_READ       0x001100 /* Code Read */
 105 #define MSR_P5_CESR_ES_CODE_TLB_MISS   0x001101 /* Code TLB miss */
 106 #define MSR_P5_CESR_ES_CODE_CACHE_MISS 0x001110 /* Code Cache miss */
 107 #define MSR_P5_CESR_ES_SEGMENT_LOADED  0x001111 /* Any segment reg. loaded */
 108 #define MSR_P5_CESR_ES_BRANCHE         0x010010 /* Branches */
 109 #define MSR_P5_CESR_ES_BTB_HIT         0x010011 /* BTB Hits */
 110 #define MSR_P5_CESR_ES_BRANCHE_BTB     0x010100 /* Taken branch or BTB Hit */
 111 #define MSR_P5_CESR_ES_PIPELINE_FLUSH  0x010101 /* Pipeline Flushes */
 112 #define MSR_P5_CESR_ES_INSTRUCTION     0x010110 /* Instruction executed */
 113 #define MSR_P5_CESR_ES_INSTRUCTION_V   0x010111 /* Inst. executed (v-pipe) */
 114 #define MSR_P5_CESR_ES_BUS_CYCLE       0x011000 /* Clocks while bus cycle */
 115 #define MSR_P5_CESR_ES_FULL_WRITE_BUF  0x011001 /* Clocks while full wrt buf. */
 116 #define MSR_P5_CESR_ES_DATA_MEM_READ   0x011010 /* Pipeline waiting for read */
 117 #define MSR_P5_CESR_ES_WRITE_EM        0x011011 /* Stall on write E|M state */
 118 #define MSR_P5_CESR_ES_LOCKED_CYCLE    0x011100 /* Locked bus cycles */
 119 #define MSR_P5_CESR_ES_IO_CYCLE        0x011101 /* I/O Read or Write cycles */
 120 #define MSR_P5_CESR_ES_NON_CACHEABLE   0x011110 /* Non-cacheable Mem. read */
 121 #define MSR_P5_CESR_ES_AGI             0x011111 /* Stall because of AGI */
 122 #define MSR_P5_CESR_ES_FLOP            0x100010 /* Floating Point operations */
 123 #define MSR_P5_CESR_ES_BREAK_DR0       0x100011 /* Breakpoint matches on DR0 */
 124 #define MSR_P5_CESR_ES_BREAK_DR1       0x100100 /* Breakpoint matches on DR1 */
 125 #define MSR_P5_CESR_ES_BREAK_DR2       0x100101 /* Breakpoint matches on DR2 */
 126 #define MSR_P5_CESR_ES_BREAK_DR3       0x100110 /* Breakpoint matches on DR3 */
 127 #define MSR_P5_CESR_ES_HARDWARE_IT     0x100111 /* Hardware interrupts */
 128
 129 /*
 130  * CR0
 131  */
 132 #define CR0_PG  0x80000000      /*       Enable paging */
 133 #define CR0_CD  0x40000000      /* i486: Cache disable */
 134 #define CR0_NW  0x20000000      /* i486: No write-through */
 135 #define CR0_AM  0x00040000      /* i486: Alignment check mask */
 136 #define CR0_WP  0x00010000      /* i486: Write-protect kernel access */
 137 #define CR0_NE  0x00000020      /* i486: Handle numeric exceptions */
 138 #define CR0_ET  0x00000010      /*       Extension type is 80387 */
 139                                 /*       (not official) */
 140 #define CR0_TS  0x00000008      /*       Task switch */
 141 #define CR0_EM  0x00000004      /*       Emulate coprocessor */
 142 #define CR0_MP  0x00000002      /*       Monitor coprocessor */
 143 #define CR0_PE  0x00000001      /*       Enable protected mode */
 144
 145 /*
 146  * CR4
 147  */
 148 #define CR4_VMXE 0x00002000     /* Enable VMX operation */
 149 #define CR4_FXS 0x00000200      /* SSE/SSE2 OS supports FXSave */
 150 #define CR4_XMM 0x00000400      /* SSE/SSE2 instructions supported in OS */
 151 #define CR4_PGE 0x00000080      /* p6:   Page Global Enable */
 152 #define CR4_MCE 0x00000040      /* p5:   Machine Check Exceptions */
 153 #define CR4_PAE 0x00000020      /* p5:   Physical Address Extensions */
 154 #define CR4_PSE 0x00000010      /* p5:   Page Size Extensions */
 155 #define CR4_DE  0x00000008      /* p5:   Debugging Extensions */
 156 #define CR4_TSD 0x00000004      /* p5:   Time Stamp Disable */
 157 #define CR4_PVI 0x00000002      /* p5:   Protected-mode Virtual Interrupts */
 158 #define CR4_VME 0x00000001      /* p5:   Virtual-8086 Mode Extensions */
 159
 160 #ifndef ASSEMBLER
 161
 162 #include <sys/cdefs.h>
 163 #include <stdint.h>
 164
 165 __BEGIN_DECLS
 166
 167 #define set_ts() set_cr0(get_cr0() | CR0_TS)
 168
 169 static inline uintptr_t get_cr0(void)
 170 {
 171         uintptr_t cr0;
 172         __asm__ volatile("mov %%cr0, %0" : "=r" (cr0));
 173         return(cr0);
 174 }
 175
 176 static inline void set_cr0(uintptr_t value)
 177 {
 178         __asm__ volatile("mov %0, %%cr0" : : "r" (value));
 179 }
 180
 181 static inline uintptr_t get_cr2(void)
 182 {
 183         uintptr_t cr2;
 184         __asm__ volatile("mov %%cr2, %0" : "=r" (cr2));
 185         return(cr2);
 186 }
 187
 188 static inline uintptr_t get_cr3(void)
 189 {
 190         register uintptr_t cr3;
 191         __asm__ volatile("mov %%cr3, %0" : "=r" (cr3));
 192         return(cr3);
 193 }
 194
 195 static inline void set_cr3(uintptr_t value)
 196 {
 197         __asm__ volatile("mov %0, %%cr3" : : "r" (value));
 198 }
 199
 200 static inline uintptr_t get_cr4(void)
 201 {
 202         uintptr_t cr4;
 203         __asm__ volatile("mov %%cr4, %0" : "=r" (cr4));
 204         return(cr4);
 205 }
 206
 207 static inline void set_cr4(uintptr_t value)
 208 {
 209         __asm__ volatile("mov %0, %%cr4" : : "r" (value));
 210 }
 211
 212 static inline void clear_ts(void)
 213 {
 214         __asm__ volatile("clts");
 215 }
 216
 217 static inline unsigned short get_tr(void)
 218 {
 219         unsigned short seg;
 220         __asm__ volatile("str %0" : "=rm" (seg));
 221         return(seg);
 222 }
 223
 224 static inline void set_tr(unsigned int seg)
 225 {
 226         __asm__ volatile("ltr %0" : : "rm" ((unsigned short)(seg)));
 227 }
 228
 229 static inline unsigned short sldt(void)
 230 {
 231         unsigned short seg;
 232         __asm__ volatile("sldt %0" : "=rm" (seg));
 233         return(seg);
 234 }
 235
 236 static inline void lldt(unsigned int seg)
 237 {
 238         __asm__ volatile("lldt %0" : : "rm" ((unsigned short)(seg)));
 239 }
 240
 241 static inline void lgdt(uintptr_t *desc)
 242 {
 243         __asm__ volatile("lgdt %0" : : "m" (*desc));
 244 }
 245
 246 static inline void lidt(uintptr_t *desc)
 247 {
 248         __asm__ volatile("lidt %0" : : "m" (*desc));
 249 }
 250
 251 static inline void swapgs(void)
 252 {
 253         __asm__ volatile("swapgs");
 254 }
 255
 256 #ifdef MACH_KERNEL_PRIVATE
 257
 258
 259
 260 #ifdef __i386__
 261
 262 #include <i386/cpu_data.h>
 263
 264 extern void cpuid64(uint32_t);
 265 extern void flush_tlb64(void);
 266 extern uint64_t get64_cr3(void);
 267 extern void set64_cr3(uint64_t);
 268 static inline void flush_tlb(void)
 269 {
 270         if (cpu_mode_is64bit()) {
 271                 flush_tlb64();
 272         } else {
 273                 set_cr3(get_cr3());
 274         }
 275 }
 276 #elif defined(__x86_64__)
 277 static inline void flush_tlb(void)
 278 {
 279         set_cr3(get_cr3());
 280 }
 281 #else
 282 #error Unsupported architecture
 283 #endif
 284
 285
 286 #endif  /* MACH_KERNEL_PRIVATE */
 287
 288 static inline void wbinvd(void)
 289 {
 290         __asm__ volatile("wbinvd");
 291 }
 292
 293 static inline void invlpg(uintptr_t addr)
 294 {
 295         __asm__  volatile("invlpg (%0)" :: "r" (addr) : "memory");
 296 }
 297
 298 /*
 299  * Access to machine-specific registers (available on 586 and better only)
 300  * Note: the rd* operations modify the parameters directly (without using
 301  * pointer indirection), this allows gcc to optimize better
 302  */
 303
 304 #define rdmsr(msr,lo,hi) \
 305         __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr))
 306
 307 #define wrmsr(msr,lo,hi) \
 308         __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
 309
 310 #define rdtsc(lo,hi) \
 311         __asm__ volatile("lfence; rdtsc; lfence" : "=a" (lo), "=d" (hi))
 312
 313 #define write_tsc(lo,hi) wrmsr(0x10, lo, hi)
 314
 315 #define rdpmc(counter,lo,hi) \
 316         __asm__ volatile("rdpmc" : "=a" (lo), "=d" (hi) : "c" (counter))
 317
 318 #ifdef __i386__
 319
 320 static inline uint64_t rdmsr64(uint32_t msr)
 321 {
 322         uint64_t ret;
 323         __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));
 324         return ret;
 325 }
 326
 327 static inline void wrmsr64(uint32_t msr, uint64_t val)
 328 {
 329         __asm__ volatile("wrmsr" : : "c" (msr), "A" (val));
 330 }
 331
 332 static inline uint64_t rdtsc64(void)
 333 {
 334         uint64_t ret;
 335         __asm__ volatile("lfence; rdtsc; lfence" : "=A" (ret));
 336         return ret;
 337 }
 338
 339 static inline uint64_t rdtscp64(uint32_t *aux)
 340 {
 341         uint64_t ret;
 342         __asm__ volatile("rdtscp; mov %%ecx, %1"
 343                                 : "=A" (ret), "=m" (*aux)
 344                                 :
 345                                 : "ecx");
 346         return ret;
 347 }
 348
 349 #elif defined(__x86_64__)
 350
 351 static inline uint64_t rdmsr64(uint32_t msr)
 352 {
 353         uint32_t lo=0, hi=0;
 354         rdmsr(msr, lo, hi);
 355         return (((uint64_t)hi) << 32) | ((uint64_t)lo);
 356 }
 357
 358 static inline void wrmsr64(uint32_t msr, uint64_t val)
 359 {
 360         wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL));
 361 }
 362
 363 static inline uint64_t rdtsc64(void)
 364 {
 365         uint32_t lo, hi;
 366         rdtsc(lo, hi);
 367         return (((uint64_t)hi) << 32) | ((uint64_t)lo);
 368 }
 369
 370 static inline uint64_t rdtscp64(uint32_t *aux)
 371 {
 372         uint32_t lo, hi;
 373         __asm__ volatile("rdtscp; mov %%ecx, %1"
 374                                          : "=a" (lo), "=d" (hi), "=m" (*aux)
 375                                          :
 376                                          : "ecx");
 377         return (((uint64_t)hi) << 32) | ((uint64_t)lo);
 378 }
 379
 380 #else
 381 #error Unsupported architecture
 382 #endif
 383
 384 /*
 385  * rdmsr_carefully() returns 0 when the MSR has been read successfully,
 386  * or non-zero (1) if the MSR does not exist.
 387  * The implementation is in locore.s.
 388  */
 389 extern int rdmsr_carefully(uint32_t msr, uint32_t *lo, uint32_t *hi);
 390
 391 __END_DECLS
 392
 393 #endif  /* ASSEMBLER */
 394
 395 #define MSR_IA32_P5_MC_ADDR             0
 396 #define MSR_IA32_P5_MC_TYPE             1
 397 #define MSR_IA32_PLATFORM_ID            0x17
 398 #define MSR_IA32_EBL_CR_POWERON         0x2a
 399
 400 #define MSR_IA32_APIC_BASE              0x1b
 401 #define MSR_IA32_APIC_BASE_BSP          (1<<8)
 402 #define MSR_IA32_APIC_BASE_ENABLE       (1<<11)
 403 #define MSR_IA32_APIC_BASE_BASE         (0xfffff<<12)
 404
 405 #define MSR_IA32_FEATURE_CONTROL        0x3a
 406 #define MSR_IA32_FEATCTL_LOCK           (1<<0)
 407 #define MSR_IA32_FEATCTL_VMXON_SMX      (1<<1)
 408 #define MSR_IA32_FEATCTL_VMXON          (1<<2)
 409 #define MSR_IA32_FEATCTL_CSTATE_SMI     (1<<16)
 410
 411 #define MSR_IA32_UCODE_WRITE            0x79
 412 #define MSR_IA32_UCODE_REV              0x8b
 413
 414 #define MSR_IA32_PERFCTR0               0xc1
 415 #define MSR_IA32_PERFCTR1               0xc2
 416
 417 #define MSR_PMG_CST_CONFIG_CONTROL      0xe2
 418
 419 #define MSR_IA32_BBL_CR_CTL             0x119
 420
 421 #define MSR_IA32_SYSENTER_CS            0x174
 422 #define MSR_IA32_SYSENTER_ESP           0x175
 423 #define MSR_IA32_SYSENTER_EIP           0x176
 424
 425 #define MSR_IA32_MCG_CAP                0x179
 426 #define MSR_IA32_MCG_STATUS             0x17a
 427 #define MSR_IA32_MCG_CTL                0x17b
 428
 429 #define MSR_IA32_EVNTSEL0               0x186
 430 #define MSR_IA32_EVNTSEL1               0x187
 431
 432 #define MSR_IA32_PERF_STS               0x198
 433 #define MSR_IA32_PERF_CTL               0x199
 434
 435 #define MSR_IA32_MISC_ENABLE            0x1a0
 436
 437 #define MSR_IA32_DEBUGCTLMSR            0x1d9
 438 #define MSR_IA32_LASTBRANCHFROMIP       0x1db
 439 #define MSR_IA32_LASTBRANCHTOIP         0x1dc
 440 #define MSR_IA32_LASTINTFROMIP          0x1dd
 441 #define MSR_IA32_LASTINTTOIP            0x1de
 442
 443 #define MSR_IA32_CR_PAT                 0x277
 444
 445 #define MSR_IA32_MC0_CTL                0x400
 446 #define MSR_IA32_MC0_STATUS             0x401
 447 #define MSR_IA32_MC0_ADDR               0x402
 448 #define MSR_IA32_MC0_MISC               0x403
 449
 450 #define MSR_IA32_MTRRCAP                0xfe
 451 #define MSR_IA32_MTRR_DEF_TYPE          0x2ff
 452 #define MSR_IA32_MTRR_PHYSBASE(n)       (0x200 + 2*(n))
 453 #define MSR_IA32_MTRR_PHYSMASK(n)       (0x200 + 2*(n) + 1)
 454 #define MSR_IA32_MTRR_FIX64K_00000      0x250
 455 #define MSR_IA32_MTRR_FIX16K_80000      0x258
 456 #define MSR_IA32_MTRR_FIX16K_A0000      0x259
 457 #define MSR_IA32_MTRR_FIX4K_C0000       0x268
 458 #define MSR_IA32_MTRR_FIX4K_C8000       0x269
 459 #define MSR_IA32_MTRR_FIX4K_D0000       0x26a
 460 #define MSR_IA32_MTRR_FIX4K_D8000       0x26b
 461 #define MSR_IA32_MTRR_FIX4K_E0000       0x26c
 462 #define MSR_IA32_MTRR_FIX4K_E8000       0x26d
 463 #define MSR_IA32_MTRR_FIX4K_F0000       0x26e
 464 #define MSR_IA32_MTRR_FIX4K_F8000       0x26f
 465
 466 #define MSR_IA32_VMX_BASE               0x480
 467 #define MSR_IA32_VMX_BASIC              MSR_IA32_VMX_BASE
 468 #define MSR_IA32_VMXPINBASED_CTLS               MSR_IA32_VMX_BASE+1
 469 #define MSR_IA32_PROCBASED_CTLS         MSR_IA32_VMX_BASE+2
 470 #define MSR_IA32_VMX_EXIT_CTLS          MSR_IA32_VMX_BASE+3
 471 #define MSR_IA32_VMX_ENTRY_CTLS         MSR_IA32_VMX_BASE+4
 472 #define MSR_IA32_VMX_MISC               MSR_IA32_VMX_BASE+5
 473 #define MSR_IA32_VMX_CR0_FIXED0         MSR_IA32_VMX_BASE+6
 474 #define MSR_IA32_VMX_CR0_FIXED1         MSR_IA32_VMX_BASE+7
 475 #define MSR_IA32_VMX_CR4_FIXED0         MSR_IA32_VMX_BASE+8
 476 #define MSR_IA32_VMX_CR4_FIXED1         MSR_IA32_VMX_BASE+9
 477
 478 #define MSR_IA32_EFER           0xC0000080
 479 #define MSR_IA32_EFER_SCE       0x00000001
 480 #define MSR_IA32_EFER_LME       0x00000100
 481 #define MSR_IA32_EFER_LMA       0x00000400
 482 #define MSR_IA32_EFER_NXE       0x00000800
 483
 484 #define MSR_IA32_STAR           0xC0000081
 485 #define MSR_IA32_LSTAR          0xC0000082
 486 #define MSR_IA32_CSTAR          0xC0000083
 487 #define MSR_IA32_FMASK          0xC0000084
 488
 489 #define MSR_IA32_FS_BASE        0xC0000100
 490 #define MSR_IA32_GS_BASE        0xC0000101
 491 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
 492
 493 #define MSR_IA32_BIOS_SIGN_ID   0x08B
 494
 495 #define MSR_FLEX_RATIO          0x194
 496 #define MSR_PLATFORM_INFO       0x0ce
 497 #define MSR_CORE_THREAD_COUNT   0x035
 498
 499 #endif  /* _I386_PROC_REG_H_ */