pexpert/i386/pe_serial.c

   1 /*
   2  * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 /*
  30  * file: pe_serial.c
  31  *       Polled-mode 16x50 UART driver.
  32  */
  33
  34 #include <machine/machine_routines.h>
  35 #include <pexpert/protos.h>
  36 #include <pexpert/pexpert.h>
  37
  38 struct pe_serial_functions {
  39     void            (*uart_init) (void);
  40     void            (*uart_set_baud_rate) (int unit, uint32_t baud_rate);
  41     int             (*tr0) (void);
  42     void            (*td0) (int c);
  43     int             (*rr0) (void);
  44     int             (*rd0) (void);
  45 };
  46
  47 static struct pe_serial_functions *gPESF;
  48
  49 static int uart_initted = 0;   /* 1 if init'ed */
  50
  51 static unsigned int legacy_uart_enabled = 0; /* 1 Legacy IO based UART is supported on platform */
  52
  53 static boolean_t lpss_uart_supported = 0; /* 1 if LPSS UART is supported on platform */
  54 static unsigned int lpss_uart_enabled = 0; /* 1 if it is LPSS UART is in D0 state */
  55 static void lpss_uart_re_init (void);
  56
  57 #define DEFAULT_UART_BAUD_RATE 115200
  58
  59 static unsigned uart_baud_rate = DEFAULT_UART_BAUD_RATE;
  60
  61 // =============================================================================
  62 // Legacy UART support using IO transactions to COM1 or COM2
  63 // =============================================================================
  64
  65 #define LEGACY_UART_PORT_ADDR   COM1_PORT_ADDR
  66 #define LEGACY_UART_CLOCK       1843200   /* 1.8432 MHz clock */
  67
  68 #define IO_WRITE(r, v)  outb(LEGACY_UART_PORT_ADDR + UART_##r, v)
  69 #define IO_READ(r)      inb(LEGACY_UART_PORT_ADDR + UART_##r)
  70
  71 enum {
  72     COM1_PORT_ADDR = 0x3f8,
  73     COM2_PORT_ADDR = 0x2f8
  74 };
  75
  76 enum {
  77     UART_RBR = 0,  /* receive buffer Register   (R) */
  78     UART_THR = 0,  /* transmit holding register (W) */
  79     UART_DLL = 0,  /* DLAB = 1, divisor latch (LSB) */
  80     UART_IER = 1,  /* interrupt enable register     */
  81     UART_DLM = 1,  /* DLAB = 1, divisor latch (MSB) */
  82     UART_IIR = 2,  /* interrupt ident register (R)  */
  83     UART_FCR = 2,  /* fifo control register (W)     */
  84     UART_LCR = 3,  /* line control register         */
  85     UART_MCR = 4,  /* modem control register        */
  86     UART_LSR = 5,  /* line status register          */
  87     UART_MSR = 6,  /* modem status register         */
  88     UART_SCR = 7   /* scratch register              */
  89 };
  90
  91 enum {
  92     UART_LCR_8BITS = 0x03,
  93     UART_LCR_DLAB  = 0x80
  94 };
  95
  96 enum {
  97     UART_MCR_DTR   = 0x01,
  98     UART_MCR_RTS   = 0x02,
  99     UART_MCR_OUT1  = 0x04,
 100     UART_MCR_OUT2  = 0x08,
 101     UART_MCR_LOOP  = 0x10
 102 };
 103
 104 enum {
 105     UART_LSR_DR    = 0x01,
 106     UART_LSR_OE    = 0x02,
 107     UART_LSR_PE    = 0x04,
 108     UART_LSR_FE    = 0x08,
 109     UART_LSR_THRE  = 0x20
 110 };
 111
 112 enum {
 113         UART_CLK_125M_1 = 0x60002,
 114         UART_CLK_125M_2 = 0x80060003,
 115 };
 116
 117 static int
 118 legacy_uart_probe( void )
 119 {
 120     /* Verify that the Scratch Register is accessible */
 121
 122     IO_WRITE( SCR, 0x5a );
 123     if (IO_READ(SCR) != 0x5a) return 0;
 124     IO_WRITE( SCR, 0xa5 );
 125     if (IO_READ(SCR) != 0xa5) return 0;
 126     return 1;
 127 }
 128
 129 static void
 130 legacy_uart_set_baud_rate( __unused int unit, uint32_t baud_rate )
 131 {
 132     const unsigned char lcr = IO_READ( LCR );
 133     unsigned long       div;
 134
 135     if (baud_rate == 0) baud_rate = 9600;
 136     div = LEGACY_UART_CLOCK / 16 / baud_rate;
 137     IO_WRITE( LCR, lcr | UART_LCR_DLAB );
 138     IO_WRITE( DLM, (unsigned char)(div >> 8) );
 139     IO_WRITE( DLL, (unsigned char) div );
 140     IO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
 141 }
 142
 143 static int
 144 legacy_uart_tr0( void )
 145 {
 146     return (IO_READ(LSR) & UART_LSR_THRE);
 147 }
 148
 149 static void
 150 legacy_uart_td0( int c )
 151 {
 152     IO_WRITE( THR, c );
 153 }
 154
 155 static void
 156 legacy_uart_init( void )
 157 {
 158     /* Disable hardware interrupts */
 159
 160     IO_WRITE( MCR, 0 );
 161     IO_WRITE( IER, 0 );
 162
 163     /* Disable FIFO's for 16550 devices */
 164
 165     IO_WRITE( FCR, 0 );
 166
 167     /* Set for 8-bit, no parity, DLAB bit cleared */
 168
 169     IO_WRITE( LCR, UART_LCR_8BITS );
 170
 171     /* Set baud rate */
 172
 173     gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
 174
 175     /* Assert DTR# and RTS# lines (OUT2?) */
 176
 177     IO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );
 178
 179     /* Clear any garbage in the input buffer */
 180
 181     IO_READ( RBR );
 182
 183     uart_initted = 1;
 184 }
 185
 186 static int
 187 legacy_uart_rr0( void )
 188 {
 189     unsigned char lsr;
 190
 191     lsr = IO_READ( LSR );
 192
 193     if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
 194     {
 195         IO_READ( RBR ); /* discard */
 196         return 0;
 197     }
 198
 199     return (lsr & UART_LSR_DR);
 200 }
 201
 202 static int
 203 legacy_uart_rd0( void )
 204 {
 205     return IO_READ( RBR );
 206 }
 207
 208 static struct pe_serial_functions legacy_uart_serial_functions = {
 209     .uart_init = legacy_uart_init,
 210     .uart_set_baud_rate = legacy_uart_set_baud_rate,
 211     .tr0 = legacy_uart_tr0,
 212     .td0 = legacy_uart_td0,
 213     .rr0 = legacy_uart_rr0,
 214     .rd0 = legacy_uart_rd0
 215 };
 216
 217 // =============================================================================
 218 // MMIO UART (using PCH LPSS UART2)
 219 // =============================================================================
 220
 221 #define MMIO_UART2_BASE_LEGACY  0xFE034000 /* Legacy MMIO Config space */
 222 #define MMIO_UART2_BASE         0xFE036000 /* MMIO Config space */
 223 #define PCI_UART2               0xFE037000 /* PCI Config Space */
 224
 225 #define MMIO_WRITE(r, v)  ml_phys_write_word(mmio_uart_base + MMIO_UART_##r, v)
 226 #define MMIO_READ(r)      ml_phys_read_word(mmio_uart_base + MMIO_UART_##r)
 227
 228 enum {
 229     MMIO_UART_RBR = 0x0,   /* receive buffer Register   (R) */
 230     MMIO_UART_THR = 0x0,   /* transmit holding register (W) */
 231     MMIO_UART_DLL = 0x0,   /* DLAB = 1, divisor latch (LSB) */
 232     MMIO_UART_IER = 0x4,   /* interrupt enable register     */
 233     MMIO_UART_DLM = 0x4,   /* DLAB = 1, divisor latch (MSB) */
 234     MMIO_UART_FCR = 0x8,   /* fifo control register (W)     */
 235     MMIO_UART_LCR = 0xc,   /* line control register         */
 236     MMIO_UART_MCR = 0x10,  /* modem control register        */
 237     MMIO_UART_LSR = 0x14,  /* line status register          */
 238     MMIO_UART_SCR = 0x1c,  /* scratch register              */
 239     MMIO_UART_CLK = 0x200, /* clocks register               */
 240     MMIO_UART_RST = 0x204  /* Reset register              */
 241 };
 242
 243 static vm_offset_t mmio_uart_base = 0;
 244
 245 static int
 246 mmio_uart_present( void )
 247 {
 248     MMIO_WRITE( SCR, 0x5a );
 249     if (MMIO_READ(SCR) != 0x5a) return 0;
 250     MMIO_WRITE( SCR, 0xa5 );
 251     if (MMIO_READ(SCR) != 0xa5) return 0;
 252     return 1;
 253 }
 254
 255 static int
 256 mmio_uart_probe( void )
 257 {
 258     unsigned new_mmio_uart_base = 0;
 259
 260     // if specified, mmio_uart overrides all probing
 261     if (PE_parse_boot_argn("mmio_uart", &new_mmio_uart_base, sizeof (new_mmio_uart_base)))
 262     {
 263         // mmio_uart=0 will disable mmio_uart support
 264         if (new_mmio_uart_base == 0) {
 265             return 0;
 266         }
 267
 268         mmio_uart_base = new_mmio_uart_base;
 269         return 1;
 270     }
 271
 272     // probe the two possible MMIO_UART2 addresses
 273     mmio_uart_base = MMIO_UART2_BASE;
 274     if (mmio_uart_present()) {
 275       return 1;
 276     }
 277
 278     mmio_uart_base = MMIO_UART2_BASE_LEGACY;
 279     if (mmio_uart_present()) {
 280       return 1;
 281     }
 282
 283     // no mmio uart found
 284     return 0;
 285 }
 286
 287 static void
 288 mmio_uart_set_baud_rate( __unused int unit, __unused uint32_t baud_rate )
 289 {
 290     const unsigned char lcr = MMIO_READ( LCR );
 291     unsigned long       div;
 292
 293     if (baud_rate == 0) baud_rate = 9600;
 294     div = LEGACY_UART_CLOCK / 16 / baud_rate;
 295
 296     MMIO_WRITE( LCR, lcr | UART_LCR_DLAB );
 297     MMIO_WRITE( DLM, (unsigned char)(div >> 8) );
 298     MMIO_WRITE( DLL, (unsigned char) div );
 299     MMIO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
 300 }
 301
 302 static int
 303 mmio_uart_tr0( void )
 304 {
 305     return (MMIO_READ(LSR) & UART_LSR_THRE);
 306 }
 307
 308 static void
 309 mmio_uart_td0( int c )
 310 {
 311     MMIO_WRITE( THR, c );
 312 }
 313
 314 static void
 315 mmio_uart_init( void )
 316 {
 317     /* Disable hardware interrupts */
 318
 319     MMIO_WRITE( MCR, 0 );
 320     MMIO_WRITE( IER, 0 );
 321
 322     /* Disable FIFO's for 16550 devices */
 323
 324     MMIO_WRITE( FCR, 0 );
 325
 326     /* Set for 8-bit, no parity, DLAB bit cleared */
 327
 328     MMIO_WRITE( LCR, UART_LCR_8BITS );
 329
 330     /* Leave baud rate as set by firmware unless serialbaud boot-arg overrides */
 331
 332     if (uart_baud_rate != DEFAULT_UART_BAUD_RATE)
 333     {
 334         gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
 335     }
 336
 337     /* Assert DTR# and RTS# lines (OUT2?) */
 338
 339     MMIO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );
 340
 341     /* Clear any garbage in the input buffer */
 342
 343     MMIO_READ( RBR );
 344
 345     uart_initted = 1;
 346 }
 347
 348 static int
 349 mmio_uart_rr0( void )
 350 {
 351     unsigned char lsr;
 352
 353     lsr = MMIO_READ( LSR );
 354
 355     if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
 356     {
 357         MMIO_READ( RBR ); /* discard */
 358         return 0;
 359     }
 360
 361     return (lsr & UART_LSR_DR);
 362 }
 363
 364 void lpss_uart_enable( boolean_t on_off )
 365 {
 366         unsigned int pmcs_reg;
 367
 368         if (!lpss_uart_supported) {
 369                 return;
 370         }
 371
 372         pmcs_reg = ml_phys_read_byte (PCI_UART2 + 0x84);
 373         if (on_off == FALSE) {
 374                 pmcs_reg |= 0x03;
 375                 lpss_uart_enabled = 0;
 376         } else {
 377                 pmcs_reg &= ~(0x03);
 378         }
 379
 380         ml_phys_write_byte (PCI_UART2 + 0x84, pmcs_reg);
 381         pmcs_reg = ml_phys_read_byte (PCI_UART2 + 0x84);
 382
 383         if (on_off == TRUE) {
 384                 lpss_uart_re_init();
 385                 lpss_uart_enabled = 1;
 386         }
 387 }
 388
 389 static void lpss_uart_re_init( void )
 390 {
 391         uint32_t register_read;
 392
 393         MMIO_WRITE (RST, 0x7);                          /* LPSS UART2 controller out ot reset */
 394         register_read = MMIO_READ (RST);
 395
 396         MMIO_WRITE (LCR, UART_LCR_DLAB);        /* Set DLAB bit to enable reading/writing of DLL, DLH */
 397         register_read = MMIO_READ (LCR);
 398
 399         MMIO_WRITE (DLL, 1);                            /* Divisor Latch Low Register */
 400         register_read = MMIO_READ (DLL);
 401
 402         MMIO_WRITE (DLM, 0);                            /* Divisor Latch High Register */
 403         register_read = MMIO_READ (DLM);
 404
 405         MMIO_WRITE (FCR, 1);                            /* Enable FIFO */
 406         register_read = MMIO_READ (FCR);
 407
 408         MMIO_WRITE (LCR, UART_LCR_8BITS);       /* Set 8 bits, clear DLAB */
 409         register_read = MMIO_READ (LCR);
 410
 411         MMIO_WRITE (MCR, UART_MCR_RTS);         /* Request to send */
 412         register_read = MMIO_READ (MCR);
 413
 414         MMIO_WRITE (CLK, UART_CLK_125M_1);      /* 1.25M Clock speed */
 415         register_read = MMIO_READ (CLK);
 416
 417         MMIO_WRITE (CLK, UART_CLK_125M_2);      /* 1.25M Clock speed */
 418         register_read = MMIO_READ (CLK);
 419 }
 420
 421 static int
 422 mmio_uart_rd0( void )
 423 {
 424     return MMIO_READ( RBR );
 425 }
 426
 427 static struct pe_serial_functions mmio_uart_serial_functions = {
 428     .uart_init = mmio_uart_init,
 429     .uart_set_baud_rate = mmio_uart_set_baud_rate,
 430     .tr0 = mmio_uart_tr0,
 431     .td0 = mmio_uart_td0,
 432     .rr0 = mmio_uart_rr0,
 433     .rd0 = mmio_uart_rd0
 434 };
 435
 436 // =============================================================================
 437 // Generic serial support below
 438 // =============================================================================
 439
 440 int
 441 serial_init( void )
 442 {
 443     unsigned new_uart_baud_rate = 0;
 444
 445     if (PE_parse_boot_argn("serialbaud", &new_uart_baud_rate, sizeof (new_uart_baud_rate)))
 446     {
 447         /* Valid divisor? */
 448         if (!((LEGACY_UART_CLOCK / 16) % new_uart_baud_rate)) {
 449             uart_baud_rate = new_uart_baud_rate;
 450         }
 451     }
 452
 453     if ( mmio_uart_probe() )
 454     {
 455         gPESF = &mmio_uart_serial_functions;
 456         gPESF->uart_init();
 457         lpss_uart_supported = 1;
 458         lpss_uart_enabled = 1;
 459         return 1;
 460     }
 461     else if ( legacy_uart_probe() )
 462     {
 463         gPESF = &legacy_uart_serial_functions;
 464         gPESF->uart_init();
 465         legacy_uart_enabled = 1;
 466         return 1;
 467     }
 468     else
 469     {
 470         return 0;
 471     }
 472
 473 }
 474
 475 static void
 476 uart_putc(char c)
 477 {
 478         if (uart_initted && (legacy_uart_enabled || lpss_uart_enabled)) {
 479         while (!gPESF->tr0());  /* Wait until THR is empty. */
 480         gPESF->td0(c);
 481     }
 482 }
 483
 484 static int
 485 uart_getc(void)
 486 {
 487     if (uart_initted && (legacy_uart_enabled || lpss_uart_enabled)) {
 488         if (!gPESF->rr0())
 489             return -1;
 490         return gPESF->rd0();
 491     }
 492     return -1;
 493 }
 494
 495 void
 496 serial_putc( char c )
 497 {
 498     uart_putc(c);
 499 }
 500
 501 int
 502 serial_getc( void )
 503 {
 504     return uart_getc();
 505 }