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29 #include <i386/cpu_data.h>
30 #include <i386/cpuid.h>
31 #include <i386/lapic.h>
32 #include <i386/proc_reg.h>
33 #include <kern/assert.h> /* static_assert, assert */
34 #include <kern/monotonic.h>
35 #include <x86_64/monotonic.h>
36 #include <sys/errno.h>
37 #include <sys/monotonic.h>
40 * Sanity check the compiler.
44 #define __has_builtin(x) 0
45 #endif /* !defined(__has_builtin) */
46 #if !__has_builtin(__builtin_ia32_rdpmc)
47 #error requires __builtin_ia32_rdpmc builtin
48 #endif /* !__has_builtin(__builtin_ia32_rdpmc) */
50 #pragma mark core counters
52 bool mt_core_supported
= false;
55 * PMC[0-2]_{RD,WR} allow reading and writing the fixed PMCs.
57 * There are separate defines for access type because the read side goes through
58 * the rdpmc instruction, which has a different counter encoding than the msr
61 #define PMC_FIXED_RD(CTR) ((UINT64_C(1) << 30) | (CTR))
62 #define PMC_FIXED_WR(CTR) (MSR_IA32_PERF_FIXED_CTR0 + (CTR))
63 #define PMC0_RD PMC_FIXED_RD(0)
64 #define PMC0_WR PMC_FIXED_WR(0)
65 #define PMC1_RD PMC_FIXED_RD(1)
66 #define PMC1_WR PMC_FIXED_WR(1)
67 #define PMC2_RD PMC_FIXED_RD(2)
68 #define PMC2_WR PMC_FIXED_WR(2)
73 return ¤t_cpu_datap()->cpu_monotonic
;
77 mt_core_snap(unsigned int ctr
)
79 if (!mt_core_supported
) {
85 return __builtin_ia32_rdpmc(PMC0_RD
);
87 return __builtin_ia32_rdpmc(PMC1_RD
);
89 return __builtin_ia32_rdpmc(PMC2_RD
);
91 panic("monotonic: invalid core counter read: %u", ctr
);
97 mt_core_set_snap(unsigned int ctr
, uint64_t count
)
99 if (!mt_core_supported
) {
105 wrmsr64(PMC0_WR
, count
);
108 wrmsr64(PMC1_WR
, count
);
111 wrmsr64(PMC2_WR
, count
);
114 panic("monotonic: invalid core counter write: %u", ctr
);
120 * FIXED_CTR_CTRL controls which rings fixed counters are enabled in and if they
123 * Each fixed counters has 4 bits: [0:1] controls which ring it's enabled in,
124 * [2] counts all hardware threads in each logical core (we don't want this),
125 * and [3] enables PMIs on overflow.
128 #define FIXED_CTR_CTRL 0x38d
131 * Fixed counters are enabled in all rings, so hard-code this register state to
132 * enable in all rings and deliver PMIs.
134 #define FIXED_CTR_CTRL_INIT (0x888 | 0x333)
137 * GLOBAL_CTRL controls which counters are enabled -- the high 32-bits control
138 * the fixed counters and the lower half is for the configurable counters.
141 #define GLOBAL_CTRL 0x38f
144 * Fixed counters are always enabled -- and there are three of them.
146 #define GLOBAL_CTRL_FIXED_EN (((UINT64_C(1) << 3) - 1) << 32)
149 * GLOBAL_STATUS reports the state of counters, like those that have overflowed.
151 #define GLOBAL_STATUS 0x38e
153 #define CTR_MAX ((UINT64_C(1) << 48) - 1)
154 #define CTR_FIX_POS(CTR) ((UINT64_C(1) << (CTR)) << 32)
156 #define GLOBAL_OVF 0x390
159 core_down(cpu_data_t
*cpu
)
161 if (!mt_core_supported
) {
165 assert(ml_get_interrupts_enabled() == FALSE
);
167 wrmsr64(GLOBAL_CTRL
, 0);
168 mt_mtc_update_fixed_counts(&cpu
->cpu_monotonic
, NULL
, NULL
);
172 core_up(cpu_data_t
*cpu
)
176 if (!mt_core_supported
) {
180 assert(ml_get_interrupts_enabled() == FALSE
);
182 mtc
= &cpu
->cpu_monotonic
;
184 for (int i
= 0; i
< MT_CORE_NFIXED
; i
++) {
185 mt_core_set_snap(i
, mtc
->mtc_snaps
[i
]);
187 wrmsr64(FIXED_CTR_CTRL
, FIXED_CTR_CTRL_INIT
);
188 wrmsr64(GLOBAL_CTRL
, GLOBAL_CTRL_FIXED_EN
);
192 mt_cpu_down(cpu_data_t
*cpu
)
198 mt_cpu_up(cpu_data_t
*cpu
)
201 intrs_en
= ml_set_interrupts_enabled(FALSE
);
203 ml_set_interrupts_enabled(intrs_en
);
207 mt_pmi_x86_64(x86_saved_state_t
*state
)
211 bool fixed_ovf
= false;
213 assert(ml_get_interrupts_enabled() == FALSE
);
215 status
= rdmsr64(GLOBAL_STATUS
);
217 (void)atomic_fetch_add_explicit(&mt_pmis
, 1, memory_order_relaxed
);
219 for (int i
= 0; i
< MT_CORE_NFIXED
; i
++) {
220 if (status
& CTR_FIX_POS(i
)) {
224 prior
= CTR_MAX
- mtc
->mtc_snaps
[i
];
225 assert(prior
<= CTR_MAX
);
226 prior
+= 1; /* wrapped */
228 mtc
->mtc_counts
[i
] += prior
;
229 mtc
->mtc_snaps
[i
] = 0;
230 mt_mtc_update_count(mtc
, i
);
234 /* if any of the configurable counters overflowed, tell kpc */
235 if (status
& ((UINT64_C(1) << 4) - 1)) {
236 extern void kpc_pmi_handler(x86_saved_state_t
*state
);
237 kpc_pmi_handler(state
);
247 do_cpuid(0xA, cpuinfo
);
249 if ((cpuinfo
[0] & 0xff) >= 2) {
250 lapic_set_pmi_func((i386_intr_func_t
)mt_pmi_x86_64
);
251 mt_core_supported
= true;
261 #pragma mark common hooks
263 const struct monotonic_dev monotonic_devs
[] = {
265 .mtd_name
= "monotonic/core",
266 .mtd_init
= core_init
271 (sizeof(monotonic_devs
) / sizeof(monotonic_devs
[0])) == MT_NDEVS
,
272 "MT_NDEVS macro should be same as the length of monotonic_devs");