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1 /*
2 * Copyright (c) 2000-2012 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29 #include <i386/machine_routines.h>
30 #include <i386/io_map_entries.h>
31 #include <i386/cpuid.h>
32 #include <i386/fpu.h>
33 #include <mach/processor.h>
34 #include <kern/processor.h>
35 #include <kern/machine.h>
36
37 #include <kern/cpu_number.h>
38 #include <kern/thread.h>
39 #include <kern/thread_call.h>
40 #include <kern/policy_internal.h>
41
42 #include <prng/random.h>
43 #include <i386/machine_cpu.h>
44 #include <i386/lapic.h>
45 #include <i386/bit_routines.h>
46 #include <i386/mp_events.h>
47 #include <i386/pmCPU.h>
48 #include <i386/trap.h>
49 #include <i386/tsc.h>
50 #include <i386/cpu_threads.h>
51 #include <i386/proc_reg.h>
52 #include <mach/vm_param.h>
53 #include <i386/pmap.h>
54 #include <i386/pmap_internal.h>
55 #include <i386/misc_protos.h>
56 #include <kern/timer_queue.h>
57 #if KPC
58 #include <kern/kpc.h>
59 #endif
60 #include <architecture/i386/pio.h>
61 #include <i386/cpu_data.h>
62 #if DEBUG
63 #define DBG(x...) kprintf("DBG: " x)
64 #else
65 #define DBG(x...)
66 #endif
67
68 #if MONOTONIC
69 #include <kern/monotonic.h>
70 #endif /* MONOTONIC */
71
72 extern void wakeup(void *);
73
74 static int max_cpus_initialized = 0;
75
76 uint64_t LockTimeOut;
77 uint64_t TLBTimeOut;
78 uint64_t LockTimeOutTSC;
79 uint32_t LockTimeOutUsec;
80 uint64_t MutexSpin;
81 uint64_t LastDebuggerEntryAllowance;
82 uint64_t delay_spin_threshold;
83
84 extern uint64_t panic_restart_timeout;
85
86 boolean_t virtualized = FALSE;
87
88 decl_simple_lock_data(static, ml_timer_evaluation_slock);
89 uint32_t ml_timer_eager_evaluations;
90 uint64_t ml_timer_eager_evaluation_max;
91 static boolean_t ml_timer_evaluation_in_progress = FALSE;
92
93
94 #define MAX_CPUS_SET 0x1
95 #define MAX_CPUS_WAIT 0x2
96
97 /* IO memory map services */
98
99 /* Map memory map IO space */
100 vm_offset_t ml_io_map(
101 vm_offset_t phys_addr,
102 vm_size_t size)
103 {
104 return(io_map(phys_addr,size,VM_WIMG_IO));
105 }
106
107 /* boot memory allocation */
108 vm_offset_t ml_static_malloc(
109 __unused vm_size_t size)
110 {
111 return((vm_offset_t)NULL);
112 }
113
114
115 void ml_get_bouncepool_info(vm_offset_t *phys_addr, vm_size_t *size)
116 {
117 *phys_addr = 0;
118 *size = 0;
119 }
120
121
122 vm_offset_t
123 ml_static_ptovirt(
124 vm_offset_t paddr)
125 {
126 #if defined(__x86_64__)
127 return (vm_offset_t)(((unsigned long) paddr) | VM_MIN_KERNEL_ADDRESS);
128 #else
129 return (vm_offset_t)((paddr) | LINEAR_KERNEL_ADDRESS);
130 #endif
131 }
132
133
134 /*
135 * Routine: ml_static_mfree
136 * Function:
137 */
138 void
139 ml_static_mfree(
140 vm_offset_t vaddr,
141 vm_size_t size)
142 {
143 addr64_t vaddr_cur;
144 ppnum_t ppn;
145 uint32_t freed_pages = 0;
146 assert(vaddr >= VM_MIN_KERNEL_ADDRESS);
147
148 assert((vaddr & (PAGE_SIZE-1)) == 0); /* must be page aligned */
149
150 for (vaddr_cur = vaddr;
151 vaddr_cur < round_page_64(vaddr+size);
152 vaddr_cur += PAGE_SIZE) {
153 ppn = pmap_find_phys(kernel_pmap, vaddr_cur);
154 if (ppn != (vm_offset_t)NULL) {
155 kernel_pmap->stats.resident_count++;
156 if (kernel_pmap->stats.resident_count >
157 kernel_pmap->stats.resident_max) {
158 kernel_pmap->stats.resident_max =
159 kernel_pmap->stats.resident_count;
160 }
161 pmap_remove(kernel_pmap, vaddr_cur, vaddr_cur+PAGE_SIZE);
162 assert(pmap_valid_page(ppn));
163 if (IS_MANAGED_PAGE(ppn)) {
164 vm_page_create(ppn,(ppn+1));
165 freed_pages++;
166 }
167 }
168 }
169 vm_page_lockspin_queues();
170 vm_page_wire_count -= freed_pages;
171 vm_page_wire_count_initial -= freed_pages;
172 vm_page_unlock_queues();
173
174 #if DEBUG
175 kprintf("ml_static_mfree: Released 0x%x pages at VA %p, size:0x%llx, last ppn: 0x%x\n", freed_pages, (void *)vaddr, (uint64_t)size, ppn);
176 #endif
177 }
178
179
180 /* virtual to physical on wired pages */
181 vm_offset_t ml_vtophys(
182 vm_offset_t vaddr)
183 {
184 return (vm_offset_t)kvtophys(vaddr);
185 }
186
187 /*
188 * Routine: ml_nofault_copy
189 * Function: Perform a physical mode copy if the source and
190 * destination have valid translations in the kernel pmap.
191 * If translations are present, they are assumed to
192 * be wired; i.e. no attempt is made to guarantee that the
193 * translations obtained remained valid for
194 * the duration of the copy process.
195 */
196
197 vm_size_t ml_nofault_copy(
198 vm_offset_t virtsrc, vm_offset_t virtdst, vm_size_t size)
199 {
200 addr64_t cur_phys_dst, cur_phys_src;
201 uint32_t count, nbytes = 0;
202
203 while (size > 0) {
204 if (!(cur_phys_src = kvtophys(virtsrc)))
205 break;
206 if (!(cur_phys_dst = kvtophys(virtdst)))
207 break;
208 if (!pmap_valid_page(i386_btop(cur_phys_dst)) || !pmap_valid_page(i386_btop(cur_phys_src)))
209 break;
210 count = (uint32_t)(PAGE_SIZE - (cur_phys_src & PAGE_MASK));
211 if (count > (PAGE_SIZE - (cur_phys_dst & PAGE_MASK)))
212 count = (uint32_t)(PAGE_SIZE - (cur_phys_dst & PAGE_MASK));
213 if (count > size)
214 count = (uint32_t)size;
215
216 bcopy_phys(cur_phys_src, cur_phys_dst, count);
217
218 nbytes += count;
219 virtsrc += count;
220 virtdst += count;
221 size -= count;
222 }
223
224 return nbytes;
225 }
226
227 /*
228 * Routine: ml_validate_nofault
229 * Function: Validate that ths address range has a valid translations
230 * in the kernel pmap. If translations are present, they are
231 * assumed to be wired; i.e. no attempt is made to guarantee
232 * that the translation persist after the check.
233 * Returns: TRUE if the range is mapped and will not cause a fault,
234 * FALSE otherwise.
235 */
236
237 boolean_t ml_validate_nofault(
238 vm_offset_t virtsrc, vm_size_t size)
239 {
240 addr64_t cur_phys_src;
241 uint32_t count;
242
243 while (size > 0) {
244 if (!(cur_phys_src = kvtophys(virtsrc)))
245 return FALSE;
246 if (!pmap_valid_page(i386_btop(cur_phys_src)))
247 return FALSE;
248 count = (uint32_t)(PAGE_SIZE - (cur_phys_src & PAGE_MASK));
249 if (count > size)
250 count = (uint32_t)size;
251
252 virtsrc += count;
253 size -= count;
254 }
255
256 return TRUE;
257 }
258
259 /* Interrupt handling */
260
261 /* Initialize Interrupts */
262 void ml_init_interrupt(void)
263 {
264 (void) ml_set_interrupts_enabled(TRUE);
265 }
266
267
268 /* Get Interrupts Enabled */
269 boolean_t ml_get_interrupts_enabled(void)
270 {
271 unsigned long flags;
272
273 __asm__ volatile("pushf; pop %0" : "=r" (flags));
274 return (flags & EFL_IF) != 0;
275 }
276
277 /* Set Interrupts Enabled */
278 boolean_t ml_set_interrupts_enabled(boolean_t enable)
279 {
280 unsigned long flags;
281 boolean_t istate;
282
283 __asm__ volatile("pushf; pop %0" : "=r" (flags));
284
285 assert(get_interrupt_level() ? (enable == FALSE) : TRUE);
286
287 istate = ((flags & EFL_IF) != 0);
288
289 if (enable) {
290 __asm__ volatile("sti;nop");
291
292 if ((get_preemption_level() == 0) && (*ast_pending() & AST_URGENT))
293 __asm__ volatile ("int %0" :: "N" (T_PREEMPT));
294 }
295 else {
296 if (istate)
297 __asm__ volatile("cli");
298 }
299
300 return istate;
301 }
302
303 /* Check if running at interrupt context */
304 boolean_t ml_at_interrupt_context(void)
305 {
306 return get_interrupt_level() != 0;
307 }
308
309 void ml_get_power_state(boolean_t *icp, boolean_t *pidlep) {
310 *icp = (get_interrupt_level() != 0);
311 /* These will be technically inaccurate for interrupts that occur
312 * successively within a single "idle exit" event, but shouldn't
313 * matter statistically.
314 */
315 *pidlep = (current_cpu_datap()->lcpu.package->num_idle == topoParms.nLThreadsPerPackage);
316 }
317
318 /* Generate a fake interrupt */
319 void ml_cause_interrupt(void)
320 {
321 panic("ml_cause_interrupt not defined yet on Intel");
322 }
323
324 /*
325 * TODO: transition users of this to kernel_thread_start_priority
326 * ml_thread_policy is an unsupported KPI
327 */
328 void ml_thread_policy(
329 thread_t thread,
330 __unused unsigned policy_id,
331 unsigned policy_info)
332 {
333 if (policy_info & MACHINE_NETWORK_WORKLOOP) {
334 thread_precedence_policy_data_t info;
335 __assert_only kern_return_t kret;
336
337 info.importance = 1;
338
339 kret = thread_policy_set_internal(thread, THREAD_PRECEDENCE_POLICY,
340 (thread_policy_t)&info,
341 THREAD_PRECEDENCE_POLICY_COUNT);
342 assert(kret == KERN_SUCCESS);
343 }
344 }
345
346 /* Initialize Interrupts */
347 void ml_install_interrupt_handler(
348 void *nub,
349 int source,
350 void *target,
351 IOInterruptHandler handler,
352 void *refCon)
353 {
354 boolean_t current_state;
355
356 current_state = ml_set_interrupts_enabled(FALSE);
357
358 PE_install_interrupt_handler(nub, source, target,
359 (IOInterruptHandler) handler, refCon);
360
361 (void) ml_set_interrupts_enabled(current_state);
362
363 initialize_screen(NULL, kPEAcquireScreen);
364 }
365
366
367 void
368 machine_signal_idle(
369 processor_t processor)
370 {
371 cpu_interrupt(processor->cpu_id);
372 }
373
374 void
375 machine_signal_idle_deferred(
376 __unused processor_t processor)
377 {
378 panic("Unimplemented");
379 }
380
381 void
382 machine_signal_idle_cancel(
383 __unused processor_t processor)
384 {
385 panic("Unimplemented");
386 }
387
388 static kern_return_t
389 register_cpu(
390 uint32_t lapic_id,
391 processor_t *processor_out,
392 boolean_t boot_cpu )
393 {
394 int target_cpu;
395 cpu_data_t *this_cpu_datap;
396
397 this_cpu_datap = cpu_data_alloc(boot_cpu);
398 if (this_cpu_datap == NULL) {
399 return KERN_FAILURE;
400 }
401 target_cpu = this_cpu_datap->cpu_number;
402 assert((boot_cpu && (target_cpu == 0)) ||
403 (!boot_cpu && (target_cpu != 0)));
404
405 lapic_cpu_map(lapic_id, target_cpu);
406
407 /* The cpu_id is not known at registration phase. Just do
408 * lapic_id for now
409 */
410 this_cpu_datap->cpu_phys_number = lapic_id;
411
412 this_cpu_datap->cpu_console_buf = console_cpu_alloc(boot_cpu);
413 if (this_cpu_datap->cpu_console_buf == NULL)
414 goto failed;
415
416 #if KPC
417 if (kpc_register_cpu(this_cpu_datap) != TRUE)
418 goto failed;
419 #endif
420
421 if (!boot_cpu) {
422 cpu_thread_alloc(this_cpu_datap->cpu_number);
423 if (this_cpu_datap->lcpu.core == NULL)
424 goto failed;
425
426 #if NCOPY_WINDOWS > 0
427 this_cpu_datap->cpu_pmap = pmap_cpu_alloc(boot_cpu);
428 if (this_cpu_datap->cpu_pmap == NULL)
429 goto failed;
430 #endif
431
432 this_cpu_datap->cpu_processor = cpu_processor_alloc(boot_cpu);
433 if (this_cpu_datap->cpu_processor == NULL)
434 goto failed;
435 /*
436 * processor_init() deferred to topology start
437 * because "slot numbers" a.k.a. logical processor numbers
438 * are not yet finalized.
439 */
440 }
441
442 *processor_out = this_cpu_datap->cpu_processor;
443
444 return KERN_SUCCESS;
445
446 failed:
447 cpu_processor_free(this_cpu_datap->cpu_processor);
448 #if NCOPY_WINDOWS > 0
449 pmap_cpu_free(this_cpu_datap->cpu_pmap);
450 #endif
451 console_cpu_free(this_cpu_datap->cpu_console_buf);
452 #if KPC
453 kpc_unregister_cpu(this_cpu_datap);
454 #endif /* KPC */
455
456 return KERN_FAILURE;
457 }
458
459
460 kern_return_t
461 ml_processor_register(
462 cpu_id_t cpu_id,
463 uint32_t lapic_id,
464 processor_t *processor_out,
465 boolean_t boot_cpu,
466 boolean_t start )
467 {
468 static boolean_t done_topo_sort = FALSE;
469 static uint32_t num_registered = 0;
470
471 /* Register all CPUs first, and track max */
472 if( start == FALSE )
473 {
474 num_registered++;
475
476 DBG( "registering CPU lapic id %d\n", lapic_id );
477
478 return register_cpu( lapic_id, processor_out, boot_cpu );
479 }
480
481 /* Sort by topology before we start anything */
482 if( !done_topo_sort )
483 {
484 DBG( "about to start CPUs. %d registered\n", num_registered );
485
486 cpu_topology_sort( num_registered );
487 done_topo_sort = TRUE;
488 }
489
490 /* Assign the cpu ID */
491 uint32_t cpunum = -1;
492 cpu_data_t *this_cpu_datap = NULL;
493
494 /* find cpu num and pointer */
495 cpunum = ml_get_cpuid( lapic_id );
496
497 if( cpunum == 0xFFFFFFFF ) /* never heard of it? */
498 panic( "trying to start invalid/unregistered CPU %d\n", lapic_id );
499
500 this_cpu_datap = cpu_datap(cpunum);
501
502 /* fix the CPU id */
503 this_cpu_datap->cpu_id = cpu_id;
504
505 /* allocate and initialize other per-cpu structures */
506 if (!boot_cpu) {
507 mp_cpus_call_cpu_init(cpunum);
508 prng_cpu_init(cpunum);
509 }
510
511 /* output arg */
512 *processor_out = this_cpu_datap->cpu_processor;
513
514 /* OK, try and start this CPU */
515 return cpu_topology_start_cpu( cpunum );
516 }
517
518
519 void
520 ml_cpu_get_info(ml_cpu_info_t *cpu_infop)
521 {
522 boolean_t os_supports_sse;
523 i386_cpu_info_t *cpuid_infop;
524
525 if (cpu_infop == NULL)
526 return;
527
528 /*
529 * Are we supporting MMX/SSE/SSE2/SSE3?
530 * As distinct from whether the cpu has these capabilities.
531 */
532 os_supports_sse = !!(get_cr4() & CR4_OSXMM);
533
534 if (ml_fpu_avx_enabled())
535 cpu_infop->vector_unit = 9;
536 else if ((cpuid_features() & CPUID_FEATURE_SSE4_2) && os_supports_sse)
537 cpu_infop->vector_unit = 8;
538 else if ((cpuid_features() & CPUID_FEATURE_SSE4_1) && os_supports_sse)
539 cpu_infop->vector_unit = 7;
540 else if ((cpuid_features() & CPUID_FEATURE_SSSE3) && os_supports_sse)
541 cpu_infop->vector_unit = 6;
542 else if ((cpuid_features() & CPUID_FEATURE_SSE3) && os_supports_sse)
543 cpu_infop->vector_unit = 5;
544 else if ((cpuid_features() & CPUID_FEATURE_SSE2) && os_supports_sse)
545 cpu_infop->vector_unit = 4;
546 else if ((cpuid_features() & CPUID_FEATURE_SSE) && os_supports_sse)
547 cpu_infop->vector_unit = 3;
548 else if (cpuid_features() & CPUID_FEATURE_MMX)
549 cpu_infop->vector_unit = 2;
550 else
551 cpu_infop->vector_unit = 0;
552
553 cpuid_infop = cpuid_info();
554
555 cpu_infop->cache_line_size = cpuid_infop->cache_linesize;
556
557 cpu_infop->l1_icache_size = cpuid_infop->cache_size[L1I];
558 cpu_infop->l1_dcache_size = cpuid_infop->cache_size[L1D];
559
560 if (cpuid_infop->cache_size[L2U] > 0) {
561 cpu_infop->l2_settings = 1;
562 cpu_infop->l2_cache_size = cpuid_infop->cache_size[L2U];
563 } else {
564 cpu_infop->l2_settings = 0;
565 cpu_infop->l2_cache_size = 0xFFFFFFFF;
566 }
567
568 if (cpuid_infop->cache_size[L3U] > 0) {
569 cpu_infop->l3_settings = 1;
570 cpu_infop->l3_cache_size = cpuid_infop->cache_size[L3U];
571 } else {
572 cpu_infop->l3_settings = 0;
573 cpu_infop->l3_cache_size = 0xFFFFFFFF;
574 }
575 }
576
577 void
578 ml_init_max_cpus(unsigned long max_cpus)
579 {
580 boolean_t current_state;
581
582 current_state = ml_set_interrupts_enabled(FALSE);
583 if (max_cpus_initialized != MAX_CPUS_SET) {
584 if (max_cpus > 0 && max_cpus <= MAX_CPUS) {
585 /*
586 * Note: max_cpus is the number of enabled processors
587 * that ACPI found; max_ncpus is the maximum number
588 * that the kernel supports or that the "cpus="
589 * boot-arg has set. Here we take int minimum.
590 */
591 machine_info.max_cpus = (integer_t)MIN(max_cpus, max_ncpus);
592 }
593 if (max_cpus_initialized == MAX_CPUS_WAIT)
594 wakeup((event_t)&max_cpus_initialized);
595 max_cpus_initialized = MAX_CPUS_SET;
596 }
597 (void) ml_set_interrupts_enabled(current_state);
598 }
599
600 int
601 ml_get_max_cpus(void)
602 {
603 boolean_t current_state;
604
605 current_state = ml_set_interrupts_enabled(FALSE);
606 if (max_cpus_initialized != MAX_CPUS_SET) {
607 max_cpus_initialized = MAX_CPUS_WAIT;
608 assert_wait((event_t)&max_cpus_initialized, THREAD_UNINT);
609 (void)thread_block(THREAD_CONTINUE_NULL);
610 }
611 (void) ml_set_interrupts_enabled(current_state);
612 return(machine_info.max_cpus);
613 }
614
615 boolean_t
616 ml_wants_panic_trap_to_debugger(void)
617 {
618 return FALSE;
619 }
620
621 void
622 ml_panic_trap_to_debugger(__unused const char *panic_format_str,
623 __unused va_list *panic_args,
624 __unused unsigned int reason,
625 __unused void *ctx,
626 __unused uint64_t panic_options_mask,
627 __unused unsigned long panic_caller)
628 {
629 return;
630 }
631
632 /*
633 * Routine: ml_init_lock_timeout
634 * Function:
635 */
636 void
637 ml_init_lock_timeout(void)
638 {
639 uint64_t abstime;
640 uint32_t mtxspin;
641 #if DEVELOPMENT || DEBUG
642 uint64_t default_timeout_ns = NSEC_PER_SEC>>2;
643 #else
644 uint64_t default_timeout_ns = NSEC_PER_SEC>>1;
645 #endif
646 uint32_t slto;
647 uint32_t prt;
648
649 if (PE_parse_boot_argn("slto_us", &slto, sizeof (slto)))
650 default_timeout_ns = slto * NSEC_PER_USEC;
651
652 /*
653 * LockTimeOut is absolutetime, LockTimeOutTSC is in TSC ticks,
654 * and LockTimeOutUsec is in microseconds and it's 32-bits.
655 */
656 LockTimeOutUsec = (uint32_t) (default_timeout_ns / NSEC_PER_USEC);
657 nanoseconds_to_absolutetime(default_timeout_ns, &abstime);
658 LockTimeOut = abstime;
659 LockTimeOutTSC = tmrCvt(abstime, tscFCvtn2t);
660
661 /*
662 * TLBTimeOut dictates the TLB flush timeout period. It defaults to
663 * LockTimeOut but can be overriden separately. In particular, a
664 * zero value inhibits the timeout-panic and cuts a trace evnt instead
665 * - see pmap_flush_tlbs().
666 */
667 if (PE_parse_boot_argn("tlbto_us", &slto, sizeof (slto))) {
668 default_timeout_ns = slto * NSEC_PER_USEC;
669 nanoseconds_to_absolutetime(default_timeout_ns, &abstime);
670 TLBTimeOut = (uint32_t) abstime;
671 } else {
672 TLBTimeOut = LockTimeOut;
673 }
674
675 #if DEVELOPMENT || DEBUG
676 reportphyreaddelayabs = LockTimeOut >> 1;
677 #endif
678 if (PE_parse_boot_argn("phyreadmaxus", &slto, sizeof (slto))) {
679 default_timeout_ns = slto * NSEC_PER_USEC;
680 nanoseconds_to_absolutetime(default_timeout_ns, &abstime);
681 reportphyreaddelayabs = abstime;
682 }
683
684 if (PE_parse_boot_argn("mtxspin", &mtxspin, sizeof (mtxspin))) {
685 if (mtxspin > USEC_PER_SEC>>4)
686 mtxspin = USEC_PER_SEC>>4;
687 nanoseconds_to_absolutetime(mtxspin*NSEC_PER_USEC, &abstime);
688 } else {
689 nanoseconds_to_absolutetime(10*NSEC_PER_USEC, &abstime);
690 }
691 MutexSpin = (unsigned int)abstime;
692
693 nanoseconds_to_absolutetime(4ULL * NSEC_PER_SEC, &LastDebuggerEntryAllowance);
694 if (PE_parse_boot_argn("panic_restart_timeout", &prt, sizeof (prt)))
695 nanoseconds_to_absolutetime(prt * NSEC_PER_SEC, &panic_restart_timeout);
696
697 virtualized = ((cpuid_features() & CPUID_FEATURE_VMM) != 0);
698 if (virtualized) {
699 int vti;
700
701 if (!PE_parse_boot_argn("vti", &vti, sizeof (vti)))
702 vti = 6;
703 printf("Timeouts adjusted for virtualization (<<%d)\n", vti);
704 kprintf("Timeouts adjusted for virtualization (<<%d):\n", vti);
705 #define VIRTUAL_TIMEOUT_INFLATE64(_timeout) \
706 MACRO_BEGIN \
707 kprintf("%24s: 0x%016llx ", #_timeout, _timeout); \
708 _timeout <<= vti; \
709 kprintf("-> 0x%016llx\n", _timeout); \
710 MACRO_END
711 #define VIRTUAL_TIMEOUT_INFLATE32(_timeout) \
712 MACRO_BEGIN \
713 kprintf("%24s: 0x%08x ", #_timeout, _timeout); \
714 if ((_timeout <<vti) >> vti == _timeout) \
715 _timeout <<= vti; \
716 else \
717 _timeout = ~0; /* cap rather than overflow */ \
718 kprintf("-> 0x%08x\n", _timeout); \
719 MACRO_END
720 VIRTUAL_TIMEOUT_INFLATE32(LockTimeOutUsec);
721 VIRTUAL_TIMEOUT_INFLATE64(LockTimeOut);
722 VIRTUAL_TIMEOUT_INFLATE64(LockTimeOutTSC);
723 VIRTUAL_TIMEOUT_INFLATE64(TLBTimeOut);
724 VIRTUAL_TIMEOUT_INFLATE64(MutexSpin);
725 VIRTUAL_TIMEOUT_INFLATE64(reportphyreaddelayabs);
726 }
727
728 interrupt_latency_tracker_setup();
729 simple_lock_init(&ml_timer_evaluation_slock, 0);
730 }
731
732 /*
733 * Threshold above which we should attempt to block
734 * instead of spinning for clock_delay_until().
735 */
736
737 void
738 ml_init_delay_spin_threshold(int threshold_us)
739 {
740 nanoseconds_to_absolutetime(threshold_us * NSEC_PER_USEC, &delay_spin_threshold);
741 }
742
743 boolean_t
744 ml_delay_should_spin(uint64_t interval)
745 {
746 return (interval < delay_spin_threshold) ? TRUE : FALSE;
747 }
748
749 /*
750 * This is called from the machine-independent layer
751 * to perform machine-dependent info updates. Defer to cpu_thread_init().
752 */
753 void
754 ml_cpu_up(void)
755 {
756 return;
757 }
758
759 /*
760 * This is called from the machine-independent layer
761 * to perform machine-dependent info updates.
762 */
763 void
764 ml_cpu_down(void)
765 {
766 i386_deactivate_cpu();
767
768 return;
769 }
770
771 /*
772 * The following are required for parts of the kernel
773 * that cannot resolve these functions as inlines:
774 */
775 extern thread_t current_act(void);
776 thread_t
777 current_act(void)
778 {
779 return(current_thread_fast());
780 }
781
782 #undef current_thread
783 extern thread_t current_thread(void);
784 thread_t
785 current_thread(void)
786 {
787 return(current_thread_fast());
788 }
789
790
791 boolean_t ml_is64bit(void) {
792
793 return (cpu_mode_is64bit());
794 }
795
796
797 boolean_t ml_thread_is64bit(thread_t thread) {
798
799 return (thread_is_64bit(thread));
800 }
801
802
803 boolean_t ml_state_is64bit(void *saved_state) {
804
805 return is_saved_state64(saved_state);
806 }
807
808 void ml_cpu_set_ldt(int selector)
809 {
810 /*
811 * Avoid loading the LDT
812 * if we're setting the KERNEL LDT and it's already set.
813 */
814 if (selector == KERNEL_LDT &&
815 current_cpu_datap()->cpu_ldt == KERNEL_LDT)
816 return;
817
818 lldt(selector);
819 current_cpu_datap()->cpu_ldt = selector;
820 }
821
822 void ml_fp_setvalid(boolean_t value)
823 {
824 fp_setvalid(value);
825 }
826
827 uint64_t ml_cpu_int_event_time(void)
828 {
829 return current_cpu_datap()->cpu_int_event_time;
830 }
831
832 vm_offset_t ml_stack_remaining(void)
833 {
834 uintptr_t local = (uintptr_t) &local;
835
836 if (ml_at_interrupt_context() != 0) {
837 return (local - (current_cpu_datap()->cpu_int_stack_top - INTSTACK_SIZE));
838 } else {
839 return (local - current_thread()->kernel_stack);
840 }
841 }
842
843 #if KASAN
844 vm_offset_t ml_stack_base(void);
845 vm_size_t ml_stack_size(void);
846
847 vm_offset_t
848 ml_stack_base(void)
849 {
850 if (ml_at_interrupt_context()) {
851 return current_cpu_datap()->cpu_int_stack_top - INTSTACK_SIZE;
852 } else {
853 return current_thread()->kernel_stack;
854 }
855 }
856
857 vm_size_t
858 ml_stack_size(void)
859 {
860 if (ml_at_interrupt_context()) {
861 return INTSTACK_SIZE;
862 } else {
863 return kernel_stack_size;
864 }
865 }
866 #endif
867
868 void
869 kernel_preempt_check(void)
870 {
871 boolean_t intr;
872 unsigned long flags;
873
874 assert(get_preemption_level() == 0);
875
876 __asm__ volatile("pushf; pop %0" : "=r" (flags));
877
878 intr = ((flags & EFL_IF) != 0);
879
880 if ((*ast_pending() & AST_URGENT) && intr == TRUE) {
881 /*
882 * can handle interrupts and preemptions
883 * at this point
884 */
885
886 /*
887 * now cause the PRE-EMPTION trap
888 */
889 __asm__ volatile ("int %0" :: "N" (T_PREEMPT));
890 }
891 }
892
893 boolean_t machine_timeout_suspended(void) {
894 return (pmap_tlb_flush_timeout || spinlock_timed_out || panic_active() || mp_recent_debugger_activity() || ml_recent_wake());
895 }
896
897 /* Eagerly evaluate all pending timer and thread callouts
898 */
899 void ml_timer_evaluate(void) {
900 KERNEL_DEBUG_CONSTANT(DECR_TIMER_RESCAN|DBG_FUNC_START, 0, 0, 0, 0, 0);
901
902 uint64_t te_end, te_start = mach_absolute_time();
903 simple_lock(&ml_timer_evaluation_slock);
904 ml_timer_evaluation_in_progress = TRUE;
905 thread_call_delayed_timer_rescan_all();
906 mp_cpus_call(CPUMASK_ALL, ASYNC, timer_queue_expire_rescan, NULL);
907 ml_timer_evaluation_in_progress = FALSE;
908 ml_timer_eager_evaluations++;
909 te_end = mach_absolute_time();
910 ml_timer_eager_evaluation_max = MAX(ml_timer_eager_evaluation_max, (te_end - te_start));
911 simple_unlock(&ml_timer_evaluation_slock);
912
913 KERNEL_DEBUG_CONSTANT(DECR_TIMER_RESCAN|DBG_FUNC_END, 0, 0, 0, 0, 0);
914 }
915
916 boolean_t
917 ml_timer_forced_evaluation(void) {
918 return ml_timer_evaluation_in_progress;
919 }
920
921 /* 32-bit right-rotate n bits */
922 static inline uint32_t ror32(uint32_t val, const unsigned int n)
923 {
924 __asm__ volatile("rorl %%cl,%0" : "=r" (val) : "0" (val), "c" (n));
925 return val;
926 }
927
928 void
929 ml_entropy_collect(void)
930 {
931 uint32_t tsc_lo, tsc_hi;
932 uint32_t *ep;
933
934 assert(cpu_number() == master_cpu);
935
936 /* update buffer pointer cyclically */
937 if (EntropyData.index_ptr - EntropyData.buffer == ENTROPY_BUFFER_SIZE)
938 ep = EntropyData.index_ptr = EntropyData.buffer;
939 else
940 ep = EntropyData.index_ptr++;
941
942 rdtsc_nofence(tsc_lo, tsc_hi);
943 *ep = ror32(*ep, 9) ^ tsc_lo;
944 }
945
946 uint64_t
947 ml_energy_stat(__unused thread_t t) {
948 return 0;
949 }
950
951 void
952 ml_gpu_stat_update(uint64_t gpu_ns_delta) {
953 current_thread()->machine.thread_gpu_ns += gpu_ns_delta;
954 }
955
956 uint64_t
957 ml_gpu_stat(thread_t t) {
958 return t->machine.thread_gpu_ns;
959 }
960
961 int plctrace_enabled = 0;
962
963 void _disable_preemption(void) {
964 disable_preemption_internal();
965 }
966
967 void _enable_preemption(void) {
968 enable_preemption_internal();
969 }
970
971 void plctrace_disable(void) {
972 plctrace_enabled = 0;
973 }
974
975 static boolean_t ml_quiescing;
976
977 void ml_set_is_quiescing(boolean_t quiescing)
978 {
979 assert(FALSE == ml_get_interrupts_enabled());
980 ml_quiescing = quiescing;
981 }
982
983 boolean_t ml_is_quiescing(void)
984 {
985 assert(FALSE == ml_get_interrupts_enabled());
986 return (ml_quiescing);
987 }
988
989 uint64_t ml_get_booter_memory_size(void)
990 {
991 return (0);
992 }