2 * Copyright (c) 2000-2012 Apple Inc. All rights reserved.
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
29 #include <i386/machine_routines.h>
30 #include <i386/io_map_entries.h>
31 #include <i386/cpuid.h>
33 #include <mach/processor.h>
34 #include <kern/processor.h>
35 #include <kern/machine.h>
37 #include <kern/cpu_number.h>
38 #include <kern/thread.h>
39 #include <kern/thread_call.h>
40 #include <kern/policy_internal.h>
42 #include <prng/random.h>
43 #include <i386/machine_cpu.h>
44 #include <i386/lapic.h>
45 #include <i386/bit_routines.h>
46 #include <i386/mp_events.h>
47 #include <i386/pmCPU.h>
48 #include <i386/trap.h>
50 #include <i386/cpu_threads.h>
51 #include <i386/proc_reg.h>
52 #include <mach/vm_param.h>
53 #include <i386/pmap.h>
54 #include <i386/pmap_internal.h>
55 #include <i386/misc_protos.h>
56 #include <kern/timer_queue.h>
60 #include <architecture/i386/pio.h>
61 #include <i386/cpu_data.h>
63 #define DBG(x...) kprintf("DBG: " x)
69 #include <kern/monotonic.h>
70 #endif /* MONOTONIC */
72 extern void wakeup(void *);
74 static int max_cpus_initialized
= 0;
78 uint64_t LockTimeOutTSC
;
79 uint32_t LockTimeOutUsec
;
81 uint64_t LastDebuggerEntryAllowance
;
82 uint64_t delay_spin_threshold
;
84 extern uint64_t panic_restart_timeout
;
86 boolean_t virtualized
= FALSE
;
88 decl_simple_lock_data(static, ml_timer_evaluation_slock
);
89 uint32_t ml_timer_eager_evaluations
;
90 uint64_t ml_timer_eager_evaluation_max
;
91 static boolean_t ml_timer_evaluation_in_progress
= FALSE
;
94 #define MAX_CPUS_SET 0x1
95 #define MAX_CPUS_WAIT 0x2
97 /* IO memory map services */
99 /* Map memory map IO space */
100 vm_offset_t
ml_io_map(
101 vm_offset_t phys_addr
,
104 return(io_map(phys_addr
,size
,VM_WIMG_IO
));
107 /* boot memory allocation */
108 vm_offset_t
ml_static_malloc(
109 __unused vm_size_t size
)
111 return((vm_offset_t
)NULL
);
115 void ml_get_bouncepool_info(vm_offset_t
*phys_addr
, vm_size_t
*size
)
126 #if defined(__x86_64__)
127 return (vm_offset_t
)(((unsigned long) paddr
) | VM_MIN_KERNEL_ADDRESS
);
129 return (vm_offset_t
)((paddr
) | LINEAR_KERNEL_ADDRESS
);
135 * Routine: ml_static_mfree
145 uint32_t freed_pages
= 0;
146 assert(vaddr
>= VM_MIN_KERNEL_ADDRESS
);
148 assert((vaddr
& (PAGE_SIZE
-1)) == 0); /* must be page aligned */
150 for (vaddr_cur
= vaddr
;
151 vaddr_cur
< round_page_64(vaddr
+size
);
152 vaddr_cur
+= PAGE_SIZE
) {
153 ppn
= pmap_find_phys(kernel_pmap
, vaddr_cur
);
154 if (ppn
!= (vm_offset_t
)NULL
) {
155 kernel_pmap
->stats
.resident_count
++;
156 if (kernel_pmap
->stats
.resident_count
>
157 kernel_pmap
->stats
.resident_max
) {
158 kernel_pmap
->stats
.resident_max
=
159 kernel_pmap
->stats
.resident_count
;
161 pmap_remove(kernel_pmap
, vaddr_cur
, vaddr_cur
+PAGE_SIZE
);
162 assert(pmap_valid_page(ppn
));
163 if (IS_MANAGED_PAGE(ppn
)) {
164 vm_page_create(ppn
,(ppn
+1));
169 vm_page_lockspin_queues();
170 vm_page_wire_count
-= freed_pages
;
171 vm_page_wire_count_initial
-= freed_pages
;
172 vm_page_unlock_queues();
175 kprintf("ml_static_mfree: Released 0x%x pages at VA %p, size:0x%llx, last ppn: 0x%x\n", freed_pages
, (void *)vaddr
, (uint64_t)size
, ppn
);
180 /* virtual to physical on wired pages */
181 vm_offset_t
ml_vtophys(
184 return (vm_offset_t
)kvtophys(vaddr
);
188 * Routine: ml_nofault_copy
189 * Function: Perform a physical mode copy if the source and
190 * destination have valid translations in the kernel pmap.
191 * If translations are present, they are assumed to
192 * be wired; i.e. no attempt is made to guarantee that the
193 * translations obtained remained valid for
194 * the duration of the copy process.
197 vm_size_t
ml_nofault_copy(
198 vm_offset_t virtsrc
, vm_offset_t virtdst
, vm_size_t size
)
200 addr64_t cur_phys_dst
, cur_phys_src
;
201 uint32_t count
, nbytes
= 0;
204 if (!(cur_phys_src
= kvtophys(virtsrc
)))
206 if (!(cur_phys_dst
= kvtophys(virtdst
)))
208 if (!pmap_valid_page(i386_btop(cur_phys_dst
)) || !pmap_valid_page(i386_btop(cur_phys_src
)))
210 count
= (uint32_t)(PAGE_SIZE
- (cur_phys_src
& PAGE_MASK
));
211 if (count
> (PAGE_SIZE
- (cur_phys_dst
& PAGE_MASK
)))
212 count
= (uint32_t)(PAGE_SIZE
- (cur_phys_dst
& PAGE_MASK
));
214 count
= (uint32_t)size
;
216 bcopy_phys(cur_phys_src
, cur_phys_dst
, count
);
228 * Routine: ml_validate_nofault
229 * Function: Validate that ths address range has a valid translations
230 * in the kernel pmap. If translations are present, they are
231 * assumed to be wired; i.e. no attempt is made to guarantee
232 * that the translation persist after the check.
233 * Returns: TRUE if the range is mapped and will not cause a fault,
237 boolean_t
ml_validate_nofault(
238 vm_offset_t virtsrc
, vm_size_t size
)
240 addr64_t cur_phys_src
;
244 if (!(cur_phys_src
= kvtophys(virtsrc
)))
246 if (!pmap_valid_page(i386_btop(cur_phys_src
)))
248 count
= (uint32_t)(PAGE_SIZE
- (cur_phys_src
& PAGE_MASK
));
250 count
= (uint32_t)size
;
259 /* Interrupt handling */
261 /* Initialize Interrupts */
262 void ml_init_interrupt(void)
264 (void) ml_set_interrupts_enabled(TRUE
);
268 /* Get Interrupts Enabled */
269 boolean_t
ml_get_interrupts_enabled(void)
273 __asm__
volatile("pushf; pop %0" : "=r" (flags
));
274 return (flags
& EFL_IF
) != 0;
277 /* Set Interrupts Enabled */
278 boolean_t
ml_set_interrupts_enabled(boolean_t enable
)
283 __asm__
volatile("pushf; pop %0" : "=r" (flags
));
285 assert(get_interrupt_level() ? (enable
== FALSE
) : TRUE
);
287 istate
= ((flags
& EFL_IF
) != 0);
290 __asm__
volatile("sti;nop");
292 if ((get_preemption_level() == 0) && (*ast_pending() & AST_URGENT
))
293 __asm__
volatile ("int %0" :: "N" (T_PREEMPT
));
297 __asm__
volatile("cli");
303 /* Check if running at interrupt context */
304 boolean_t
ml_at_interrupt_context(void)
306 return get_interrupt_level() != 0;
309 void ml_get_power_state(boolean_t
*icp
, boolean_t
*pidlep
) {
310 *icp
= (get_interrupt_level() != 0);
311 /* These will be technically inaccurate for interrupts that occur
312 * successively within a single "idle exit" event, but shouldn't
313 * matter statistically.
315 *pidlep
= (current_cpu_datap()->lcpu
.package
->num_idle
== topoParms
.nLThreadsPerPackage
);
318 /* Generate a fake interrupt */
319 void ml_cause_interrupt(void)
321 panic("ml_cause_interrupt not defined yet on Intel");
325 * TODO: transition users of this to kernel_thread_start_priority
326 * ml_thread_policy is an unsupported KPI
328 void ml_thread_policy(
330 __unused
unsigned policy_id
,
331 unsigned policy_info
)
333 if (policy_info
& MACHINE_NETWORK_WORKLOOP
) {
334 thread_precedence_policy_data_t info
;
335 __assert_only kern_return_t kret
;
339 kret
= thread_policy_set_internal(thread
, THREAD_PRECEDENCE_POLICY
,
340 (thread_policy_t
)&info
,
341 THREAD_PRECEDENCE_POLICY_COUNT
);
342 assert(kret
== KERN_SUCCESS
);
346 /* Initialize Interrupts */
347 void ml_install_interrupt_handler(
351 IOInterruptHandler handler
,
354 boolean_t current_state
;
356 current_state
= ml_set_interrupts_enabled(FALSE
);
358 PE_install_interrupt_handler(nub
, source
, target
,
359 (IOInterruptHandler
) handler
, refCon
);
361 (void) ml_set_interrupts_enabled(current_state
);
363 initialize_screen(NULL
, kPEAcquireScreen
);
369 processor_t processor
)
371 cpu_interrupt(processor
->cpu_id
);
375 machine_signal_idle_deferred(
376 __unused processor_t processor
)
378 panic("Unimplemented");
382 machine_signal_idle_cancel(
383 __unused processor_t processor
)
385 panic("Unimplemented");
391 processor_t
*processor_out
,
395 cpu_data_t
*this_cpu_datap
;
397 this_cpu_datap
= cpu_data_alloc(boot_cpu
);
398 if (this_cpu_datap
== NULL
) {
401 target_cpu
= this_cpu_datap
->cpu_number
;
402 assert((boot_cpu
&& (target_cpu
== 0)) ||
403 (!boot_cpu
&& (target_cpu
!= 0)));
405 lapic_cpu_map(lapic_id
, target_cpu
);
407 /* The cpu_id is not known at registration phase. Just do
410 this_cpu_datap
->cpu_phys_number
= lapic_id
;
412 this_cpu_datap
->cpu_console_buf
= console_cpu_alloc(boot_cpu
);
413 if (this_cpu_datap
->cpu_console_buf
== NULL
)
417 if (kpc_register_cpu(this_cpu_datap
) != TRUE
)
422 cpu_thread_alloc(this_cpu_datap
->cpu_number
);
423 if (this_cpu_datap
->lcpu
.core
== NULL
)
426 #if NCOPY_WINDOWS > 0
427 this_cpu_datap
->cpu_pmap
= pmap_cpu_alloc(boot_cpu
);
428 if (this_cpu_datap
->cpu_pmap
== NULL
)
432 this_cpu_datap
->cpu_processor
= cpu_processor_alloc(boot_cpu
);
433 if (this_cpu_datap
->cpu_processor
== NULL
)
436 * processor_init() deferred to topology start
437 * because "slot numbers" a.k.a. logical processor numbers
438 * are not yet finalized.
442 *processor_out
= this_cpu_datap
->cpu_processor
;
447 cpu_processor_free(this_cpu_datap
->cpu_processor
);
448 #if NCOPY_WINDOWS > 0
449 pmap_cpu_free(this_cpu_datap
->cpu_pmap
);
451 console_cpu_free(this_cpu_datap
->cpu_console_buf
);
453 kpc_unregister_cpu(this_cpu_datap
);
461 ml_processor_register(
464 processor_t
*processor_out
,
468 static boolean_t done_topo_sort
= FALSE
;
469 static uint32_t num_registered
= 0;
471 /* Register all CPUs first, and track max */
476 DBG( "registering CPU lapic id %d\n", lapic_id
);
478 return register_cpu( lapic_id
, processor_out
, boot_cpu
);
481 /* Sort by topology before we start anything */
482 if( !done_topo_sort
)
484 DBG( "about to start CPUs. %d registered\n", num_registered
);
486 cpu_topology_sort( num_registered
);
487 done_topo_sort
= TRUE
;
490 /* Assign the cpu ID */
491 uint32_t cpunum
= -1;
492 cpu_data_t
*this_cpu_datap
= NULL
;
494 /* find cpu num and pointer */
495 cpunum
= ml_get_cpuid( lapic_id
);
497 if( cpunum
== 0xFFFFFFFF ) /* never heard of it? */
498 panic( "trying to start invalid/unregistered CPU %d\n", lapic_id
);
500 this_cpu_datap
= cpu_datap(cpunum
);
503 this_cpu_datap
->cpu_id
= cpu_id
;
505 /* allocate and initialize other per-cpu structures */
507 mp_cpus_call_cpu_init(cpunum
);
508 prng_cpu_init(cpunum
);
512 *processor_out
= this_cpu_datap
->cpu_processor
;
514 /* OK, try and start this CPU */
515 return cpu_topology_start_cpu( cpunum
);
520 ml_cpu_get_info(ml_cpu_info_t
*cpu_infop
)
522 boolean_t os_supports_sse
;
523 i386_cpu_info_t
*cpuid_infop
;
525 if (cpu_infop
== NULL
)
529 * Are we supporting MMX/SSE/SSE2/SSE3?
530 * As distinct from whether the cpu has these capabilities.
532 os_supports_sse
= !!(get_cr4() & CR4_OSXMM
);
534 if (ml_fpu_avx_enabled())
535 cpu_infop
->vector_unit
= 9;
536 else if ((cpuid_features() & CPUID_FEATURE_SSE4_2
) && os_supports_sse
)
537 cpu_infop
->vector_unit
= 8;
538 else if ((cpuid_features() & CPUID_FEATURE_SSE4_1
) && os_supports_sse
)
539 cpu_infop
->vector_unit
= 7;
540 else if ((cpuid_features() & CPUID_FEATURE_SSSE3
) && os_supports_sse
)
541 cpu_infop
->vector_unit
= 6;
542 else if ((cpuid_features() & CPUID_FEATURE_SSE3
) && os_supports_sse
)
543 cpu_infop
->vector_unit
= 5;
544 else if ((cpuid_features() & CPUID_FEATURE_SSE2
) && os_supports_sse
)
545 cpu_infop
->vector_unit
= 4;
546 else if ((cpuid_features() & CPUID_FEATURE_SSE
) && os_supports_sse
)
547 cpu_infop
->vector_unit
= 3;
548 else if (cpuid_features() & CPUID_FEATURE_MMX
)
549 cpu_infop
->vector_unit
= 2;
551 cpu_infop
->vector_unit
= 0;
553 cpuid_infop
= cpuid_info();
555 cpu_infop
->cache_line_size
= cpuid_infop
->cache_linesize
;
557 cpu_infop
->l1_icache_size
= cpuid_infop
->cache_size
[L1I
];
558 cpu_infop
->l1_dcache_size
= cpuid_infop
->cache_size
[L1D
];
560 if (cpuid_infop
->cache_size
[L2U
] > 0) {
561 cpu_infop
->l2_settings
= 1;
562 cpu_infop
->l2_cache_size
= cpuid_infop
->cache_size
[L2U
];
564 cpu_infop
->l2_settings
= 0;
565 cpu_infop
->l2_cache_size
= 0xFFFFFFFF;
568 if (cpuid_infop
->cache_size
[L3U
] > 0) {
569 cpu_infop
->l3_settings
= 1;
570 cpu_infop
->l3_cache_size
= cpuid_infop
->cache_size
[L3U
];
572 cpu_infop
->l3_settings
= 0;
573 cpu_infop
->l3_cache_size
= 0xFFFFFFFF;
578 ml_init_max_cpus(unsigned long max_cpus
)
580 boolean_t current_state
;
582 current_state
= ml_set_interrupts_enabled(FALSE
);
583 if (max_cpus_initialized
!= MAX_CPUS_SET
) {
584 if (max_cpus
> 0 && max_cpus
<= MAX_CPUS
) {
586 * Note: max_cpus is the number of enabled processors
587 * that ACPI found; max_ncpus is the maximum number
588 * that the kernel supports or that the "cpus="
589 * boot-arg has set. Here we take int minimum.
591 machine_info
.max_cpus
= (integer_t
)MIN(max_cpus
, max_ncpus
);
593 if (max_cpus_initialized
== MAX_CPUS_WAIT
)
594 wakeup((event_t
)&max_cpus_initialized
);
595 max_cpus_initialized
= MAX_CPUS_SET
;
597 (void) ml_set_interrupts_enabled(current_state
);
601 ml_get_max_cpus(void)
603 boolean_t current_state
;
605 current_state
= ml_set_interrupts_enabled(FALSE
);
606 if (max_cpus_initialized
!= MAX_CPUS_SET
) {
607 max_cpus_initialized
= MAX_CPUS_WAIT
;
608 assert_wait((event_t
)&max_cpus_initialized
, THREAD_UNINT
);
609 (void)thread_block(THREAD_CONTINUE_NULL
);
611 (void) ml_set_interrupts_enabled(current_state
);
612 return(machine_info
.max_cpus
);
616 ml_wants_panic_trap_to_debugger(void)
622 ml_panic_trap_to_debugger(__unused
const char *panic_format_str
,
623 __unused
va_list *panic_args
,
624 __unused
unsigned int reason
,
626 __unused
uint64_t panic_options_mask
,
627 __unused
unsigned long panic_caller
)
633 * Routine: ml_init_lock_timeout
637 ml_init_lock_timeout(void)
641 #if DEVELOPMENT || DEBUG
642 uint64_t default_timeout_ns
= NSEC_PER_SEC
>>2;
644 uint64_t default_timeout_ns
= NSEC_PER_SEC
>>1;
649 if (PE_parse_boot_argn("slto_us", &slto
, sizeof (slto
)))
650 default_timeout_ns
= slto
* NSEC_PER_USEC
;
653 * LockTimeOut is absolutetime, LockTimeOutTSC is in TSC ticks,
654 * and LockTimeOutUsec is in microseconds and it's 32-bits.
656 LockTimeOutUsec
= (uint32_t) (default_timeout_ns
/ NSEC_PER_USEC
);
657 nanoseconds_to_absolutetime(default_timeout_ns
, &abstime
);
658 LockTimeOut
= abstime
;
659 LockTimeOutTSC
= tmrCvt(abstime
, tscFCvtn2t
);
662 * TLBTimeOut dictates the TLB flush timeout period. It defaults to
663 * LockTimeOut but can be overriden separately. In particular, a
664 * zero value inhibits the timeout-panic and cuts a trace evnt instead
665 * - see pmap_flush_tlbs().
667 if (PE_parse_boot_argn("tlbto_us", &slto
, sizeof (slto
))) {
668 default_timeout_ns
= slto
* NSEC_PER_USEC
;
669 nanoseconds_to_absolutetime(default_timeout_ns
, &abstime
);
670 TLBTimeOut
= (uint32_t) abstime
;
672 TLBTimeOut
= LockTimeOut
;
675 #if DEVELOPMENT || DEBUG
676 reportphyreaddelayabs
= LockTimeOut
>> 1;
678 if (PE_parse_boot_argn("phyreadmaxus", &slto
, sizeof (slto
))) {
679 default_timeout_ns
= slto
* NSEC_PER_USEC
;
680 nanoseconds_to_absolutetime(default_timeout_ns
, &abstime
);
681 reportphyreaddelayabs
= abstime
;
684 if (PE_parse_boot_argn("mtxspin", &mtxspin
, sizeof (mtxspin
))) {
685 if (mtxspin
> USEC_PER_SEC
>>4)
686 mtxspin
= USEC_PER_SEC
>>4;
687 nanoseconds_to_absolutetime(mtxspin
*NSEC_PER_USEC
, &abstime
);
689 nanoseconds_to_absolutetime(10*NSEC_PER_USEC
, &abstime
);
691 MutexSpin
= (unsigned int)abstime
;
693 nanoseconds_to_absolutetime(4ULL * NSEC_PER_SEC
, &LastDebuggerEntryAllowance
);
694 if (PE_parse_boot_argn("panic_restart_timeout", &prt
, sizeof (prt
)))
695 nanoseconds_to_absolutetime(prt
* NSEC_PER_SEC
, &panic_restart_timeout
);
697 virtualized
= ((cpuid_features() & CPUID_FEATURE_VMM
) != 0);
701 if (!PE_parse_boot_argn("vti", &vti
, sizeof (vti
)))
703 printf("Timeouts adjusted for virtualization (<<%d)\n", vti
);
704 kprintf("Timeouts adjusted for virtualization (<<%d):\n", vti
);
705 #define VIRTUAL_TIMEOUT_INFLATE64(_timeout) \
707 kprintf("%24s: 0x%016llx ", #_timeout, _timeout); \
709 kprintf("-> 0x%016llx\n", _timeout); \
711 #define VIRTUAL_TIMEOUT_INFLATE32(_timeout) \
713 kprintf("%24s: 0x%08x ", #_timeout, _timeout); \
714 if ((_timeout <<vti) >> vti == _timeout) \
717 _timeout = ~0; /* cap rather than overflow */ \
718 kprintf("-> 0x%08x\n", _timeout); \
720 VIRTUAL_TIMEOUT_INFLATE32(LockTimeOutUsec
);
721 VIRTUAL_TIMEOUT_INFLATE64(LockTimeOut
);
722 VIRTUAL_TIMEOUT_INFLATE64(LockTimeOutTSC
);
723 VIRTUAL_TIMEOUT_INFLATE64(TLBTimeOut
);
724 VIRTUAL_TIMEOUT_INFLATE64(MutexSpin
);
725 VIRTUAL_TIMEOUT_INFLATE64(reportphyreaddelayabs
);
728 interrupt_latency_tracker_setup();
729 simple_lock_init(&ml_timer_evaluation_slock
, 0);
733 * Threshold above which we should attempt to block
734 * instead of spinning for clock_delay_until().
738 ml_init_delay_spin_threshold(int threshold_us
)
740 nanoseconds_to_absolutetime(threshold_us
* NSEC_PER_USEC
, &delay_spin_threshold
);
744 ml_delay_should_spin(uint64_t interval
)
746 return (interval
< delay_spin_threshold
) ? TRUE
: FALSE
;
750 * This is called from the machine-independent layer
751 * to perform machine-dependent info updates. Defer to cpu_thread_init().
760 * This is called from the machine-independent layer
761 * to perform machine-dependent info updates.
766 i386_deactivate_cpu();
772 * The following are required for parts of the kernel
773 * that cannot resolve these functions as inlines:
775 extern thread_t
current_act(void);
779 return(current_thread_fast());
782 #undef current_thread
783 extern thread_t
current_thread(void);
787 return(current_thread_fast());
791 boolean_t
ml_is64bit(void) {
793 return (cpu_mode_is64bit());
797 boolean_t
ml_thread_is64bit(thread_t thread
) {
799 return (thread_is_64bit(thread
));
803 boolean_t
ml_state_is64bit(void *saved_state
) {
805 return is_saved_state64(saved_state
);
808 void ml_cpu_set_ldt(int selector
)
811 * Avoid loading the LDT
812 * if we're setting the KERNEL LDT and it's already set.
814 if (selector
== KERNEL_LDT
&&
815 current_cpu_datap()->cpu_ldt
== KERNEL_LDT
)
819 current_cpu_datap()->cpu_ldt
= selector
;
822 void ml_fp_setvalid(boolean_t value
)
827 uint64_t ml_cpu_int_event_time(void)
829 return current_cpu_datap()->cpu_int_event_time
;
832 vm_offset_t
ml_stack_remaining(void)
834 uintptr_t local
= (uintptr_t) &local
;
836 if (ml_at_interrupt_context() != 0) {
837 return (local
- (current_cpu_datap()->cpu_int_stack_top
- INTSTACK_SIZE
));
839 return (local
- current_thread()->kernel_stack
);
844 vm_offset_t
ml_stack_base(void);
845 vm_size_t
ml_stack_size(void);
850 if (ml_at_interrupt_context()) {
851 return current_cpu_datap()->cpu_int_stack_top
- INTSTACK_SIZE
;
853 return current_thread()->kernel_stack
;
860 if (ml_at_interrupt_context()) {
861 return INTSTACK_SIZE
;
863 return kernel_stack_size
;
869 kernel_preempt_check(void)
874 assert(get_preemption_level() == 0);
876 __asm__
volatile("pushf; pop %0" : "=r" (flags
));
878 intr
= ((flags
& EFL_IF
) != 0);
880 if ((*ast_pending() & AST_URGENT
) && intr
== TRUE
) {
882 * can handle interrupts and preemptions
887 * now cause the PRE-EMPTION trap
889 __asm__
volatile ("int %0" :: "N" (T_PREEMPT
));
893 boolean_t
machine_timeout_suspended(void) {
894 return (pmap_tlb_flush_timeout
|| spinlock_timed_out
|| panic_active() || mp_recent_debugger_activity() || ml_recent_wake());
897 /* Eagerly evaluate all pending timer and thread callouts
899 void ml_timer_evaluate(void) {
900 KERNEL_DEBUG_CONSTANT(DECR_TIMER_RESCAN
|DBG_FUNC_START
, 0, 0, 0, 0, 0);
902 uint64_t te_end
, te_start
= mach_absolute_time();
903 simple_lock(&ml_timer_evaluation_slock
);
904 ml_timer_evaluation_in_progress
= TRUE
;
905 thread_call_delayed_timer_rescan_all();
906 mp_cpus_call(CPUMASK_ALL
, ASYNC
, timer_queue_expire_rescan
, NULL
);
907 ml_timer_evaluation_in_progress
= FALSE
;
908 ml_timer_eager_evaluations
++;
909 te_end
= mach_absolute_time();
910 ml_timer_eager_evaluation_max
= MAX(ml_timer_eager_evaluation_max
, (te_end
- te_start
));
911 simple_unlock(&ml_timer_evaluation_slock
);
913 KERNEL_DEBUG_CONSTANT(DECR_TIMER_RESCAN
|DBG_FUNC_END
, 0, 0, 0, 0, 0);
917 ml_timer_forced_evaluation(void) {
918 return ml_timer_evaluation_in_progress
;
921 /* 32-bit right-rotate n bits */
922 static inline uint32_t ror32(uint32_t val
, const unsigned int n
)
924 __asm__
volatile("rorl %%cl,%0" : "=r" (val
) : "0" (val
), "c" (n
));
929 ml_entropy_collect(void)
931 uint32_t tsc_lo
, tsc_hi
;
934 assert(cpu_number() == master_cpu
);
936 /* update buffer pointer cyclically */
937 if (EntropyData
.index_ptr
- EntropyData
.buffer
== ENTROPY_BUFFER_SIZE
)
938 ep
= EntropyData
.index_ptr
= EntropyData
.buffer
;
940 ep
= EntropyData
.index_ptr
++;
942 rdtsc_nofence(tsc_lo
, tsc_hi
);
943 *ep
= ror32(*ep
, 9) ^ tsc_lo
;
947 ml_energy_stat(__unused thread_t t
) {
952 ml_gpu_stat_update(uint64_t gpu_ns_delta
) {
953 current_thread()->machine
.thread_gpu_ns
+= gpu_ns_delta
;
957 ml_gpu_stat(thread_t t
) {
958 return t
->machine
.thread_gpu_ns
;
961 int plctrace_enabled
= 0;
963 void _disable_preemption(void) {
964 disable_preemption_internal();
967 void _enable_preemption(void) {
968 enable_preemption_internal();
971 void plctrace_disable(void) {
972 plctrace_enabled
= 0;
975 static boolean_t ml_quiescing
;
977 void ml_set_is_quiescing(boolean_t quiescing
)
979 assert(FALSE
== ml_get_interrupts_enabled());
980 ml_quiescing
= quiescing
;
983 boolean_t
ml_is_quiescing(void)
985 assert(FALSE
== ml_get_interrupts_enabled());
986 return (ml_quiescing
);
989 uint64_t ml_get_booter_memory_size(void)