osfmk/arm/machine_cpuid.h

   1 /*
   2  * Copyright (c) 2017 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 #ifndef _ARM_MACHINE_CPUID_H_
  29 #define _ARM_MACHINE_CPUID_H_
  30
  31 /* CPU feature identification */
  32
  33 typedef struct {
  34 uint32_t        arm_32bit_isa   : 4,
  35                         arm_thumb_ver   : 4,
  36                         arm_jazelle             : 4,
  37                         arm_thumb2              : 4,
  38                         reserved                : 16;
  39 } arm_feature_bits_t;
  40
  41 typedef union {
  42         arm_feature_bits_t      field;
  43         uint32_t                        value;
  44 } arm_feature0_reg_t;
  45
  46 // Register 0, subtype 21: Instruction Set Features #1
  47 typedef struct
  48 {
  49     uint32_t endianness_support     : 4;
  50     uint32_t exception_1_support    : 4;
  51     uint32_t exception_2_support    : 4;
  52     uint32_t sign_zero_ext_support  : 4;
  53     uint32_t if_then_support        : 4;
  54     uint32_t immediate_support      : 4;
  55     uint32_t interworking_support   : 4;
  56     uint32_t jazelle_support        : 4;
  57 }
  58 syscp_ID_instructions_feat_1_reg;
  59
  60 typedef union {
  61         uint32_t value;
  62         syscp_ID_instructions_feat_1_reg field;
  63 } arm_isa_feat1_reg;
  64
  65 arm_isa_feat1_reg machine_read_isa_feat1(void);
  66
  67 /* Debug identification */
  68
  69 /* ID_DFR0 */
  70 typedef union {
  71         struct {
  72                 uint32_t    coprocessor_core_debug      : 4,
  73                             coprocessor_secure_debug    : 4,
  74                             memory_mapped_core_debug    : 4,
  75                             coprocessor_trace_debug     : 4,
  76                             memory_mapped_trace_debug   : 4,
  77                             microcontroller_debug       : 4;
  78         } debug_feature;
  79         uint32_t value;
  80 } arm_cpuid_id_dfr0;
  81
  82 /* DBGDIDR */
  83 typedef union {
  84         struct {
  85                 uint32_t    revision                    : 4,
  86                             variant                     : 4,
  87                                                         : 4,
  88                             se_imp                      : 1,
  89                             pcsr_imp                    : 1,
  90                             nsuhd_imp                   : 1,
  91                                                         : 1,
  92                             version                     : 4,
  93                             ctx_cmps                    : 4,
  94                             brps                        : 4,
  95                             wrps                        : 4;
  96         } debug_id;
  97         uint32_t value;
  98 } arm_debug_dbgdidr;
  99
 100 typedef struct {
 101         boolean_t               memory_mapped_core_debug;
 102         boolean_t               coprocessor_core_debug;
 103         uint32_t                num_watchpoint_pairs;
 104         uint32_t                num_breakpoint_pairs;
 105 } arm_debug_info_t;
 106
 107 #endif /* _ARM_MACHINE_CPUID_H_ */