osfmk/chud/ppc/chud_cpu_asm.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #include <chud/ppc/chud_spr.h>
  30 #include <ppc/asm.h>
  31 #include <mach/kern_return.h>
  32
  33 /*
  34  * kern_return_t mfspr64(uint64_t *val, int spr);
  35  *
  36  * r3: address to store value in
  37  * r4: spr to read from
  38  *
  39  */
  40
  41 ;           Force a line boundry here
  42             .align  5
  43             .globl  EXT(mfspr64)
  44
  45 EXT(mfspr64):
  46             ;; generic PPC 64-bit wide SPRs
  47             cmpwi       r4,chud_ppc_srr0
  48             beq         mfspr64_srr0
  49             cmpwi       r4,chud_ppc_srr1
  50             beq         mfspr64_srr1
  51             cmpwi       r4,chud_ppc_dar
  52             beq         mfspr64_dar
  53             cmpwi       r4,chud_ppc_sdr1
  54             beq         mfspr64_sdr1
  55             cmpwi       r4,chud_ppc_sprg0
  56             beq         mfspr64_sprg0
  57             cmpwi       r4,chud_ppc_sprg1
  58             beq         mfspr64_sprg1
  59             cmpwi       r4,chud_ppc_sprg2
  60             beq         mfspr64_sprg2
  61             cmpwi       r4,chud_ppc_sprg3
  62             beq         mfspr64_sprg3
  63             cmpwi       r4,chud_ppc64_asr
  64             beq         mfspr64_asr
  65             cmpwi       r4,chud_ppc_dabr
  66             beq         mfspr64_dabr
  67
  68             ;; GPUL specific 64-bit wide SPRs
  69             cmpwi       r4,chud_970_hid0
  70             beq         mfspr64_hid0
  71             cmpwi       r4,chud_970_hid1
  72             beq         mfspr64_hid1
  73             cmpwi       r4,chud_970_hid4
  74             beq         mfspr64_hid4
  75             cmpwi       r4,chud_970_hid5
  76             beq         mfspr64_hid5
  77             cmpwi       r4,chud_970_mmcr0
  78             beq         mfspr64_mmcr0
  79             cmpwi       r4,chud_970_mmcr1
  80             beq         mfspr64_mmcr1
  81             cmpwi       r4,chud_970_mmcra
  82             beq         mfspr64_mmcra
  83             cmpwi       r4,chud_970_siar
  84             beq         mfspr64_siar
  85             cmpwi       r4,chud_970_sdar
  86             beq         mfspr64_sdar
  87             cmpwi       r4,chud_970_imc
  88             beq         mfspr64_imc
  89             cmpwi       r4,chud_970_rmor
  90             beq         mfspr64_rmor
  91             cmpwi       r4,chud_970_hrmor
  92             beq         mfspr64_hrmor
  93             cmpwi       r4,chud_970_hior
  94             beq         mfspr64_hior
  95             cmpwi       r4,chud_970_lpidr
  96             beq         mfspr64_lpidr
  97             cmpwi       r4,chud_970_lpcr
  98             beq         mfspr64_lpcr
  99             cmpwi       r4,chud_970_dabrx
 100             beq         mfspr64_dabrx
 101             cmpwi       r4,chud_970_hsprg0
 102             beq         mfspr64_hsprg0
 103             cmpwi       r4,chud_970_hsprg1
 104             beq         mfspr64_hsprg1
 105             cmpwi       r4,chud_970_hsrr0
 106             beq         mfspr64_hsrr0
 107             cmpwi       r4,chud_970_hsrr1
 108             beq         mfspr64_hsrr1
 109             cmpwi       r4,chud_970_hdec
 110             beq         mfspr64_hdec
 111             cmpwi       r4,chud_970_trig0
 112             beq         mfspr64_trig0
 113             cmpwi       r4,chud_970_trig1
 114             beq         mfspr64_trig1
 115             cmpwi       r4,chud_970_trig2
 116             beq         mfspr64_trig2
 117             cmpwi       r4,chud_ppc64_accr
 118             beq         mfspr64_accr
 119             cmpwi       r4,chud_970_scomc
 120             beq         mfspr64_scomc
 121             cmpwi       r4,chud_970_scomd
 122             beq         mfspr64_scomd
 123
 124             b           mfspr64_failure
 125
 126 mfspr64_srr0:
 127             mfspr       r5,chud_ppc_srr0
 128             std         r5,0(r3)
 129             b           mfspr64_success
 130 mfspr64_srr1:
 131             mfspr       r5,chud_ppc_srr1
 132             std         r5,0(r3)
 133             b           mfspr64_success
 134 mfspr64_dar:
 135             mfspr       r5,chud_ppc_dar
 136             std         r5,0(r3)
 137             b           mfspr64_success
 138 mfspr64_sdr1:
 139             mfspr       r5,chud_ppc_sdr1
 140             std         r5,0(r3)
 141             b           mfspr64_success
 142 mfspr64_sprg0:
 143             mfspr       r5,chud_ppc_sprg0
 144             std         r5,0(r3)
 145             b           mfspr64_success
 146 mfspr64_sprg1:
 147             mfspr       r5,chud_ppc_sprg1
 148             std         r5,0(r3)
 149             b           mfspr64_success
 150 mfspr64_sprg2:
 151             mfspr       r5,chud_ppc_sprg2
 152             std         r5,0(r3)
 153             b           mfspr64_success
 154 mfspr64_sprg3:
 155             mfspr       r5,chud_ppc_sprg3
 156             std         r5,0(r3)
 157             b           mfspr64_success
 158 mfspr64_asr:
 159             mfspr       r5,chud_ppc64_asr
 160             std         r5,0(r3)
 161             b           mfspr64_success
 162 mfspr64_dabr:
 163             mfspr       r5,chud_ppc_dabr
 164             std         r5,0(r3)
 165             b           mfspr64_success
 166 mfspr64_hid0:
 167             mfspr       r5,chud_970_hid0
 168             std         r5,0(r3)
 169             b           mfspr64_success
 170 mfspr64_hid1:
 171             mfspr       r5,chud_970_hid1
 172             std         r5,0(r3)
 173             b           mfspr64_success
 174 mfspr64_hid4:
 175             mfspr       r5,chud_970_hid4
 176             std         r5,0(r3)
 177             b           mfspr64_success
 178 mfspr64_hid5:
 179             mfspr       r5,chud_970_hid5
 180             std         r5,0(r3)
 181             b           mfspr64_success
 182 mfspr64_mmcr0:
 183             mfspr       r5,chud_970_mmcr0
 184             std         r5,0(r3)
 185             b           mfspr64_success
 186 mfspr64_mmcr1:
 187             mfspr       r5,chud_970_mmcr1
 188             std         r5,0(r3)
 189             b           mfspr64_success
 190 mfspr64_mmcra:
 191             mfspr       r5,chud_970_mmcra
 192             std         r5,0(r3)
 193             b           mfspr64_success
 194 mfspr64_siar:
 195             mfspr       r5,chud_970_siar
 196             std         r5,0(r3)
 197             b           mfspr64_success
 198 mfspr64_sdar:
 199             mfspr       r5,chud_970_sdar
 200             std         r5,0(r3)
 201             b           mfspr64_success
 202 mfspr64_imc:
 203             mfspr       r5,chud_970_imc
 204             std         r5,0(r3)
 205             b           mfspr64_success
 206 mfspr64_rmor:
 207             mfspr       r5,chud_970_rmor
 208             std         r5,0(r3)
 209             b           mfspr64_success
 210 mfspr64_hrmor:
 211             mfspr       r5,chud_970_hrmor
 212             std         r5,0(r3)
 213             b           mfspr64_success
 214 mfspr64_hior:
 215             mfspr       r5,chud_970_hior
 216             std         r5,0(r3)
 217             b           mfspr64_success
 218 mfspr64_lpidr:
 219             mfspr       r5,chud_970_lpidr
 220             std         r5,0(r3)
 221             b           mfspr64_success
 222 mfspr64_lpcr:
 223             mfspr       r5,chud_970_lpcr
 224             std         r5,0(r3)
 225             b           mfspr64_success
 226 mfspr64_dabrx:
 227             mfspr       r5,chud_970_dabrx
 228             std         r5,0(r3)
 229             b           mfspr64_success
 230 mfspr64_hsprg0:
 231             mfspr       r5,chud_970_hsprg0
 232             std         r5,0(r3)
 233             b           mfspr64_success
 234 mfspr64_hsprg1:
 235             mfspr       r5,chud_970_hsprg1
 236             std         r5,0(r3)
 237             b           mfspr64_success
 238 mfspr64_hsrr0:
 239             mfspr       r5,chud_970_hsrr0
 240             std         r5,0(r3)
 241             b           mfspr64_success
 242 mfspr64_hsrr1:
 243             mfspr       r5,chud_970_hsrr1
 244             std         r5,0(r3)
 245             b           mfspr64_success
 246 mfspr64_hdec:
 247             mfspr       r5,chud_970_hdec
 248             std         r5,0(r3)
 249             b           mfspr64_success
 250 mfspr64_trig0:
 251             mfspr       r5,chud_970_trig0
 252             std         r5,0(r3)
 253             b           mfspr64_success
 254 mfspr64_trig1:
 255             mfspr       r5,chud_970_trig1
 256             std         r5,0(r3)
 257             b           mfspr64_success
 258 mfspr64_trig2:
 259             mfspr       r5,chud_970_trig2
 260             std         r5,0(r3)
 261             b           mfspr64_success
 262 mfspr64_accr:
 263             mfspr       r5,chud_ppc64_accr
 264             std         r5,0(r3)
 265             b           mfspr64_success
 266 mfspr64_scomc:
 267             mfspr       r5,chud_970_scomc
 268             std         r5,0(r3)
 269             b           mfspr64_success
 270 mfspr64_scomd:
 271             mfspr       r5,chud_970_scomd
 272             std         r5,0(r3)
 273             b           mfspr64_success
 274
 275 mfspr64_failure:
 276             li          r3,KERN_FAILURE
 277             blr
 278
 279 mfspr64_success:
 280             li          r3,KERN_SUCCESS
 281             blr
 282
 283
 284 /*
 285  * kern_return_t mtspr64(int spr, uint64_t *val);
 286  *
 287  * r3: spr to write to
 288  * r4: address to get value from
 289  *
 290  */
 291
 292 ;           Force a line boundry here
 293             .align  5
 294             .globl  EXT(mtspr64)
 295
 296 EXT(mtspr64):
 297             ;; generic PPC 64-bit wide SPRs
 298             cmpwi       r3,chud_ppc_srr0
 299             beq         mtspr64_srr0
 300             cmpwi       r3,chud_ppc_srr1
 301             beq         mtspr64_srr1
 302             cmpwi       r3,chud_ppc_dar
 303             beq         mtspr64_dar
 304             cmpwi       r3,chud_ppc_sdr1
 305             beq         mtspr64_sdr1
 306             cmpwi       r3,chud_ppc_sprg0
 307             beq         mtspr64_sprg0
 308             cmpwi       r3,chud_ppc_sprg1
 309             beq         mtspr64_sprg1
 310             cmpwi       r3,chud_ppc_sprg2
 311             beq         mtspr64_sprg2
 312             cmpwi       r3,chud_ppc_sprg3
 313             beq         mtspr64_sprg3
 314             cmpwi       r3,chud_ppc64_asr
 315             beq         mtspr64_asr
 316             cmpwi       r3,chud_ppc_dabr
 317             beq         mtspr64_dabr
 318
 319             ;; GPUL specific 64-bit wide SPRs
 320             cmpwi       r3,chud_970_hid0
 321             beq         mtspr64_hid0
 322             cmpwi       r3,chud_970_hid1
 323             beq         mtspr64_hid1
 324             cmpwi       r3,chud_970_hid4
 325             beq         mtspr64_hid4
 326             cmpwi       r3,chud_970_hid5
 327             beq         mtspr64_hid5
 328             cmpwi       r3,chud_970_mmcr0
 329             beq         mtspr64_mmcr0
 330             cmpwi       r3,chud_970_mmcr1
 331             beq         mtspr64_mmcr1
 332             cmpwi       r3,chud_970_mmcra
 333             beq         mtspr64_mmcra
 334             cmpwi       r3,chud_970_siar
 335             beq         mtspr64_siar
 336             cmpwi       r3,chud_970_sdar
 337             beq         mtspr64_sdar
 338             cmpwi       r3,chud_970_imc
 339             beq         mtspr64_imc
 340             cmpwi       r3,chud_970_rmor
 341             beq         mtspr64_rmor
 342             cmpwi       r3,chud_970_hrmor
 343             beq         mtspr64_hrmor
 344             cmpwi       r3,chud_970_hior
 345             beq         mtspr64_hior
 346             cmpwi       r3,chud_970_lpidr
 347             beq         mtspr64_lpidr
 348             cmpwi       r3,chud_970_lpcr
 349             beq         mtspr64_lpcr
 350             cmpwi       r3,chud_970_dabrx
 351             beq         mtspr64_dabrx
 352             cmpwi       r3,chud_970_hsprg0
 353             beq         mtspr64_hsprg0
 354             cmpwi       r3,chud_970_hsprg1
 355             beq         mtspr64_hsprg1
 356             cmpwi       r3,chud_970_hsrr0
 357             beq         mtspr64_hsrr0
 358             cmpwi       r3,chud_970_hsrr1
 359             beq         mtspr64_hsrr1
 360             cmpwi       r3,chud_970_hdec
 361             beq         mtspr64_hdec
 362             cmpwi       r3,chud_970_trig0
 363             beq         mtspr64_trig0
 364             cmpwi       r3,chud_970_trig1
 365             beq         mtspr64_trig1
 366             cmpwi       r3,chud_970_trig2
 367             beq         mtspr64_trig2
 368             cmpwi       r3,chud_ppc64_accr
 369             beq         mtspr64_accr
 370             cmpwi       r3,chud_970_scomc
 371             beq         mtspr64_scomc
 372             cmpwi       r3,chud_970_scomd
 373             beq         mtspr64_scomd
 374
 375             b           mtspr64_failure
 376
 377 mtspr64_srr0:
 378             ld          r5,0(r4)
 379             mtspr       chud_ppc_srr0,r5
 380             b           mtspr64_success
 381 mtspr64_srr1:
 382             ld          r5,0(r4)
 383             mtspr       chud_ppc_srr1,r5
 384             b           mtspr64_success
 385 mtspr64_dar:
 386             ld          r5,0(r4)
 387             mtspr       chud_ppc_dar,r5
 388             b           mtspr64_success
 389 mtspr64_sdr1:
 390             ld          r5,0(r4)
 391             mtspr       chud_ppc_sdr1,r5
 392             b           mtspr64_success
 393 mtspr64_sprg0:
 394             ld          r5,0(r4)
 395             mtspr       chud_ppc_sprg0,r5
 396             b           mtspr64_success
 397 mtspr64_sprg1:
 398             ld          r5,0(r4)
 399             mtspr       chud_ppc_sprg1,r5
 400             b           mtspr64_success
 401 mtspr64_sprg2:
 402             ld          r5,0(r4)
 403             mtspr       chud_ppc_sprg2,r5
 404             b           mtspr64_success
 405 mtspr64_sprg3:
 406             ld          r5,0(r4)
 407             mtspr       chud_ppc_sprg3,r5
 408             b           mtspr64_success
 409 mtspr64_asr:
 410             ld          r5,0(r4)
 411             mtspr       chud_ppc64_asr,r5
 412             b           mtspr64_success
 413 mtspr64_dabr:
 414             ld          r5,0(r4)
 415             mtspr       chud_ppc_dabr,r5
 416             b           mtspr64_success
 417 mtspr64_hid0:
 418             ld          r5,0(r4)
 419             sync
 420             mtspr       chud_970_hid0,r5
 421             mfspr       r5,chud_970_hid0        /* syncronization requirements */
 422             mfspr       r5,chud_970_hid0
 423             mfspr       r5,chud_970_hid0
 424             mfspr       r5,chud_970_hid0
 425             mfspr       r5,chud_970_hid0
 426             mfspr       r5,chud_970_hid0
 427             b           mtspr64_success
 428 mtspr64_hid1:
 429             ld          r5,0(r4)
 430             mtspr       chud_970_hid1,r5        /* tell you twice */
 431             mtspr       chud_970_hid1,r5
 432             isync
 433             b           mtspr64_success
 434 mtspr64_hid4:
 435             ld          r5,0(r4)
 436             sync                                /* syncronization requirements */
 437             mtspr       chud_970_hid4,r5
 438             isync
 439             b           mtspr64_success
 440 mtspr64_hid5:
 441             ld          r5,0(r4)
 442             mtspr       chud_970_hid5,r5
 443             b           mtspr64_success
 444 mtspr64_mmcr0:
 445             ld          r5,0(r4)
 446             mtspr       chud_970_mmcr0,r5
 447             b           mtspr64_success
 448 mtspr64_mmcr1:
 449             ld          r5,0(r4)
 450             mtspr       chud_970_mmcr1,r5
 451             b           mtspr64_success
 452 mtspr64_mmcra:
 453             ld          r5,0(r4)
 454             mtspr       chud_970_mmcra,r5
 455             b           mtspr64_success
 456 mtspr64_siar:
 457             ld          r5,0(r4)
 458             mtspr       chud_970_siar,r5
 459             b           mtspr64_success
 460 mtspr64_sdar:
 461             ld          r5,0(r4)
 462             mtspr       chud_970_sdar,r5
 463             b           mtspr64_success
 464 mtspr64_imc:
 465             ld          r5,0(r4)
 466             mtspr       chud_970_imc,r5
 467             b           mtspr64_success
 468 mtspr64_rmor:
 469             ld          r5,0(r4)
 470             mtspr       chud_970_rmor,r5
 471             b           mtspr64_success
 472 mtspr64_hrmor:
 473             ld          r5,0(r4)
 474             mtspr       chud_970_hrmor,r5
 475             b           mtspr64_success
 476 mtspr64_hior:
 477             ld          r5,0(r4)
 478             mtspr       chud_970_hior,r5
 479             b           mtspr64_success
 480 mtspr64_lpidr:
 481             ld          r5,0(r4)
 482             mtspr       chud_970_lpidr,r5
 483             b           mtspr64_success
 484 mtspr64_lpcr:
 485             ld          r5,0(r4)
 486             mtspr       chud_970_lpcr,r5
 487             b           mtspr64_success
 488 mtspr64_dabrx:
 489             ld          r5,0(r4)
 490             mtspr       chud_970_dabrx,r5
 491             b           mtspr64_success
 492 mtspr64_hsprg0:
 493             ld          r5,0(r4)
 494             mtspr       chud_970_hsprg0,r5
 495             b           mtspr64_success
 496 mtspr64_hsprg1:
 497             ld          r5,0(r4)
 498             mtspr       chud_970_hsprg1,r5
 499             b           mtspr64_success
 500 mtspr64_hsrr0:
 501             ld          r5,0(r4)
 502             mtspr       chud_970_hsrr0,r5
 503             b           mtspr64_success
 504 mtspr64_hsrr1:
 505             ld          r5,0(r4)
 506             mtspr       chud_970_hsrr1,r5
 507             b           mtspr64_success
 508 mtspr64_hdec:
 509             ld          r5,0(r4)
 510             mtspr       chud_970_hdec,r5
 511             b           mtspr64_success
 512 mtspr64_trig0:
 513             ld          r5,0(r4)
 514             mtspr       chud_970_trig0,r5
 515             b           mtspr64_success
 516 mtspr64_trig1:
 517             ld          r5,0(r4)
 518             mtspr       chud_970_trig1,r5
 519             b           mtspr64_success
 520 mtspr64_trig2:
 521             ld          r5,0(r4)
 522             mtspr       chud_970_trig2,r5
 523             b           mtspr64_success
 524 mtspr64_accr:
 525             ld          r5,0(r4)
 526             mtspr       chud_ppc64_accr,r5
 527             b           mtspr64_success
 528 mtspr64_scomc:
 529             ld          r5,0(r4)
 530             mtspr       chud_970_scomc,r5
 531             b           mtspr64_success
 532 mtspr64_scomd:
 533             ld          r5,0(r4)
 534             mtspr       chud_970_scomd,r5
 535             b           mtspr64_success
 536
 537 mtspr64_failure:
 538             li          r3,KERN_FAILURE
 539             blr
 540
 541 mtspr64_success:
 542             li          r3,KERN_SUCCESS
 543             blr
 544
 545
 546 /*
 547  * kern_return_t mfmsr64(uint64_t *val);
 548  *
 549  * r3: address to store value in
 550  *
 551  */
 552
 553 ;           Force a line boundry here
 554             .align  5
 555             .globl  EXT(mfmsr64)
 556
 557 EXT(mfmsr64):
 558             mfmsr       r5
 559             std         r5,0(r3)
 560 mfmsr64_success:
 561             li          r3,KERN_SUCCESS
 562             blr
 563
 564 mfmsr64_failure:
 565             li          r3,KERN_FAILURE
 566             blr
 567
 568
 569 /*
 570  * kern_return_t mtmsr64(uint64_t *val);
 571  *
 572  * r3: address to load value from
 573  *
 574  */
 575
 576 ;           Force a line boundry here
 577             .align  5
 578             .globl  EXT(mtmsr64)
 579
 580 EXT(mtmsr64):
 581             ld          r5,0(r3)
 582             mtmsrd      r5
 583             b           mtmsr64_success
 584
 585 mtmsr64_success:
 586             li          r3,KERN_SUCCESS
 587             blr
 588
 589 mtmsr64_failure:
 590             li          r3,KERN_FAILURE
 591             blr
 592
 593 .L_end: