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[apple/xnu.git] / bsd / dev / i386 / dis_tables.c
1 /*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22
23 /*
24 * Copyright (c) 2015, Joyent, Inc.
25 * Copyright (c) 2008 Sun Microsystems, Inc. All rights reserved.
26 */
27
28 /*
29 * Copyright (c) 2010, Intel Corporation.
30 * All rights reserved.
31 */
32
33 /* Copyright (c) 1988 AT&T */
34 /* All Rights Reserved */
35
36 /*
37 * APPLE NOTE: There is a copy of this file in userspace in
38 * dtrace:/disassembler/dis_tables.c
39 *
40 * It needs to be in sync with this file.
41 */
42
43 #include <sys/dtrace.h>
44 #include <sys/dtrace_glue.h>
45 #include <sys/dis_tables.h>
46
47 /* BEGIN CSTYLED */
48
49 /*
50 * Disassembly begins in dis_distable, which is equivalent to the One-byte
51 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
52 * decoding loops then traverse out through the other tables as necessary to
53 * decode a given instruction.
54 *
55 * The behavior of this file can be controlled by one of the following flags:
56 *
57 * DIS_TEXT Include text for disassembly
58 * DIS_MEM Include memory-size calculations
59 *
60 * Either or both of these can be defined.
61 *
62 * This file is not, and will never be, cstyled. If anything, the tables should
63 * be taken out another tab stop or two so nothing overlaps.
64 */
65
66 /*
67 * These functions must be provided for the consumer to do disassembly.
68 */
69 #ifdef DIS_TEXT
70 extern char *strncpy(char *, const char *, size_t);
71 extern size_t strlen(const char *);
72 extern int strcmp(const char *, const char *);
73 extern int strncmp(const char *, const char *, size_t);
74 extern size_t strlcat(char *, const char *, size_t);
75 #endif
76
77
78 #define TERM 0 /* used to indicate that the 'indirect' */
79 /* field terminates - no pointer. */
80
81 /* Used to decode instructions. */
82 typedef struct instable {
83 struct instable *it_indirect; /* for decode op codes */
84 uchar_t it_adrmode;
85 #ifdef DIS_TEXT
86 char it_name[NCPS];
87 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */
88 #endif
89 #ifdef DIS_MEM
90 uint_t it_size:16;
91 #endif
92 uint_t it_invalid64:1; /* opcode invalid in amd64 */
93 uint_t it_always64:1; /* 64 bit when in 64 bit mode */
94 uint_t it_invalid32:1; /* invalid in IA32 */
95 uint_t it_stackop:1; /* push/pop stack operation */
96 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */
97 uint_t it_avxsuf:1; /* AVX suffix required */
98 } instable_t;
99
100 /*
101 * Instruction formats.
102 */
103 enum {
104 UNKNOWN,
105 MRw,
106 IMlw,
107 IMw,
108 IR,
109 OA,
110 AO,
111 MS,
112 SM,
113 Mv,
114 Mw,
115 M, /* register or memory */
116 MG9, /* register or memory in group 9 (prefix optional) */
117 Mb, /* register or memory, always byte sized */
118 MO, /* memory only (no registers) */
119 PREF,
120 SWAPGS_RDTSCP,
121 MONITOR_MWAIT,
122 R,
123 RA,
124 SEG,
125 MR,
126 RM,
127 RM_66r, /* RM, but with a required 0x66 prefix */
128 IA,
129 MA,
130 SD,
131 AD,
132 SA,
133 D,
134 INM,
135 SO,
136 BD,
137 I,
138 P,
139 V,
140 DSHIFT, /* for double shift that has an 8-bit immediate */
141 U,
142 OVERRIDE,
143 NORM, /* instructions w/o ModR/M byte, no memory access */
144 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */
145 O, /* for call */
146 JTAB, /* jump table */
147 IMUL, /* for 186 iimul instr */
148 CBW, /* so data16 can be evaluated for cbw and variants */
149 MvI, /* for 186 logicals */
150 ENTER, /* for 186 enter instr */
151 RMw, /* for 286 arpl instr */
152 Ib, /* for push immediate byte */
153 F, /* for 287 instructions */
154 FF, /* for 287 instructions */
155 FFC, /* for 287 instructions */
156 DM, /* 16-bit data */
157 AM, /* 16-bit addr */
158 LSEG, /* for 3-bit seg reg encoding */
159 MIb, /* for 386 logicals */
160 SREG, /* for 386 special registers */
161 PREFIX, /* a REP instruction prefix */
162 LOCK, /* a LOCK instruction prefix */
163 INT3, /* The int 3 instruction, which has a fake operand */
164 INTx, /* The normal int instruction, with explicit int num */
165 DSHIFTcl, /* for double shift that implicitly uses %cl */
166 CWD, /* so data16 can be evaluated for cwd and variants */
167 RET, /* single immediate 16-bit operand */
168 MOVZ, /* for movs and movz, with different size operands */
169 CRC32, /* for crc32, with different size operands */
170 XADDB, /* for xaddb */
171 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */
172 MOVBE, /* movbe instruction */
173
174 /*
175 * MMX/SIMD addressing modes.
176 */
177
178 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */
179 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */
180 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */
181 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */
182 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */
183 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */
184 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */
185 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */
186 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */
187 MMOSH, /* Prefixable MMX mm,imm8 */
188 MM, /* MMX/SIMD-Int mm/mem -> mm */
189 MMS, /* MMX/SIMD-Int mm -> mm/mem */
190 MMSH, /* MMX mm,imm8 */
191 XMMO, /* Prefixable SIMD xmm/mem -> xmm */
192 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */
193 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */
194 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */
195 XMMOX3, /* Prefixable SIMD xmm -> r32 */
196 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */
197 XMMOM, /* Prefixable SIMD xmm -> mem */
198 XMMOMS, /* Prefixable SIMD mem -> xmm */
199 XMM, /* SIMD xmm/mem -> xmm */
200 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */
201 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */
202 XMMXIMPL, /* SIMD xmm -> xmm (mem) */
203 XMM3P, /* SIMD xmm -> r32,imm8 */
204 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */
205 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */
206 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */
207 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */
208 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */
209 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */
210 XMMS, /* SIMD xmm -> xmm/mem */
211 XMMM, /* SIMD mem -> xmm */
212 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */
213 XMMMS, /* SIMD xmm -> mem */
214 XMM3MX, /* SIMD r32/mem -> xmm */
215 XMM3MXS, /* SIMD xmm -> r32/mem */
216 XMMSH, /* SIMD xmm,imm8 */
217 XMMXM3, /* SIMD xmm/mem -> r32 */
218 XMMX3, /* SIMD xmm -> r32 */
219 XMMXMM, /* SIMD xmm/mem -> mm */
220 XMMMX, /* SIMD mm -> xmm */
221 XMMXM, /* SIMD xmm -> mm */
222 XMMX2I, /* SIMD xmm -> xmm, imm, imm */
223 XMM2I, /* SIMD xmm, imm, imm */
224 XMMFENCE, /* SIMD lfence or mfence */
225 XMMSFNC, /* SIMD sfence (none or mem) */
226 XGETBV_XSETBV,
227 VEX_NONE, /* VEX no operand */
228 VEX_MO, /* VEX mod_rm -> implicit reg */
229 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
230 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */
231 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */
232 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */
233 VEX_MX, /* VEX mod_rm -> mod_reg */
234 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */
235 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
236 VEX_MR, /* VEX mod_rm -> mod_reg */
237 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */
238 VEX_RX, /* VEX mod_reg -> mod_rm */
239 VEX_RR, /* VEX mod_rm -> mod_reg */
240 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
241 VEX_RM, /* VEX mod_reg -> mod_rm */
242 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */
243 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
244 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
245 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */
246 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */
247 VMxo, /* VMx instruction with optional prefix */
248 SVM, /* AMD SVM instructions */
249 BLS, /* BLSR, BLSMSK, BLSI */
250 FMA, /* FMA instructions, all VEX_RMrX */
251 ADX /* ADX instructions, support REX.w, mod_rm->mod_reg */
252 };
253
254 /*
255 * VEX prefixes
256 */
257 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */
258 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */
259
260 #define FILL 0x90 /* Fill byte used for alignment (nop) */
261
262 /*
263 ** Register numbers for the i386
264 */
265 #define EAX_REGNO 0
266 #define ECX_REGNO 1
267 #define EDX_REGNO 2
268 #define EBX_REGNO 3
269 #define ESP_REGNO 4
270 #define EBP_REGNO 5
271 #define ESI_REGNO 6
272 #define EDI_REGNO 7
273
274 /*
275 * modes for immediate values
276 */
277 #define MODE_NONE 0
278 #define MODE_IPREL 1 /* signed IP relative value */
279 #define MODE_SIGNED 2 /* sign extended immediate */
280 #define MODE_IMPLIED 3 /* constant value implied from opcode */
281 #define MODE_OFFSET 4 /* offset part of an address */
282 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */
283
284 /*
285 * The letters used in these macros are:
286 * IND - indirect to another to another table
287 * "T" - means to Terminate indirections (this is the final opcode)
288 * "S" - means "operand length suffix required"
289 * "Sa" - means AVX2 suffix (d/q) required
290 * "NS" - means "no suffix" which is the operand length suffix of the opcode
291 * "Z" - means instruction size arg required
292 * "u" - means the opcode is invalid in IA32 but valid in amd64
293 * "x" - means the opcode is invalid in amd64, but not IA32
294 * "y" - means the operand size is always 64 bits in 64 bit mode
295 * "p" - means push/pop stack operation
296 * "vr" - means VEX instruction that operates on normal registers, not fpu
297 */
298
299 #if defined(DIS_TEXT) && defined(DIS_MEM)
300 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0, 0, 0}
301 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0, 0, 0}
302 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, 0}
303 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0, 0, 0}
304 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0, 0, 0}
305 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0, 0, 0}
306 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1, 0, 0}
307 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 0, 0}
308 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0, 0, 0}
309 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1, 0}
310 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0}
311 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0, 0, 0}
312 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0, 0, 0}
313 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1, 0, 0}
314 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 0}
315 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1}
316 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0, 0, 0}
317 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0, 0, 0}
318 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0, 0, 0, 0}
319 #elif defined(DIS_TEXT)
320 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
321 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
322 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0}
323 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0}
324 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0}
325 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0}
326 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1}
327 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
328 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
329 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1}
330 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
331 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
332 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
333 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
334 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
335 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1}
336 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
337 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
338 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
339 #elif defined(DIS_MEM)
340 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0}
341 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0}
342 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0}
343 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0, 0, 0}
344 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0, 0, 0}
345 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1, 0, 0}
346 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0, 0, 0}
347 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 0}
348 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0, 0, 0}
349 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1, 0}
350 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0}
351 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0, 0, 0}
352 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0, 0, 0}
353 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1, 0, 0}
354 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 0}
355 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1}
356 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0, 0 ,0}
357 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0, 0, 0}
358 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0, 0, 0}
359 #else
360 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0, 0}
361 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0, 0, 0}
362 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0}
363 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0, 0, 0}
364 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0, 0, 0}
365 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1, 0, 0}
366 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0, 0, 0}
367 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 0}
368 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0, 0, 0}
369 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1, 0}
370 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0}
371 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0, 0, 0}
372 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0, 0, 0}
373 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1, 0, 0}
374 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 0}
375 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1}
376 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0, 0, 0}
377 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0, 0, 0}
378 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0, 0}
379 #endif
380
381 #ifdef DIS_TEXT
382 /*
383 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
384 */
385 const char *const dis_addr16[3][8] = {
386 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
387 "(%bx)",
388 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
389 "(%bx)",
390 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
391 "(%bx)",
392 };
393
394
395 /*
396 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
397 */
398 const char *const dis_addr32_mode0[16] = {
399 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)",
400 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)"
401 };
402
403 const char *const dis_addr32_mode12[16] = {
404 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)",
405 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
406 };
407
408 /*
409 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
410 */
411 const char *const dis_addr64_mode0[16] = {
412 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)",
413 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
414 };
415 const char *const dis_addr64_mode12[16] = {
416 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)",
417 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
418 };
419
420 /*
421 * decode for scale from SIB byte
422 */
423 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
424
425 /*
426 * decode for scale from VSIB byte, note that we always include the scale factor
427 * to match gas.
428 */
429 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" };
430
431 /*
432 * register decoding for normal references to registers (ie. not addressing)
433 */
434 const char *const dis_REG8[16] = {
435 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
436 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
437 };
438
439 const char *const dis_REG8_REX[16] = {
440 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
441 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
442 };
443
444 const char *const dis_REG16[16] = {
445 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
446 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
447 };
448
449 const char *const dis_REG32[16] = {
450 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
451 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
452 };
453
454 const char *const dis_REG64[16] = {
455 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
456 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
457 };
458
459 const char *const dis_DEBUGREG[16] = {
460 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7",
461 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
462 };
463
464 const char *const dis_CONTROLREG[16] = {
465 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
466 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
467 };
468
469 const char *const dis_TESTREG[16] = {
470 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
471 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
472 };
473
474 const char *const dis_MMREG[16] = {
475 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
476 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
477 };
478
479 const char *const dis_XMMREG[16] = {
480 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
481 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15"
482 };
483
484 const char *const dis_YMMREG[16] = {
485 "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
486 "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15"
487 };
488
489 const char *const dis_SEGREG[16] = {
490 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
491 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
492 };
493
494 /*
495 * SIMD predicate suffixes
496 */
497 const char *const dis_PREDSUFFIX[8] = {
498 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
499 };
500
501 const char *const dis_AVXvgrp7[3][8] = {
502 /*0 1 2 3 4 5 6 7*/
503 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""},
504 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""},
505 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"}
506 };
507
508 #endif /* DIS_TEXT */
509
510 /*
511 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
512 */
513 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
514
515 /*
516 * "decode table" for pause and clflush instructions
517 */
518 const instable_t dis_opPause = TNS("pause", NORM);
519
520 /*
521 * Decode table for 0x0F00 opcodes
522 */
523 const instable_t dis_op0F00[8] = {
524
525 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M),
526 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID,
527 };
528
529
530 /*
531 * Decode table for 0x0F01 opcodes
532 */
533 const instable_t dis_op0F01[8] = {
534
535 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
536 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
537 };
538
539 /*
540 * Decode table for 0x0F18 opcodes -- SIMD prefetch
541 */
542 const instable_t dis_op0F18[8] = {
543
544 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
545 /* [4] */ INVALID, INVALID, INVALID, INVALID,
546 };
547
548 /*
549 * Decode table for 0x0FAE opcodes -- SIMD state save/restore
550 */
551 const instable_t dis_op0FAE[8] = {
552 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M),
553 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
554 };
555
556 /*
557 * Decode table for 0x0FBA opcodes
558 */
559
560 const instable_t dis_op0FBA[8] = {
561
562 /* [0] */ INVALID, INVALID, INVALID, INVALID,
563 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
564 };
565
566 /*
567 * Decode table for 0x0FC7 opcode (group 9)
568 */
569
570 const instable_t dis_op0FC7[8] = {
571
572 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID,
573 /* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9),
574 };
575
576 /*
577 * Decode table for 0x0FC7 opcode (group 9) mode 3
578 */
579
580 const instable_t dis_op0FC7m3[8] = {
581
582 /* [0] */ INVALID, INVALID, INVALID, INVALID,
583 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9),
584 };
585
586 /*
587 * Decode table for 0x0FC7 opcode with 0x66 prefix
588 */
589
590 const instable_t dis_op660FC7[8] = {
591
592 /* [0] */ INVALID, INVALID, INVALID, INVALID,
593 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID,
594 };
595
596 /*
597 * Decode table for 0x0FC7 opcode with 0xF3 prefix
598 */
599
600 const instable_t dis_opF30FC7[8] = {
601
602 /* [0] */ INVALID, INVALID, INVALID, INVALID,
603 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID,
604 };
605
606 /*
607 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
608 *
609 *bit pattern: 0000 1111 1100 1reg
610 */
611 const instable_t dis_op0FC8[4] = {
612 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID,
613 };
614
615 /*
616 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
617 */
618 const instable_t dis_op0F7123[4][8] = {
619 {
620 /* [70].0 */ INVALID, INVALID, INVALID, INVALID,
621 /* .4 */ INVALID, INVALID, INVALID, INVALID,
622 }, {
623 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID,
624 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID,
625 }, {
626 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID,
627 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID,
628 }, {
629 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH),
630 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH),
631 } };
632
633 /*
634 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
635 */
636 const instable_t dis_opSIMD7123[32] = {
637 /* [70].0 */ INVALID, INVALID, INVALID, INVALID,
638 /* .4 */ INVALID, INVALID, INVALID, INVALID,
639
640 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID,
641 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID,
642
643 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID,
644 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID,
645
646 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH),
647 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH),
648 };
649
650 /*
651 * SIMD instructions have been wedged into the existing IA32 instruction
652 * set through the use of prefixes. That is, while 0xf0 0x58 may be
653 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
654 * instruction - addss. At present, three prefixes have been coopted in
655 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
656 * following tables are used to provide the prefixed instruction names.
657 * The arrays are sparse, but they're fast.
658 */
659
660 /*
661 * Decode table for SIMD instructions with the address size (0x66) prefix.
662 */
663 const instable_t dis_opSIMDdata16[256] = {
664 /* [00] */ INVALID, INVALID, INVALID, INVALID,
665 /* [04] */ INVALID, INVALID, INVALID, INVALID,
666 /* [08] */ INVALID, INVALID, INVALID, INVALID,
667 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
668
669 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
670 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8),
671 /* [18] */ INVALID, INVALID, INVALID, INVALID,
672 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
673
674 /* [20] */ INVALID, INVALID, INVALID, INVALID,
675 /* [24] */ INVALID, INVALID, INVALID, INVALID,
676 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
677 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
678
679 /* [30] */ INVALID, INVALID, INVALID, INVALID,
680 /* [34] */ INVALID, INVALID, INVALID, INVALID,
681 /* [38] */ INVALID, INVALID, INVALID, INVALID,
682 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
683
684 /* [40] */ INVALID, INVALID, INVALID, INVALID,
685 /* [44] */ INVALID, INVALID, INVALID, INVALID,
686 /* [48] */ INVALID, INVALID, INVALID, INVALID,
687 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
688
689 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID,
690 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
691 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
692 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
693
694 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
695 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
696 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
697 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
698
699 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID,
700 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID,
701 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID,
702 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),
703
704 /* [80] */ INVALID, INVALID, INVALID, INVALID,
705 /* [84] */ INVALID, INVALID, INVALID, INVALID,
706 /* [88] */ INVALID, INVALID, INVALID, INVALID,
707 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
708
709 /* [90] */ INVALID, INVALID, INVALID, INVALID,
710 /* [94] */ INVALID, INVALID, INVALID, INVALID,
711 /* [98] */ INVALID, INVALID, INVALID, INVALID,
712 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
713
714 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
715 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
716 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
717 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
718
719 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
720 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
721 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
722 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
723
724 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID,
725 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID,
726 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
727 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
728
729 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16),
730 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3),
731 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
732 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
733
734 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
735 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
736 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16),
737 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
738
739 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16),
740 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
741 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
742 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID,
743 };
744
745 const instable_t dis_opAVX660F[256] = {
746 /* [00] */ INVALID, INVALID, INVALID, INVALID,
747 /* [04] */ INVALID, INVALID, INVALID, INVALID,
748 /* [08] */ INVALID, INVALID, INVALID, INVALID,
749 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
750
751 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
752 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
753 /* [18] */ INVALID, INVALID, INVALID, INVALID,
754 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
755
756 /* [20] */ INVALID, INVALID, INVALID, INVALID,
757 /* [24] */ INVALID, INVALID, INVALID, INVALID,
758 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16),
759 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
760
761 /* [30] */ INVALID, INVALID, INVALID, INVALID,
762 /* [34] */ INVALID, INVALID, INVALID, INVALID,
763 /* [38] */ INVALID, INVALID, INVALID, INVALID,
764 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
765
766 /* [40] */ INVALID, INVALID, INVALID, INVALID,
767 /* [44] */ INVALID, INVALID, INVALID, INVALID,
768 /* [48] */ INVALID, INVALID, INVALID, INVALID,
769 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
770
771 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID,
772 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
773 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
774 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
775
776 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
777 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
778 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
779 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
780
781 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
782 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
783 /* [78] */ INVALID, INVALID, INVALID, INVALID,
784 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
785
786 /* [80] */ INVALID, INVALID, INVALID, INVALID,
787 /* [84] */ INVALID, INVALID, INVALID, INVALID,
788 /* [88] */ INVALID, INVALID, INVALID, INVALID,
789 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
790
791 /* [90] */ INVALID, INVALID, INVALID, INVALID,
792 /* [94] */ INVALID, INVALID, INVALID, INVALID,
793 /* [98] */ INVALID, INVALID, INVALID, INVALID,
794 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
795
796 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
797 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
798 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
799 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
800
801 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
802 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
803 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
804 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
805
806 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID,
807 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID,
808 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
809 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
810
811 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
812 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
813 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
814 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
815
816 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
817 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
818 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
819 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
820
821 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
822 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
823 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
824 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID,
825 };
826
827 /*
828 * Decode table for SIMD instructions with the repnz (0xf2) prefix.
829 */
830 const instable_t dis_opSIMDrepnz[256] = {
831 /* [00] */ INVALID, INVALID, INVALID, INVALID,
832 /* [04] */ INVALID, INVALID, INVALID, INVALID,
833 /* [08] */ INVALID, INVALID, INVALID, INVALID,
834 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
835
836 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID,
837 /* [14] */ INVALID, INVALID, INVALID, INVALID,
838 /* [18] */ INVALID, INVALID, INVALID, INVALID,
839 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
840
841 /* [20] */ INVALID, INVALID, INVALID, INVALID,
842 /* [24] */ INVALID, INVALID, INVALID, INVALID,
843 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
844 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID,
845
846 /* [30] */ INVALID, INVALID, INVALID, INVALID,
847 /* [34] */ INVALID, INVALID, INVALID, INVALID,
848 /* [38] */ INVALID, INVALID, INVALID, INVALID,
849 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
850
851 /* [40] */ INVALID, INVALID, INVALID, INVALID,
852 /* [44] */ INVALID, INVALID, INVALID, INVALID,
853 /* [48] */ INVALID, INVALID, INVALID, INVALID,
854 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
855
856 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID,
857 /* [54] */ INVALID, INVALID, INVALID, INVALID,
858 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID,
859 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8),
860
861 /* [60] */ INVALID, INVALID, INVALID, INVALID,
862 /* [64] */ INVALID, INVALID, INVALID, INVALID,
863 /* [68] */ INVALID, INVALID, INVALID, INVALID,
864 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
865
866 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID,
867 /* [74] */ INVALID, INVALID, INVALID, INVALID,
868 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID,
869 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID,
870
871 /* [80] */ INVALID, INVALID, INVALID, INVALID,
872 /* [84] */ INVALID, INVALID, INVALID, INVALID,
873 /* [88] */ INVALID, INVALID, INVALID, INVALID,
874 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
875
876 /* [90] */ INVALID, INVALID, INVALID, INVALID,
877 /* [94] */ INVALID, INVALID, INVALID, INVALID,
878 /* [98] */ INVALID, INVALID, INVALID, INVALID,
879 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
880
881 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
882 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
883 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
884 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
885
886 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
887 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
888 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
889 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
890
891 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID,
892 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
893 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
894 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
895
896 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID,
897 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID,
898 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
899 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
900
901 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
902 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID,
903 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
904 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
905
906 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID,
907 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
908 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
909 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
910 };
911
912 const instable_t dis_opAVXF20F[256] = {
913 /* [00] */ INVALID, INVALID, INVALID, INVALID,
914 /* [04] */ INVALID, INVALID, INVALID, INVALID,
915 /* [08] */ INVALID, INVALID, INVALID, INVALID,
916 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
917
918 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID,
919 /* [14] */ INVALID, INVALID, INVALID, INVALID,
920 /* [18] */ INVALID, INVALID, INVALID, INVALID,
921 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
922
923 /* [20] */ INVALID, INVALID, INVALID, INVALID,
924 /* [24] */ INVALID, INVALID, INVALID, INVALID,
925 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
926 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID,
927
928 /* [30] */ INVALID, INVALID, INVALID, INVALID,
929 /* [34] */ INVALID, INVALID, INVALID, INVALID,
930 /* [38] */ INVALID, INVALID, INVALID, INVALID,
931 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
932
933 /* [40] */ INVALID, INVALID, INVALID, INVALID,
934 /* [44] */ INVALID, INVALID, INVALID, INVALID,
935 /* [48] */ INVALID, INVALID, INVALID, INVALID,
936 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
937
938 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID,
939 /* [54] */ INVALID, INVALID, INVALID, INVALID,
940 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
941 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
942
943 /* [60] */ INVALID, INVALID, INVALID, INVALID,
944 /* [64] */ INVALID, INVALID, INVALID, INVALID,
945 /* [68] */ INVALID, INVALID, INVALID, INVALID,
946 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
947
948 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID,
949 /* [74] */ INVALID, INVALID, INVALID, INVALID,
950 /* [78] */ INVALID, INVALID, INVALID, INVALID,
951 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID,
952
953 /* [80] */ INVALID, INVALID, INVALID, INVALID,
954 /* [84] */ INVALID, INVALID, INVALID, INVALID,
955 /* [88] */ INVALID, INVALID, INVALID, INVALID,
956 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
957
958 /* [90] */ INVALID, INVALID, INVALID, INVALID,
959 /* [94] */ INVALID, INVALID, INVALID, INVALID,
960 /* [98] */ INVALID, INVALID, INVALID, INVALID,
961 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
962
963 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
964 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
965 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
966 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
967
968 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
969 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
970 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
971 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
972
973 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID,
974 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
975 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
976 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
977
978 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID,
979 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
980 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
981 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
982
983 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
984 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
985 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
986 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
987
988 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID,
989 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
990 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
991 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
992 };
993
994 const instable_t dis_opAVXF20F3A[256] = {
995 /* [00] */ INVALID, INVALID, INVALID, INVALID,
996 /* [04] */ INVALID, INVALID, INVALID, INVALID,
997 /* [08] */ INVALID, INVALID, INVALID, INVALID,
998 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
999
1000 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1001 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1002 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1003 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1004
1005 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1006 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1007 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1008 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1009
1010 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1011 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1012 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1013 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1014
1015 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1016 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1017 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1018 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1019
1020 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1021 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1022 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1023 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1024
1025 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1026 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1027 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1028 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1029
1030 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1031 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1032 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1033 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1034
1035 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1036 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1037 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1038 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1039
1040 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1041 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1042 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1043 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1044
1045 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1046 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1047 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1048 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1049
1050 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1051 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1052 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1053 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1054
1055 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1056 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1057 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1058 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1059
1060 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1061 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1062 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1063 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1064
1065 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1066 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1067 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1068 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1069
1070 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID,
1071 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1072 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1073 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1074 };
1075
1076 const instable_t dis_opAVXF20F38[256] = {
1077 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1078 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1079 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1080 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1081
1082 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1083 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1084 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1085 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1086
1087 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1088 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1089 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1090 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1091
1092 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1093 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1094 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1095 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1096
1097 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1098 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1099 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1100 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1101
1102 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1103 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1104 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1105 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1106
1107 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1108 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1109 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1110 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1111
1112 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1113 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1114 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1115 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1116
1117 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1118 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1119 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1120 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1121
1122 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1123 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1124 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1125 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1126
1127 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1128 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1129 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1130 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1131
1132 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1133 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1134 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1135 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1136
1137 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1138 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1139 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1140 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1141
1142 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1143 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1144 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1145 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1146
1147 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1148 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1149 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1150 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1151
1152 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1153 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1154 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1155 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1156 };
1157
1158 const instable_t dis_opAVXF30F38[256] = {
1159 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1160 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1161 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1162 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1163
1164 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1165 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1166 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1167 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1168
1169 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1170 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1171 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1172 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1173
1174 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1175 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1176 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1177 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1178
1179 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1180 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1181 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1182 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1183
1184 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1185 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1186 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1187 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1188
1189 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1190 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1191 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1192 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1193
1194 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1195 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1196 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1197 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1198
1199 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1200 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1201 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1202 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1203
1204 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1205 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1206 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1207 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1208
1209 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1210 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1211 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1212 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1213
1214 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1215 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1216 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1217 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1218
1219 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1220 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1221 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1222 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1223
1224 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1225 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1226 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1227 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1228
1229 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1230 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1231 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1232 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1233
1234 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1235 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5),
1236 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1237 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1238 };
1239 /*
1240 * Decode table for SIMD instructions with the repz (0xf3) prefix.
1241 */
1242 const instable_t dis_opSIMDrepz[256] = {
1243 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1244 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1245 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1246 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1247
1248 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID,
1249 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID,
1250 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1251 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1252
1253 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1254 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1255 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
1256 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID,
1257
1258 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1259 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1260 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1261 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1262
1263 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1264 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1265 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1266 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1267
1268 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4),
1269 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1270 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
1271 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4),
1272
1273 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1274 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1275 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1276 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16),
1277
1278 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID,
1279 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1280 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1281 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16),
1282
1283 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1284 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1285 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1286 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1287
1288 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1289 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1290 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1291 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1292
1293 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1294 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1295 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1296 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1297
1298 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1299 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1300 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID,
1301 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID,
1302
1303 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID,
1304 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1305 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1306 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1307
1308 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1309 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID,
1310 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1311 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1312
1313 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1314 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID,
1315 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1316 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1317
1318 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1319 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1320 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1321 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1322 };
1323
1324 const instable_t dis_opAVXF30F[256] = {
1325 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1326 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1327 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1328 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1329
1330 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID,
1331 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID,
1332 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1333 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1334
1335 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1336 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1337 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
1338 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID,
1339
1340 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1341 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1342 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1343 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1344
1345 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1346 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1347 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1348 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1349
1350 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4),
1351 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1352 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16),
1353 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4),
1354
1355 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1356 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1357 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1358 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16),
1359
1360 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID,
1361 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1362 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1363 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16),
1364
1365 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1366 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1367 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1368 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1369
1370 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1371 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1372 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1373 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1374
1375 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1376 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1377 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1378 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1379
1380 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1381 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1382 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1383 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1384
1385 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID,
1386 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1387 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1388 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1389
1390 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1391 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1392 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1393 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1394
1395 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1396 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID,
1397 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1398 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1399
1400 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1401 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1402 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1403 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1404 };
1405 /*
1406 * The following two tables are used to encode crc32 and movbe
1407 * since they share the same opcodes.
1408 */
1409 const instable_t dis_op0F38F0[2] = {
1410 /* [00] */ TNS("crc32b",CRC32),
1411 TS("movbe",MOVBE),
1412 };
1413
1414 const instable_t dis_op0F38F1[2] = {
1415 /* [00] */ TS("crc32",CRC32),
1416 TS("movbe",MOVBE),
1417 };
1418
1419 /*
1420 * The following table is used to distinguish between adox and adcx which share
1421 * the same opcodes.
1422 */
1423 const instable_t dis_op0F38F6[2] = {
1424 /* [00] */ TNS("adcx",ADX),
1425 TNS("adox",ADX),
1426 };
1427
1428 const instable_t dis_op0F38[256] = {
1429 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1430 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1431 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1432 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1433
1434 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID,
1435 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16),
1436 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1437 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
1438
1439 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1440 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID,
1441 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1442 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1443
1444 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
1445 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16),
1446 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
1447 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
1448
1449 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID,
1450 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1451 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1452 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1453
1454 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1455 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1456 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1457 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1458
1459 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1460 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1461 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1462 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1463
1464 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1465 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1466 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1467 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1468
1469 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID,
1470 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1471 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1472 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1473
1474 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1475 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1476 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1477 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1478
1479 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1480 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1481 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1482 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1483
1484 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1485 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1486 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1487 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1488
1489 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1490 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1491 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
1492 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, INVALID,
1493
1494 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1495 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1496 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16),
1497 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
1498
1499 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1500 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1501 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1502 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1503 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
1504 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID,
1505 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1506 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1507 };
1508
1509 const instable_t dis_opAVX660F38[256] = {
1510 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1511 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1512 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1513 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1514
1515 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16),
1516 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16),
1517 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1518 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
1519
1520 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1521 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID,
1522 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1523 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
1524
1525 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
1526 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
1527 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
1528 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
1529
1530 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID,
1531 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
1532 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1533 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1534
1535 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1536 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1537 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
1538 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1539
1540 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1541 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1542 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1543 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1544
1545 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1546 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1547 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID,
1548 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1549
1550 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1551 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1552 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1553 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID,
1554
1555 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
1556 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
1557 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
1558 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
1559
1560 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1561 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
1562 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
1563 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
1564
1565 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1566 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
1567 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
1568 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
1569
1570 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1571 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1572 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1573 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1574
1575 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1576 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1577 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16),
1578 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
1579
1580 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1581 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1582 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1583 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1584 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
1585 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5),
1586 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1587 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1588 };
1589
1590 const instable_t dis_op0F3A[256] = {
1591 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1592 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1593 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
1594 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
1595
1596 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1597 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
1598 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1599 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1600
1601 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
1602 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1603 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1604 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1605
1606 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1607 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1608 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1609 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1610
1611 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
1612 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID,
1613 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1614 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1615
1616 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1617 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1618 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1619 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1620
1621 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
1622 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1623 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1624 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1625
1626 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1627 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1628 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1629 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1630
1631 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1632 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1633 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1634 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1635
1636 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1637 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1638 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1639 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1640
1641 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1642 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1643 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1644 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1645
1646 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1647 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1648 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1649 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1650
1651 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1652 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1653 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1654 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, INVALID, INVALID,
1655
1656 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1657 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1658 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1659 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16),
1660
1661 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1662 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1663 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1664 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1665
1666 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1667 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1668 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1669 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1670 };
1671
1672 const instable_t dis_opAVX660F3A[256] = {
1673 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
1674 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1675 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1676 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1677
1678 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1679 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1680 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
1681 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID,
1682
1683 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1684 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1685 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1686 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1687
1688 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1689 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1690 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID,
1691 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1692
1693 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
1694 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID,
1695 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16),
1696 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID,
1697
1698 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1699 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1700 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1701 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1702
1703 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
1704 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1705 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1706 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1707
1708 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1709 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1710 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1711 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1712
1713 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1714 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1715 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1716 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1717
1718 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1719 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1720 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1721 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1722
1723 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1724 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1725 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1726 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1727
1728 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1729 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1730 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1731 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1732
1733 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1734 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1735 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1736 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1737
1738 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1739 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1740 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1741 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16),
1742
1743 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1744 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1745 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1746 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1747
1748 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1749 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1750 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1751 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1752 };
1753
1754 /*
1755 * Decode table for 0x0F0D which uses the first byte of the mod_rm to
1756 * indicate a sub-code.
1757 */
1758 const instable_t dis_op0F0D[8] = {
1759 /* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID,
1760 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1761 };
1762
1763 /*
1764 * Decode table for 0x0F opcodes
1765 */
1766
1767 const instable_t dis_op0F[16][16] = {
1768 {
1769 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR),
1770 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM),
1771 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM),
1772 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID,
1773 }, {
1774 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1775 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1776 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
1777 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw),
1778 }, {
1779 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
1780 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
1781 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1782 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1783 }, {
1784 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM),
1785 /* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID,
1786 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1787 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1788 }, {
1789 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR),
1790 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR),
1791 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR),
1792 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR),
1793 }, {
1794 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
1795 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16),
1796 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
1797 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16),
1798 }, {
1799 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1800 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1801 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1802 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1803 }, {
1804 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
1805 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1806 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID,
1807 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
1808 }, {
1809 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
1810 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D),
1811 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D),
1812 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D),
1813 }, {
1814 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb),
1815 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb),
1816 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb),
1817 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb),
1818 }, {
1819 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw),
1820 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID,
1821 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw),
1822 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw),
1823 }, {
1824 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw),
1825 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ),
1826 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw),
1827 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ),
1828 }, {
1829 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
1830 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
1831 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1832 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1833 }, {
1834 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8),
1835 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3),
1836 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8),
1837 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8),
1838 }, {
1839 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8),
1840 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8),
1841 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8),
1842 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8),
1843 }, {
1844 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8),
1845 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8),
1846 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8),
1847 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID,
1848 } };
1849
1850 const instable_t dis_opAVX0F[16][16] = {
1851 {
1852 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1853 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1854 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1855 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1856 }, {
1857 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8),
1858 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
1859 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1860 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1861 }, {
1862 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1863 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1864 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16),
1865 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
1866 }, {
1867 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1868 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1869 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1870 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1871 }, {
1872 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1873 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1874 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1875 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1876 }, {
1877 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
1878 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16),
1879 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
1880 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16),
1881 }, {
1882 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1883 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1884 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1885 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1886 }, {
1887 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1888 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE),
1889 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1890 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1891 }, {
1892 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1893 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1894 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1895 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1896 }, {
1897 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1898 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1899 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1900 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1901 }, {
1902 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1903 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1904 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1905 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID,
1906 }, {
1907 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1908 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1909 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1910 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1911 }, {
1912 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID,
1913 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID,
1914 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1915 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1916 }, {
1917 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1918 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1919 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1920 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1921 }, {
1922 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1923 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1924 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1925 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1926 }, {
1927 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5),
1928 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5),
1929 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1930 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1931 } };
1932
1933 /*
1934 * Decode table for 0x80 opcodes
1935 */
1936
1937 const instable_t dis_op80[8] = {
1938
1939 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw),
1940 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw),
1941 };
1942
1943
1944 /*
1945 * Decode table for 0x81 opcodes.
1946 */
1947
1948 const instable_t dis_op81[8] = {
1949
1950 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw),
1951 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw),
1952 };
1953
1954
1955 /*
1956 * Decode table for 0x82 opcodes.
1957 */
1958
1959 const instable_t dis_op82[8] = {
1960
1961 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw),
1962 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw),
1963 };
1964 /*
1965 * Decode table for 0x83 opcodes.
1966 */
1967
1968 const instable_t dis_op83[8] = {
1969
1970 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw),
1971 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw),
1972 };
1973
1974 /*
1975 * Decode table for 0xC0 opcodes.
1976 */
1977
1978 const instable_t dis_opC0[8] = {
1979
1980 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI),
1981 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI),
1982 };
1983
1984 /*
1985 * Decode table for 0xD0 opcodes.
1986 */
1987
1988 const instable_t dis_opD0[8] = {
1989
1990 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
1991 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
1992 };
1993
1994 /*
1995 * Decode table for 0xC1 opcodes.
1996 * 186 instruction set
1997 */
1998
1999 const instable_t dis_opC1[8] = {
2000
2001 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI),
2002 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI),
2003 };
2004
2005 /*
2006 * Decode table for 0xD1 opcodes.
2007 */
2008
2009 const instable_t dis_opD1[8] = {
2010
2011 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
2012 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv),
2013 };
2014
2015
2016 /*
2017 * Decode table for 0xD2 opcodes.
2018 */
2019
2020 const instable_t dis_opD2[8] = {
2021
2022 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
2023 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
2024 };
2025 /*
2026 * Decode table for 0xD3 opcodes.
2027 */
2028
2029 const instable_t dis_opD3[8] = {
2030
2031 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
2032 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv),
2033 };
2034
2035
2036 /*
2037 * Decode table for 0xF6 opcodes.
2038 */
2039
2040 const instable_t dis_opF6[8] = {
2041
2042 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw),
2043 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA),
2044 };
2045
2046
2047 /*
2048 * Decode table for 0xF7 opcodes.
2049 */
2050
2051 const instable_t dis_opF7[8] = {
2052
2053 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw),
2054 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA),
2055 };
2056
2057
2058 /*
2059 * Decode table for 0xFE opcodes.
2060 */
2061
2062 const instable_t dis_opFE[8] = {
2063
2064 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID,
2065 /* [4] */ INVALID, INVALID, INVALID, INVALID,
2066 };
2067 /*
2068 * Decode table for 0xFF opcodes.
2069 */
2070
2071 const instable_t dis_opFF[8] = {
2072
2073 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM),
2074 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID,
2075 };
2076
2077 /* for 287 instructions, which are a mess to decode */
2078
2079 const instable_t dis_opFP1n2[8][8] = {
2080 {
2081 /* bit pattern: 1101 1xxx MODxx xR/M */
2082 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M),
2083 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M),
2084 }, {
2085 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M),
2086 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2),
2087 }, {
2088 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M),
2089 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M),
2090 }, {
2091 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M),
2092 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10),
2093 }, {
2094 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8),
2095 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8),
2096 }, {
2097 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8),
2098 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2),
2099 }, {
2100 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2),
2101 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2),
2102 }, {
2103 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2),
2104 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8),
2105 } };
2106
2107 const instable_t dis_opFP3[8][8] = {
2108 {
2109 /* bit pattern: 1101 1xxx 11xx xREG */
2110 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
2111 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
2112 }, {
2113 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F),
2114 /* [1,4] */ INVALID, INVALID, INVALID, INVALID,
2115 }, {
2116 /* [2,0] */ INVALID, INVALID, INVALID, INVALID,
2117 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID,
2118 }, {
2119 /* [3,0] */ INVALID, INVALID, INVALID, INVALID,
2120 /* [3,4] */ INVALID, INVALID, INVALID, INVALID,
2121 }, {
2122 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
2123 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
2124 }, {
2125 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F),
2126 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID,
2127 }, {
2128 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM),
2129 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF),
2130 }, {
2131 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F),
2132 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID,
2133 } };
2134
2135 const instable_t dis_opFP4[4][8] = {
2136 {
2137 /* bit pattern: 1101 1001 111x xxxx */
2138 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID,
2139 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID,
2140 }, {
2141 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM),
2142 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID,
2143 }, {
2144 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM),
2145 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM),
2146 }, {
2147 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM),
2148 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM),
2149 } };
2150
2151 const instable_t dis_opFP5[8] = {
2152 /* bit pattern: 1101 1011 111x xxxx */
2153 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM),
2154 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID,
2155 };
2156
2157 const instable_t dis_opFP6[8] = {
2158 /* bit pattern: 1101 1011 11yy yxxx */
2159 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF),
2160 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID,
2161 };
2162
2163 const instable_t dis_opFP7[8] = {
2164 /* bit pattern: 1101 1010 11yy yxxx */
2165 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF),
2166 /* [04] */ INVALID, INVALID, INVALID, INVALID,
2167 };
2168
2169 /*
2170 * Main decode table for the op codes. The first two nibbles
2171 * will be used as an index into the table. If there is a
2172 * a need to further decode an instruction, the array to be
2173 * referenced is indicated with the other two entries being
2174 * empty.
2175 */
2176
2177 const instable_t dis_distable[16][16] = {
2178 {
2179 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw),
2180 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG),
2181 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw),
2182 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F),
2183 }, {
2184 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw),
2185 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG),
2186 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw),
2187 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
2188 }, {
2189 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
2190 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNS("%es:",OVERRIDE), TNSx("daa",NORM),
2191 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
2192 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
2193 }, {
2194 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
2195 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNS("%ss:",OVERRIDE), TNSx("aaa",NORM),
2196 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
2197 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNS("%ds:",OVERRIDE), TNSx("aas",NORM),
2198 }, {
2199 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
2200 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
2201 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
2202 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
2203 }, {
2204 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
2205 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
2206 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
2207 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
2208 }, {
2209 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw),
2210 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM),
2211 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL),
2212 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2213 }, {
2214 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD),
2215 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD),
2216 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD),
2217 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD),
2218 }, {
2219 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83),
2220 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw),
2221 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw),
2222 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M),
2223 }, {
2224 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
2225 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
2226 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM),
2227 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM),
2228 }, {
2229 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO),
2230 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD),
2231 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD),
2232 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD),
2233 }, {
2234 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2235 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2236 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
2237 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
2238 }, {
2239 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM),
2240 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw),
2241 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM),
2242 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM),
2243 }, {
2244 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3),
2245 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1),
2246
2247 /* 287 instructions. Note that although the indirect field */
2248 /* indicates opFP1n2 for further decoding, this is not necessarily */
2249 /* the case since the opFP arrays are not partitioned according to key1 */
2250 /* and key2. opFP1n2 is given only to indicate that we haven't */
2251 /* finished decoding the instruction. */
2252 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
2253 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
2254 }, {
2255 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD),
2256 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P),
2257 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD),
2258 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V),
2259 }, {
2260 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX),
2261 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7),
2262 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM),
2263 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF),
2264 } };
2265
2266 /* END CSTYLED */
2267
2268 /*
2269 * common functions to decode and disassemble an x86 or amd64 instruction
2270 */
2271
2272 /*
2273 * These are the individual fields of a REX prefix. Note that a REX
2274 * prefix with none of these set is still needed to:
2275 * - use the MOVSXD (sign extend 32 to 64 bits) instruction
2276 * - access the %sil, %dil, %bpl, %spl registers
2277 */
2278 #define REX_W 0x08 /* 64 bit operand size when set */
2279 #define REX_R 0x04 /* high order bit extension of ModRM reg field */
2280 #define REX_X 0x02 /* high order bit extension of SIB index field */
2281 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */
2282
2283 /*
2284 * These are the individual fields of a VEX prefix.
2285 */
2286 #define VEX_R 0x08 /* REX.R in 1's complement form */
2287 #define VEX_X 0x04 /* REX.X in 1's complement form */
2288 #define VEX_B 0x02 /* REX.B in 1's complement form */
2289 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
2290 #define VEX_L 0x04
2291 #define VEX_W 0x08 /* opcode specific, use like REX.W */
2292 #define VEX_m 0x1F /* VEX m-mmmm field */
2293 #define VEX_v 0x78 /* VEX register specifier */
2294 #define VEX_p 0x03 /* VEX pp field, opcode extension */
2295
2296 /* VEX m-mmmm field, only used by three bytes prefix */
2297 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */
2298 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
2299 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
2300
2301 /* VEX pp field, providing equivalent functionality of a SIMD prefix */
2302 #define VEX_p_66 0x01
2303 #define VEX_p_F3 0x02
2304 #define VEX_p_F2 0x03
2305
2306 /*
2307 * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2308 */
2309 static int isize[] = {1, 2, 4, 4};
2310 static int isize64[] = {1, 2, 4, 8};
2311
2312 /*
2313 * Just a bunch of useful macros.
2314 */
2315 #define WBIT(x) (x & 0x1) /* to get w bit */
2316 #define REGNO(x) (x & 0x7) /* to get 3 bit register */
2317 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */
2318 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2319 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2320
2321 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */
2322
2323 #define BYTE_OPND 0 /* w-bit value indicating byte register */
2324 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */
2325 #define MM_OPND 2 /* "value" used to indicate a mmx reg */
2326 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */
2327 #define SEG_OPND 4 /* "value" used to indicate a segment reg */
2328 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */
2329 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */
2330 #define TEST_OPND 7 /* "value" used to indicate a test reg */
2331 #define WORD_OPND 8 /* w-bit value indicating word size reg */
2332 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */
2333
2334 /*
2335 * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
2336 * there's not really a consistent scheme that we can use to know what the mode
2337 * is supposed to be for a given type. Various instructions, like VPGATHERDD,
2338 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
2339 * some registers match VEX_L, but the VSIB is always XMM.
2340 *
2341 * The simplest way to deal with this is to just define a table based on the
2342 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
2343 * them.
2344 *
2345 * We further have to subdivide this based on the value of VEX_W and the value
2346 * of VEX_L. The array is constructed to be indexed as:
2347 * [opcode - 0x90][VEX_W][VEX_L].
2348 */
2349 /* w = 0, 0x90 */
2350 typedef struct dis_gather_regs {
2351 uint_t dgr_arg0; /* src reg */
2352 uint_t dgr_arg1; /* vsib reg */
2353 uint_t dgr_arg2; /* dst reg */
2354 const char *dgr_suffix; /* suffix to append */
2355 } dis_gather_regs_t;
2356
2357 static dis_gather_regs_t dis_vgather[4][2][2] = {
2358 {
2359 /* op 0x90, W.0 */
2360 {
2361 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2362 { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2363 },
2364 /* op 0x90, W.1 */
2365 {
2366 { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2367 { YMM_OPND, XMM_OPND, YMM_OPND, "q" }
2368 }
2369 },
2370 {
2371 /* op 0x91, W.0 */
2372 {
2373 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2374 { XMM_OPND, YMM_OPND, XMM_OPND, "d" },
2375 },
2376 /* op 0x91, W.1 */
2377 {
2378 { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2379 { YMM_OPND, YMM_OPND, YMM_OPND, "q" },
2380 }
2381 },
2382 {
2383 /* op 0x92, W.0 */
2384 {
2385 { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2386 { YMM_OPND, YMM_OPND, YMM_OPND, "s" }
2387 },
2388 /* op 0x92, W.1 */
2389 {
2390 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2391 { YMM_OPND, XMM_OPND, YMM_OPND, "d" }
2392 }
2393 },
2394 {
2395 /* op 0x93, W.0 */
2396 {
2397 { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2398 { XMM_OPND, YMM_OPND, XMM_OPND, "s" }
2399 },
2400 /* op 0x93, W.1 */
2401 {
2402 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2403 { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2404 }
2405 }
2406 };
2407
2408 /*
2409 * Get the next byte and separate the op code into the high and low nibbles.
2410 */
2411 static int
2412 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)
2413 {
2414 int byte;
2415
2416 /*
2417 * x86 instructions have a maximum length of 15 bytes. Bail out if
2418 * we try to read more.
2419 */
2420 if (x->d86_len >= 15)
2421 return (x->d86_error = 1);
2422
2423 if (x->d86_error)
2424 return (1);
2425 byte = x->d86_get_byte(x->d86_data);
2426 if (byte < 0)
2427 return (x->d86_error = 1);
2428 x->d86_bytes[x->d86_len++] = byte;
2429 *low = byte & 0xf; /* ----xxxx low 4 bits */
2430 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */
2431 return (0);
2432 }
2433
2434 /*
2435 * Get and decode an SIB (scaled index base) byte
2436 */
2437 static void
2438 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)
2439 {
2440 int byte;
2441
2442 if (x->d86_error)
2443 return;
2444
2445 byte = x->d86_get_byte(x->d86_data);
2446 if (byte < 0) {
2447 x->d86_error = 1;
2448 return;
2449 }
2450 x->d86_bytes[x->d86_len++] = byte;
2451
2452 *base = byte & 0x7;
2453 *index = (byte >> 3) & 0x7;
2454 *ss = (byte >> 6) & 0x3;
2455 }
2456
2457 /*
2458 * Get the byte following the op code and separate it into the
2459 * mode, register, and r/m fields.
2460 */
2461 static void
2462 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
2463 {
2464 if (x->d86_got_modrm == 0) {
2465 if (x->d86_rmindex == -1)
2466 x->d86_rmindex = x->d86_len;
2467 dtrace_get_SIB(x, mode, reg, r_m);
2468 x->d86_got_modrm = 1;
2469 }
2470 }
2471
2472 /*
2473 * Adjust register selection based on any REX prefix bits present.
2474 */
2475 /*ARGSUSED*/
2476 static void
2477 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
2478 {
2479 #pragma unused (mode)
2480 if (reg != NULL && r_m == NULL) {
2481 if (rex_prefix & REX_B)
2482 *reg += 8;
2483 } else {
2484 if (reg != NULL && (REX_R & rex_prefix) != 0)
2485 *reg += 8;
2486 if (r_m != NULL && (REX_B & rex_prefix) != 0)
2487 *r_m += 8;
2488 }
2489 }
2490
2491 /*
2492 * Adjust register selection based on any VEX prefix bits present.
2493 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
2494 */
2495 /*ARGSUSED*/
2496 static void
2497 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
2498 {
2499 #pragma unused (mode)
2500 if (reg != NULL && r_m == NULL) {
2501 if (!(vex_byte1 & VEX_B))
2502 *reg += 8;
2503 } else {
2504 if (reg != NULL && ((VEX_R & vex_byte1) == 0))
2505 *reg += 8;
2506 if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
2507 *r_m += 8;
2508 }
2509 }
2510
2511 /*
2512 * Get an immediate operand of the given size, with sign extension.
2513 */
2514 static void
2515 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
2516 {
2517 int i;
2518 int byte;
2519 int valsize = 0;
2520
2521 if (x->d86_numopnds < (uint_t)opindex + 1)
2522 x->d86_numopnds = (uint_t)opindex + 1;
2523
2524 switch (wbit) {
2525 case BYTE_OPND:
2526 valsize = 1;
2527 break;
2528 case LONG_OPND:
2529 if (x->d86_opnd_size == SIZE16)
2530 valsize = 2;
2531 else if (x->d86_opnd_size == SIZE32)
2532 valsize = 4;
2533 else
2534 valsize = 8;
2535 break;
2536 case MM_OPND:
2537 case XMM_OPND:
2538 case YMM_OPND:
2539 case SEG_OPND:
2540 case CONTROL_OPND:
2541 case DEBUG_OPND:
2542 case TEST_OPND:
2543 valsize = size;
2544 break;
2545 case WORD_OPND:
2546 valsize = 2;
2547 break;
2548 }
2549 if (valsize < size)
2550 valsize = size;
2551
2552 if (x->d86_error)
2553 return;
2554 x->d86_opnd[opindex].d86_value = 0;
2555 for (i = 0; i < size; ++i) {
2556 byte = x->d86_get_byte(x->d86_data);
2557 if (byte < 0) {
2558 x->d86_error = 1;
2559 return;
2560 }
2561 x->d86_bytes[x->d86_len++] = byte;
2562 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8);
2563 }
2564 /* Do sign extension */
2565 if (x->d86_bytes[x->d86_len - 1] & 0x80) {
2566 for (; i < (int)sizeof (uint64_t); i++)
2567 x->d86_opnd[opindex].d86_value |=
2568 (uint64_t)0xff << (i * 8);
2569 }
2570 #ifdef DIS_TEXT
2571 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2572 x->d86_opnd[opindex].d86_value_size = valsize;
2573 x->d86_imm_bytes += size;
2574 #endif
2575 }
2576
2577 /*
2578 * Get an ip relative operand of the given size, with sign extension.
2579 */
2580 static void
2581 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex)
2582 {
2583 dtrace_imm_opnd(x, wbit, size, opindex);
2584 #ifdef DIS_TEXT
2585 x->d86_opnd[opindex].d86_mode = MODE_IPREL;
2586 #endif
2587 }
2588
2589 /*
2590 * Check to see if there is a segment override prefix pending.
2591 * If so, print it in the current 'operand' location and set
2592 * the override flag back to false.
2593 */
2594 /*ARGSUSED*/
2595 static void
2596 dtrace_check_override(dis86_t *x, int opindex)
2597 {
2598 #ifdef DIS_TEXT
2599 if (x->d86_seg_prefix) {
2600 (void) strlcat(x->d86_opnd[opindex].d86_prefix,
2601 x->d86_seg_prefix, PFIXLEN);
2602 }
2603 #else
2604 #pragma unused (opindex)
2605 #endif
2606 x->d86_seg_prefix = NULL;
2607 }
2608
2609
2610 /*
2611 * Process a single instruction Register or Memory operand.
2612 *
2613 * mode = addressing mode from ModRM byte
2614 * r_m = r_m (or reg if mode == 3) field from ModRM byte
2615 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
2616 * o = index of operand that we are processing (0, 1 or 2)
2617 *
2618 * the value of reg or r_m must have already been adjusted for any REX prefix.
2619 */
2620 /*ARGSUSED*/
2621 static void
2622 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
2623 {
2624 int have_SIB = 0; /* flag presence of scale-index-byte */
2625 uint_t ss; /* scale-factor from opcode */
2626 uint_t index; /* index register number */
2627 uint_t base; /* base register number */
2628 int dispsize; /* size of displacement in bytes */
2629 #ifdef DIS_TEXT
2630 char *opnd = x->d86_opnd[opindex].d86_opnd;
2631 #else
2632 #pragma unused (wbit)
2633 #endif
2634
2635 if (x->d86_numopnds < (uint_t)opindex + 1)
2636 x->d86_numopnds = (uint_t)opindex + 1;
2637
2638 if (x->d86_error)
2639 return;
2640
2641 /*
2642 * first handle a simple register
2643 */
2644 if (mode == REG_ONLY) {
2645 #ifdef DIS_TEXT
2646 switch (wbit) {
2647 case MM_OPND:
2648 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN);
2649 break;
2650 case XMM_OPND:
2651 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
2652 break;
2653 case YMM_OPND:
2654 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
2655 break;
2656 case SEG_OPND:
2657 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
2658 break;
2659 case CONTROL_OPND:
2660 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN);
2661 break;
2662 case DEBUG_OPND:
2663 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN);
2664 break;
2665 case TEST_OPND:
2666 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN);
2667 break;
2668 case BYTE_OPND:
2669 if (x->d86_rex_prefix == 0)
2670 (void) strlcat(opnd, dis_REG8[r_m], OPLEN);
2671 else
2672 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN);
2673 break;
2674 case WORD_OPND:
2675 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2676 break;
2677 case LONG_OPND:
2678 if (x->d86_opnd_size == SIZE16)
2679 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2680 else if (x->d86_opnd_size == SIZE32)
2681 (void) strlcat(opnd, dis_REG32[r_m], OPLEN);
2682 else
2683 (void) strlcat(opnd, dis_REG64[r_m], OPLEN);
2684 break;
2685 }
2686 #endif /* DIS_TEXT */
2687 return;
2688 }
2689
2690 /*
2691 * if symbolic representation, skip override prefix, if any
2692 */
2693 dtrace_check_override(x, opindex);
2694
2695 /*
2696 * Handle 16 bit memory references first, since they decode
2697 * the mode values more simply.
2698 * mode 1 is r_m + 8 bit displacement
2699 * mode 2 is r_m + 16 bit displacement
2700 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
2701 */
2702 if (x->d86_addr_size == SIZE16) {
2703 if ((mode == 0 && r_m == 6) || mode == 2)
2704 dtrace_imm_opnd(x, WORD_OPND, 2, opindex);
2705 else if (mode == 1)
2706 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex);
2707 #ifdef DIS_TEXT
2708 if (mode == 0 && r_m == 6)
2709 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2710 else if (mode == 0)
2711 x->d86_opnd[opindex].d86_mode = MODE_NONE;
2712 else
2713 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2714 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN);
2715 #endif
2716 return;
2717 }
2718
2719 /*
2720 * 32 and 64 bit addressing modes are more complex since they
2721 * can involve an SIB (scaled index and base) byte to decode.
2722 */
2723 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) {
2724 have_SIB = 1;
2725 dtrace_get_SIB(x, &ss, &index, &base);
2726 if (x->d86_error)
2727 return;
2728 if (base != 5 || mode != 0)
2729 if (x->d86_rex_prefix & REX_B)
2730 base += 8;
2731 if (x->d86_rex_prefix & REX_X)
2732 index += 8;
2733 } else {
2734 base = r_m;
2735 }
2736
2737 /*
2738 * Compute the displacement size and get its bytes
2739 */
2740 dispsize = 0;
2741
2742 if (mode == 1)
2743 dispsize = 1;
2744 else if (mode == 2)
2745 dispsize = 4;
2746 else if ((r_m & 7) == EBP_REGNO ||
2747 (have_SIB && (base & 7) == EBP_REGNO))
2748 dispsize = 4;
2749
2750 if (dispsize > 0) {
2751 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND,
2752 dispsize, opindex);
2753 if (x->d86_error)
2754 return;
2755 }
2756
2757 #ifdef DIS_TEXT
2758 if (dispsize > 0)
2759 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2760
2761 if (have_SIB == 0) {
2762 if (x->d86_mode == SIZE32) {
2763 if (mode == 0)
2764 (void) strlcat(opnd, dis_addr32_mode0[r_m],
2765 OPLEN);
2766 else
2767 (void) strlcat(opnd, dis_addr32_mode12[r_m],
2768 OPLEN);
2769 } else {
2770 if (mode == 0) {
2771 (void) strlcat(opnd, dis_addr64_mode0[r_m],
2772 OPLEN);
2773 if (r_m == 5) {
2774 x->d86_opnd[opindex].d86_mode =
2775 MODE_RIPREL;
2776 }
2777 } else {
2778 (void) strlcat(opnd, dis_addr64_mode12[r_m],
2779 OPLEN);
2780 }
2781 }
2782 } else {
2783 uint_t need_paren = 0;
2784 char **regs;
2785 char **bregs;
2786 const char *const *sf;
2787 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
2788 regs = (char **)dis_REG32;
2789 else
2790 regs = (char **)dis_REG64;
2791
2792 if (x->d86_vsib != 0) {
2793 if (wbit == YMM_OPND) /* NOTE this is not addr_size! */
2794 bregs = (char **)dis_YMMREG;
2795 else
2796 bregs = (char **)dis_XMMREG;
2797 sf = dis_vscale_factor;
2798 } else {
2799 bregs = regs;
2800 sf = dis_scale_factor;
2801 }
2802
2803 /*
2804 * print the base (if any)
2805 */
2806 if (base == EBP_REGNO && mode == 0) {
2807 if (index != ESP_REGNO || x->d86_vsib != 0) {
2808 (void) strlcat(opnd, "(", OPLEN);
2809 need_paren = 1;
2810 }
2811 } else {
2812 (void) strlcat(opnd, "(", OPLEN);
2813 (void) strlcat(opnd, regs[base], OPLEN);
2814 need_paren = 1;
2815 }
2816
2817 /*
2818 * print the index (if any)
2819 */
2820 if (index != ESP_REGNO || x->d86_vsib) {
2821 (void) strlcat(opnd, ",", OPLEN);
2822 (void) strlcat(opnd, bregs[index], OPLEN);
2823 (void) strlcat(opnd, sf[ss], OPLEN);
2824 } else
2825 if (need_paren)
2826 (void) strlcat(opnd, ")", OPLEN);
2827 }
2828 #endif
2829 }
2830
2831 /*
2832 * Operand sequence for standard instruction involving one register
2833 * and one register/memory operand.
2834 * wbit indicates a byte(0) or opnd_size(1) operation
2835 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
2836 */
2837 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \
2838 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2839 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2840 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2841 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \
2842 }
2843
2844 /*
2845 * Similar to above, but allows for the two operands to be of different
2846 * classes (ie. wbit).
2847 * wbit is for the r_m operand
2848 * w2 is for the reg operand
2849 */
2850 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \
2851 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2852 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2853 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2854 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \
2855 }
2856
2857 /*
2858 * Similar, but for 2 operands plus an immediate.
2859 * vbit indicates direction
2860 * 0 for "opcode imm, r, r_m" or
2861 * 1 for "opcode imm, r_m, r"
2862 */
2863 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
2864 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2865 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2866 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \
2867 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \
2868 dtrace_imm_opnd(x, wbit, immsize, 0); \
2869 }
2870
2871 /*
2872 * Similar, but for 2 operands plus two immediates.
2873 */
2874 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
2875 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2876 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2877 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2878 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \
2879 dtrace_imm_opnd(x, wbit, immsize, 1); \
2880 dtrace_imm_opnd(x, wbit, immsize, 0); \
2881 }
2882
2883 /*
2884 * 1 operands plus two immediates.
2885 */
2886 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
2887 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2888 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2889 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2890 dtrace_imm_opnd(x, wbit, immsize, 1); \
2891 dtrace_imm_opnd(x, wbit, immsize, 0); \
2892 }
2893
2894 /*
2895 * Dissassemble a single x86 or amd64 instruction.
2896 *
2897 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
2898 * for interpreting instructions.
2899 *
2900 * returns non-zero for bad opcode
2901 */
2902 int
2903 dtrace_disx86(dis86_t *x, uint_t cpu_mode)
2904 {
2905 instable_t *dp; /* decode table being used */
2906 #ifdef DIS_TEXT
2907 uint_t i;
2908 #endif
2909 #ifdef DIS_MEM
2910 uint_t nomem = 0;
2911 #define NOMEM (nomem = 1)
2912 #else
2913 #define NOMEM /* nothing */
2914 #endif
2915 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */
2916 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */
2917 uint_t wbit = 0; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */
2918 uint_t w2; /* wbit value for second operand */
2919 uint_t vbit;
2920 uint_t mode = 0; /* mode value from ModRM byte */
2921 uint_t reg = 0; /* reg value from ModRM byte */
2922 uint_t r_m = 0; /* r_m value from ModRM byte */
2923
2924 uint_t opcode1 = 0; /* high nibble of 1st byte */
2925 uint_t opcode2 = 0; /* low nibble of 1st byte */
2926 uint_t opcode3 = 0; /* extra opcode bits usually from ModRM byte */
2927 uint_t opcode4 = 0; /* high nibble of 2nd byte */
2928 uint_t opcode5 = 0; /* low nibble of 2nd byte */
2929 uint_t opcode6 = 0; /* high nibble of 3rd byte */
2930 uint_t opcode7 = 0; /* low nibble of 3rd byte */
2931 uint_t opcode_bytes = 1;
2932
2933 /*
2934 * legacy prefixes come in 5 flavors, you should have only one of each
2935 */
2936 uint_t opnd_size_prefix = 0;
2937 uint_t addr_size_prefix = 0;
2938 uint_t segment_prefix = 0;
2939 uint_t lock_prefix = 0;
2940 uint_t rep_prefix = 0;
2941 uint_t rex_prefix = 0; /* amd64 register extension prefix */
2942
2943 /*
2944 * Intel VEX instruction encoding prefix and fields
2945 */
2946
2947 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
2948 uint_t vex_prefix = 0;
2949
2950 /*
2951 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
2952 * (for 3 bytes prefix)
2953 */
2954 uint_t vex_byte1 = 0;
2955
2956 /*
2957 * For 32-bit mode, it should prefetch the next byte to
2958 * distinguish between AVX and les/lds
2959 */
2960 uint_t vex_prefetch = 0;
2961
2962 uint_t vex_m = 0;
2963 uint_t vex_v = 0;
2964 uint_t vex_p = 0;
2965 uint_t vex_R = 1;
2966 uint_t vex_X = 1;
2967 uint_t vex_B = 1;
2968 uint_t vex_W = 0;
2969 uint_t vex_L = 0;
2970 dis_gather_regs_t *vreg;
2971
2972 #ifdef DIS_TEXT
2973 /* Instruction name for BLS* family of instructions */
2974 char *blsinstr;
2975 #endif
2976
2977 size_t off;
2978
2979 instable_t dp_mmx;
2980
2981 x->d86_len = 0;
2982 x->d86_rmindex = -1;
2983 x->d86_error = 0;
2984 #ifdef DIS_TEXT
2985 x->d86_numopnds = 0;
2986 x->d86_seg_prefix = NULL;
2987 x->d86_mnem[0] = 0;
2988 for (i = 0; i < 4; ++i) {
2989 x->d86_opnd[i].d86_opnd[0] = 0;
2990 x->d86_opnd[i].d86_prefix[0] = 0;
2991 x->d86_opnd[i].d86_value_size = 0;
2992 x->d86_opnd[i].d86_value = 0;
2993 x->d86_opnd[i].d86_mode = MODE_NONE;
2994 }
2995 #endif
2996 x->d86_rex_prefix = 0;
2997 x->d86_got_modrm = 0;
2998 x->d86_memsize = 0;
2999 x->d86_vsib = 0;
3000
3001 if (cpu_mode == SIZE16) {
3002 opnd_size = SIZE16;
3003 addr_size = SIZE16;
3004 } else if (cpu_mode == SIZE32) {
3005 opnd_size = SIZE32;
3006 addr_size = SIZE32;
3007 } else {
3008 opnd_size = SIZE32;
3009 addr_size = SIZE64;
3010 }
3011
3012 /*
3013 * Get one opcode byte and check for zero padding that follows
3014 * jump tables.
3015 */
3016 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3017 goto error;
3018
3019 if (opcode1 == 0 && opcode2 == 0 &&
3020 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
3021 #ifdef DIS_TEXT
3022 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
3023 #endif
3024 goto done;
3025 }
3026
3027 /*
3028 * Gather up legacy x86 prefix bytes.
3029 */
3030 for (;;) {
3031 uint_t *which_prefix = NULL;
3032
3033 dp = (instable_t *)&dis_distable[opcode1][opcode2];
3034
3035 switch (dp->it_adrmode) {
3036 case PREFIX:
3037 which_prefix = &rep_prefix;
3038 break;
3039 case LOCK:
3040 which_prefix = &lock_prefix;
3041 break;
3042 case OVERRIDE:
3043 which_prefix = &segment_prefix;
3044 #ifdef DIS_TEXT
3045 x->d86_seg_prefix = (char *)dp->it_name;
3046 #endif
3047 if (dp->it_invalid64 && cpu_mode == SIZE64)
3048 goto error;
3049 break;
3050 case AM:
3051 which_prefix = &addr_size_prefix;
3052 break;
3053 case DM:
3054 which_prefix = &opnd_size_prefix;
3055 break;
3056 }
3057 if (which_prefix == NULL)
3058 break;
3059 *which_prefix = (opcode1 << 4) | opcode2;
3060 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3061 goto error;
3062 }
3063
3064 /*
3065 * Handle amd64 mode PREFIX values.
3066 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
3067 * We might have a REX prefix (opcodes 0x40-0x4f)
3068 */
3069 if (cpu_mode == SIZE64) {
3070 if (segment_prefix != 0x64 && segment_prefix != 0x65)
3071 segment_prefix = 0;
3072
3073 if (opcode1 == 0x4) {
3074 rex_prefix = (opcode1 << 4) | opcode2;
3075 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3076 goto error;
3077 dp = (instable_t *)&dis_distable[opcode1][opcode2];
3078 } else if (opcode1 == 0xC &&
3079 (opcode2 == 0x4 || opcode2 == 0x5)) {
3080 /* AVX instructions */
3081 vex_prefix = (opcode1 << 4) | opcode2;
3082 x->d86_rex_prefix = 0x40;
3083 }
3084 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
3085 /* LDS, LES or AVX */
3086 dtrace_get_modrm(x, &mode, &reg, &r_m);
3087 vex_prefetch = 1;
3088
3089 if (mode == REG_ONLY) {
3090 /* AVX */
3091 vex_prefix = (opcode1 << 4) | opcode2;
3092 x->d86_rex_prefix = 0x40;
3093 opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
3094 opcode4 = ((reg << 3) | r_m) & 0x0F;
3095 }
3096 }
3097
3098 if (vex_prefix == VEX_2bytes) {
3099 if (!vex_prefetch) {
3100 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3101 goto error;
3102 }
3103 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
3104 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
3105 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
3106 vex_p = opcode4 & VEX_p;
3107 /*
3108 * The vex.x and vex.b bits are not defined in two bytes
3109 * mode vex prefix, their default values are 1
3110 */
3111 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
3112
3113 if (vex_R == 0)
3114 x->d86_rex_prefix |= REX_R;
3115
3116 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3117 goto error;
3118
3119 switch (vex_p) {
3120 case VEX_p_66:
3121 dp = (instable_t *)
3122 &dis_opAVX660F[(opcode1 << 4) | opcode2];
3123 break;
3124 case VEX_p_F3:
3125 dp = (instable_t *)
3126 &dis_opAVXF30F[(opcode1 << 4) | opcode2];
3127 break;
3128 case VEX_p_F2:
3129 dp = (instable_t *)
3130 &dis_opAVXF20F [(opcode1 << 4) | opcode2];
3131 break;
3132 default:
3133 dp = (instable_t *)
3134 &dis_opAVX0F[opcode1][opcode2];
3135
3136 }
3137
3138 } else if (vex_prefix == VEX_3bytes) {
3139 if (!vex_prefetch) {
3140 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3141 goto error;
3142 }
3143 vex_R = (opcode3 & VEX_R) >> 3;
3144 vex_X = (opcode3 & VEX_X) >> 2;
3145 vex_B = (opcode3 & VEX_B) >> 1;
3146 vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
3147 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
3148
3149 if (vex_R == 0)
3150 x->d86_rex_prefix |= REX_R;
3151 if (vex_X == 0)
3152 x->d86_rex_prefix |= REX_X;
3153 if (vex_B == 0)
3154 x->d86_rex_prefix |= REX_B;
3155
3156 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
3157 goto error;
3158 vex_W = (opcode5 & VEX_W) >> 3;
3159 vex_L = (opcode6 & VEX_L) >> 2;
3160 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
3161 vex_p = opcode6 & VEX_p;
3162
3163 if (vex_W)
3164 x->d86_rex_prefix |= REX_W;
3165
3166 /* Only these three vex_m values valid; others are reserved */
3167 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
3168 (vex_m != VEX_m_0F3A))
3169 goto error;
3170
3171 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3172 goto error;
3173
3174 switch (vex_p) {
3175 case VEX_p_66:
3176 if (vex_m == VEX_m_0F) {
3177 dp = (instable_t *)
3178 &dis_opAVX660F
3179 [(opcode1 << 4) | opcode2];
3180 } else if (vex_m == VEX_m_0F38) {
3181 dp = (instable_t *)
3182 &dis_opAVX660F38
3183 [(opcode1 << 4) | opcode2];
3184 } else if (vex_m == VEX_m_0F3A) {
3185 dp = (instable_t *)
3186 &dis_opAVX660F3A
3187 [(opcode1 << 4) | opcode2];
3188 } else {
3189 goto error;
3190 }
3191 break;
3192 case VEX_p_F3:
3193 if (vex_m == VEX_m_0F) {
3194 dp = (instable_t *)
3195 &dis_opAVXF30F
3196 [(opcode1 << 4) | opcode2];
3197 } else if (vex_m == VEX_m_0F38) {
3198 dp = (instable_t *)
3199 &dis_opAVXF30F38
3200 [(opcode1 << 4) | opcode2];
3201 } else {
3202 goto error;
3203 }
3204 break;
3205 case VEX_p_F2:
3206 if (vex_m == VEX_m_0F) {
3207 dp = (instable_t *)
3208 &dis_opAVXF20F
3209 [(opcode1 << 4) | opcode2];
3210 } else if (vex_m == VEX_m_0F3A) {
3211 dp = (instable_t *)
3212 &dis_opAVXF20F3A
3213 [(opcode1 << 4) | opcode2];
3214 } else if (vex_m == VEX_m_0F38) {
3215 dp = (instable_t *)
3216 &dis_opAVXF20F38
3217 [(opcode1 << 4) | opcode2];
3218 } else {
3219 goto error;
3220 }
3221 break;
3222 default:
3223 dp = (instable_t *)
3224 &dis_opAVX0F[opcode1][opcode2];
3225
3226 }
3227 }
3228 if (vex_prefix) {
3229 if (dp->it_vexwoxmm) {
3230 wbit = LONG_OPND;
3231 } else {
3232 if (vex_L)
3233 wbit = YMM_OPND;
3234 else
3235 wbit = XMM_OPND;
3236 }
3237 }
3238
3239 /*
3240 * Deal with selection of operand and address size now.
3241 * Note that the REX.W bit being set causes opnd_size_prefix to be
3242 * ignored.
3243 */
3244 if (cpu_mode == SIZE64) {
3245 if ((rex_prefix & REX_W) || vex_W)
3246 opnd_size = SIZE64;
3247 else if (opnd_size_prefix)
3248 opnd_size = SIZE16;
3249
3250 if (addr_size_prefix)
3251 addr_size = SIZE32;
3252 } else if (cpu_mode == SIZE32) {
3253 if (opnd_size_prefix)
3254 opnd_size = SIZE16;
3255 if (addr_size_prefix)
3256 addr_size = SIZE16;
3257 } else {
3258 if (opnd_size_prefix)
3259 opnd_size = SIZE32;
3260 if (addr_size_prefix)
3261 addr_size = SIZE32;
3262 }
3263 /*
3264 * The pause instruction - a repz'd nop. This doesn't fit
3265 * with any of the other prefix goop added for SSE, so we'll
3266 * special-case it here.
3267 */
3268 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) {
3269 rep_prefix = 0;
3270 dp = (instable_t *)&dis_opPause;
3271 }
3272
3273 /*
3274 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
3275 * byte so we may need to perform a table indirection.
3276 */
3277 if (dp->it_indirect == (instable_t *)dis_op0F) {
3278 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
3279 goto error;
3280 opcode_bytes = 2;
3281 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) {
3282 uint_t subcode;
3283
3284 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3285 goto error;
3286 opcode_bytes = 3;
3287 subcode = ((opcode6 & 0x3) << 1) |
3288 ((opcode7 & 0x8) >> 3);
3289 dp = (instable_t *)&dis_op0F7123[opcode5][subcode];
3290 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) {
3291 dp = (instable_t *)&dis_op0FC8[0];
3292 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) {
3293 opcode_bytes = 3;
3294 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3295 goto error;
3296 if (opnd_size == SIZE16)
3297 opnd_size = SIZE32;
3298
3299 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7];
3300 #ifdef DIS_TEXT
3301 if (LIT_STRNEQL(dp->it_name, "INVALID"))
3302 goto error;
3303 #endif
3304 switch (dp->it_adrmode) {
3305 case XMMP:
3306 break;
3307 case XMMP_66r:
3308 case XMMPRM_66r:
3309 case XMM3PM_66r:
3310 if (opnd_size_prefix == 0) {
3311 goto error;
3312 }
3313 break;
3314 case XMMP_66o:
3315 if (opnd_size_prefix == 0) {
3316 /* SSSE3 MMX instructions */
3317 dp_mmx = *dp;
3318 dp = &dp_mmx;
3319 dp->it_adrmode = MMOPM_66o;
3320 #ifdef DIS_MEM
3321 dp->it_size = 8;
3322 #endif
3323 }
3324 break;
3325 default:
3326 goto error;
3327 }
3328 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) {
3329 opcode_bytes = 3;
3330 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3331 goto error;
3332 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
3333
3334 /*
3335 * Both crc32 and movbe have the same 3rd opcode
3336 * byte of either 0xF0 or 0xF1, so we use another
3337 * indirection to distinguish between the two.
3338 */
3339 if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
3340 dp->it_indirect == (instable_t *)dis_op0F38F1) {
3341
3342 dp = dp->it_indirect;
3343 if (rep_prefix != 0xF2) {
3344 /* It is movbe */
3345 dp++;
3346 }
3347 }
3348
3349 /*
3350 * The adx family of instructions (adcx and adox)
3351 * continue the classic Intel tradition of abusing
3352 * arbitrary prefixes without actually meaning the
3353 * prefix bit. Therefore, if we find either the
3354 * opnd_size_prefix or rep_prefix we end up zeroing it
3355 * out after making our determination so as to ensure
3356 * that we don't get confused and accidentally print
3357 * repz prefixes and the like on these instructions.
3358 *
3359 * In addition, these instructions are actually much
3360 * closer to AVX instructions in semantics. Importantly,
3361 * they always default to having 32-bit operands.
3362 * However, if the CPU is in 64-bit mode, then and only
3363 * then, does it use REX.w promotes things to 64-bits
3364 * and REX.r allows 64-bit mode to use register r8-r15.
3365 */
3366 if (dp->it_indirect == (instable_t *)dis_op0F38F6) {
3367 dp = dp->it_indirect;
3368 if (opnd_size_prefix == 0 &&
3369 rep_prefix == 0xf3) {
3370 /* It is adox */
3371 dp++;
3372 } else if (opnd_size_prefix != 0x66 &&
3373 rep_prefix != 0) {
3374 /* It isn't adcx */
3375 goto error;
3376 }
3377 opnd_size_prefix = 0;
3378 rep_prefix = 0;
3379 opnd_size = SIZE32;
3380 if (rex_prefix & REX_W)
3381 opnd_size = SIZE64;
3382 }
3383
3384 #ifdef DIS_TEXT
3385 if (LIT_STRNEQL(dp->it_name, "INVALID"))
3386 goto error;
3387 #endif
3388 switch (dp->it_adrmode) {
3389 case ADX:
3390 case XMM:
3391 break;
3392 case RM_66r:
3393 case XMM_66r:
3394 case XMMM_66r:
3395 if (opnd_size_prefix == 0) {
3396 goto error;
3397 }
3398 break;
3399 case XMM_66o:
3400 if (opnd_size_prefix == 0) {
3401 /* SSSE3 MMX instructions */
3402 dp_mmx = *dp;
3403 dp = &dp_mmx;
3404 dp->it_adrmode = MM;
3405 #ifdef DIS_MEM
3406 dp->it_size = 8;
3407 #endif
3408 }
3409 break;
3410 case CRC32:
3411 if (rep_prefix != 0xF2) {
3412 goto error;
3413 }
3414 rep_prefix = 0;
3415 break;
3416 case MOVBE:
3417 if (rep_prefix != 0x0) {
3418 goto error;
3419 }
3420 break;
3421 default:
3422 goto error;
3423 }
3424 } else {
3425 dp = (instable_t *)&dis_op0F[opcode4][opcode5];
3426 }
3427 }
3428
3429 /*
3430 * If still not at a TERM decode entry, then a ModRM byte
3431 * exists and its fields further decode the instruction.
3432 */
3433 x->d86_got_modrm = 0;
3434 if (dp->it_indirect != TERM) {
3435 dtrace_get_modrm(x, &mode, &opcode3, &r_m);
3436 if (x->d86_error)
3437 goto error;
3438 reg = opcode3;
3439
3440 /*
3441 * decode 287 instructions (D8-DF) from opcodeN
3442 */
3443 if (opcode1 == 0xD && opcode2 >= 0x8) {
3444 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4)
3445 dp = (instable_t *)&dis_opFP5[r_m];
3446 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4)
3447 dp = (instable_t *)&dis_opFP7[opcode3];
3448 else if (opcode2 == 0xB && mode == 0x3)
3449 dp = (instable_t *)&dis_opFP6[opcode3];
3450 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4)
3451 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m];
3452 else if (mode == 0x3)
3453 dp = (instable_t *)
3454 &dis_opFP3[opcode2 - 8][opcode3];
3455 else
3456 dp = (instable_t *)
3457 &dis_opFP1n2[opcode2 - 8][opcode3];
3458 } else {
3459 dp = (instable_t *)dp->it_indirect + opcode3;
3460 }
3461 }
3462
3463 /*
3464 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
3465 * (sign extend 32bit to 64 bit)
3466 */
3467 if ((vex_prefix == 0) && cpu_mode == SIZE64 &&
3468 opcode1 == 0x6 && opcode2 == 0x3)
3469 {
3470 dp = (instable_t *)&dis_opMOVSLD;
3471 }
3472
3473 /*
3474 * at this point we should have a correct (or invalid) opcode
3475 */
3476 if ((cpu_mode == SIZE64 && dp->it_invalid64) ||
3477 (cpu_mode != SIZE64 && dp->it_invalid32))
3478 goto error;
3479 if (dp->it_indirect != TERM)
3480 goto error;
3481
3482 /*
3483 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do
3484 * need to include UNKNOWN below, as we may have instructions that
3485 * actually have a prefix, but don't exist in any other form.
3486 */
3487 switch (dp->it_adrmode) {
3488 case UNKNOWN:
3489 case MMO:
3490 case MMOIMPL:
3491 case MMO3P:
3492 case MMOM3:
3493 case MMOMS:
3494 case MMOPM:
3495 case MMOPRM:
3496 case MMOS:
3497 case XMMO:
3498 case XMMOM:
3499 case XMMOMS:
3500 case XMMOPM:
3501 case XMMOS:
3502 case XMMOMX:
3503 case XMMOX3:
3504 case XMMOXMM:
3505 /*
3506 * This is horrible. Some SIMD instructions take the
3507 * form 0x0F 0x?? ..., which is easily decoded using the
3508 * existing tables. Other SIMD instructions use various
3509 * prefix bytes to overload existing instructions. For
3510 * Example, addps is F0, 58, whereas addss is F3 (repz),
3511 * F0, 58. Presumably someone got a raise for this.
3512 *
3513 * If we see one of the instructions which can be
3514 * modified in this way (if we've got one of the SIMDO*
3515 * address modes), we'll check to see if the last prefix
3516 * was a repz. If it was, we strip the prefix from the
3517 * mnemonic, and we indirect using the dis_opSIMDrepz
3518 * table.
3519 */
3520
3521 /*
3522 * Calculate our offset in dis_op0F
3523 */
3524 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F))
3525 goto error;
3526
3527 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3528 sizeof (instable_t);
3529
3530 /*
3531 * Rewrite if this instruction used one of the magic prefixes.
3532 */
3533 if (rep_prefix) {
3534 if (rep_prefix == 0xf2)
3535 dp = (instable_t *)&dis_opSIMDrepnz[off];
3536 else
3537 dp = (instable_t *)&dis_opSIMDrepz[off];
3538 rep_prefix = 0;
3539 } else if (opnd_size_prefix) {
3540 dp = (instable_t *)&dis_opSIMDdata16[off];
3541 opnd_size_prefix = 0;
3542 if (opnd_size == SIZE16)
3543 opnd_size = SIZE32;
3544 }
3545 break;
3546
3547 case MG9:
3548 /*
3549 * More horribleness: the group 9 (0xF0 0xC7) instructions are
3550 * allowed an optional prefix of 0x66 or 0xF3. This is similar
3551 * to the SIMD business described above, but with a different
3552 * addressing mode (and an indirect table), so we deal with it
3553 * separately (if similarly).
3554 *
3555 * Intel further complicated this with the release of Ivy Bridge
3556 * where they overloaded these instructions based on the ModR/M
3557 * bytes. The VMX instructions have a mode of 0 since they are
3558 * memory instructions but rdrand instructions have a mode of
3559 * 0b11 (REG_ONLY) because they only operate on registers. While
3560 * there are different prefix formats, for now it is sufficient
3561 * to use a single different table.
3562 */
3563
3564 /*
3565 * Calculate our offset in dis_op0FC7 (the group 9 table)
3566 */
3567 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
3568 goto error;
3569
3570 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
3571 sizeof (instable_t);
3572
3573 /*
3574 * If we have a mode of 0b11 then we have to rewrite this.
3575 */
3576 dtrace_get_modrm(x, &mode, &reg, &r_m);
3577 if (mode == REG_ONLY) {
3578 dp = (instable_t *)&dis_op0FC7m3[off];
3579 break;
3580 }
3581
3582 /*
3583 * Rewrite if this instruction used one of the magic prefixes.
3584 */
3585 if (rep_prefix) {
3586 if (rep_prefix == 0xf3)
3587 dp = (instable_t *)&dis_opF30FC7[off];
3588 else
3589 goto error;
3590 rep_prefix = 0;
3591 } else if (opnd_size_prefix) {
3592 dp = (instable_t *)&dis_op660FC7[off];
3593 opnd_size_prefix = 0;
3594 if (opnd_size == SIZE16)
3595 opnd_size = SIZE32;
3596 }
3597 break;
3598
3599
3600 case MMOSH:
3601 /*
3602 * As with the "normal" SIMD instructions, the MMX
3603 * shuffle instructions are overloaded. These
3604 * instructions, however, are special in that they use
3605 * an extra byte, and thus an extra table. As of this
3606 * writing, they only use the opnd_size prefix.
3607 */
3608
3609 /*
3610 * Calculate our offset in dis_op0F7123
3611 */
3612 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 >
3613 sizeof (dis_op0F7123))
3614 goto error;
3615
3616 if (opnd_size_prefix) {
3617 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) /
3618 sizeof (instable_t);
3619 dp = (instable_t *)&dis_opSIMD7123[off];
3620 opnd_size_prefix = 0;
3621 if (opnd_size == SIZE16)
3622 opnd_size = SIZE32;
3623 }
3624 break;
3625 case MRw:
3626 if (rep_prefix) {
3627 if (rep_prefix == 0xf3) {
3628
3629 /*
3630 * Calculate our offset in dis_op0F
3631 */
3632 if ((uintptr_t)dp - (uintptr_t)dis_op0F
3633 > sizeof (dis_op0F))
3634 goto error;
3635
3636 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3637 sizeof (instable_t);
3638
3639 dp = (instable_t *)&dis_opSIMDrepz[off];
3640 rep_prefix = 0;
3641 } else {
3642 goto error;
3643 }
3644 }
3645 break;
3646 }
3647
3648 /*
3649 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
3650 */
3651 if (cpu_mode == SIZE64)
3652 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop))
3653 opnd_size = SIZE64;
3654
3655 #ifdef DIS_TEXT
3656 /*
3657 * At this point most instructions can format the opcode mnemonic
3658 * including the prefixes.
3659 */
3660 if (lock_prefix)
3661 (void) strlcat(x->d86_mnem, "lock ", OPLEN);
3662
3663 if (rep_prefix == 0xf2)
3664 (void) strlcat(x->d86_mnem, "repnz ", OPLEN);
3665 else if (rep_prefix == 0xf3)
3666 (void) strlcat(x->d86_mnem, "repz ", OPLEN);
3667
3668 if (cpu_mode == SIZE64 && addr_size_prefix)
3669 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN);
3670
3671 if (dp->it_adrmode != CBW &&
3672 dp->it_adrmode != CWD &&
3673 dp->it_adrmode != XMMSFNC) {
3674 if (LIT_STRNEQL(dp->it_name, "INVALID"))
3675 goto error;
3676 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN);
3677 if (dp->it_avxsuf && dp->it_suffix) {
3678 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d",
3679 OPLEN);
3680 } else if (dp->it_suffix) {
3681 char *types[] = {"", "w", "l", "q"};
3682 if (opcode_bytes == 2 && opcode4 == 4) {
3683 /* It's a cmovx.yy. Replace the suffix x */
3684 for (i = 5; i < OPLEN; i++) {
3685 if (x->d86_mnem[i] == '.')
3686 break;
3687 }
3688 x->d86_mnem[i - 1] = *types[opnd_size];
3689 } else if ((opnd_size == 2) && (opcode_bytes == 3) &&
3690 ((opcode6 == 1 && opcode7 == 6) ||
3691 (opcode6 == 2 && opcode7 == 2))) {
3692 /*
3693 * To handle PINSRD and PEXTRD
3694 */
3695 (void) strlcat(x->d86_mnem, "d", OPLEN);
3696 } else {
3697 (void) strlcat(x->d86_mnem, types[opnd_size],
3698 OPLEN);
3699 }
3700 }
3701 }
3702 #endif
3703
3704 /*
3705 * Process operands based on the addressing modes.
3706 */
3707 x->d86_mode = cpu_mode;
3708 /*
3709 * In vex mode the rex_prefix has no meaning
3710 */
3711 if (!vex_prefix)
3712 x->d86_rex_prefix = rex_prefix;
3713 x->d86_opnd_size = opnd_size;
3714 x->d86_addr_size = addr_size;
3715 vbit = 0; /* initialize for mem/reg -> reg */
3716 switch (dp->it_adrmode) {
3717 /*
3718 * amd64 instruction to sign extend 32 bit reg/mem operands
3719 * into 64 bit register values
3720 */
3721 case MOVSXZ:
3722 #ifdef DIS_TEXT
3723 if (rex_prefix == 0) {
3724 (void) strncpy(x->d86_mnem, "movzld", OPLEN);
3725 x->d86_mnem[OPLEN - 1] = '\0';
3726 }
3727 #endif
3728 dtrace_get_modrm(x, &mode, &reg, &r_m);
3729 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3730 x->d86_opnd_size = SIZE64;
3731 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3732 x->d86_opnd_size = opnd_size = SIZE32;
3733 wbit = LONG_OPND;
3734 dtrace_get_operand(x, mode, r_m, wbit, 0);
3735 break;
3736
3737 /*
3738 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
3739 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
3740 * wbit lives in 2nd byte, note that operands
3741 * are different sized
3742 */
3743 case MOVZ:
3744 if (rex_prefix & REX_W) {
3745 /* target register size = 64 bit */
3746 x->d86_mnem[5] = 'q';
3747 }
3748 dtrace_get_modrm(x, &mode, &reg, &r_m);
3749 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3750 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3751 x->d86_opnd_size = opnd_size = SIZE16;
3752 wbit = WBIT(opcode5);
3753 dtrace_get_operand(x, mode, r_m, wbit, 0);
3754 break;
3755 case CRC32:
3756 opnd_size = SIZE32;
3757 if (rex_prefix & REX_W)
3758 opnd_size = SIZE64;
3759 x->d86_opnd_size = opnd_size;
3760
3761 dtrace_get_modrm(x, &mode, &reg, &r_m);
3762 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3763 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3764 wbit = WBIT(opcode7);
3765 if (opnd_size_prefix)
3766 x->d86_opnd_size = opnd_size = SIZE16;
3767 dtrace_get_operand(x, mode, r_m, wbit, 0);
3768 break;
3769 case MOVBE:
3770 opnd_size = SIZE32;
3771 if (rex_prefix & REX_W)
3772 opnd_size = SIZE64;
3773 x->d86_opnd_size = opnd_size;
3774
3775 dtrace_get_modrm(x, &mode, &reg, &r_m);
3776 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3777 wbit = WBIT(opcode7);
3778 if (opnd_size_prefix)
3779 x->d86_opnd_size = opnd_size = SIZE16;
3780 if (wbit) {
3781 /* reg -> mem */
3782 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
3783 dtrace_get_operand(x, mode, r_m, wbit, 1);
3784 } else {
3785 /* mem -> reg */
3786 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3787 dtrace_get_operand(x, mode, r_m, wbit, 0);
3788 }
3789 break;
3790
3791 /*
3792 * imul instruction, with either 8-bit or longer immediate
3793 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
3794 */
3795 case IMUL:
3796 wbit = LONG_OPND;
3797 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,
3798 OPSIZE(opnd_size, opcode2 == 0x9), 1);
3799 break;
3800
3801 /* memory or register operand to register, with 'w' bit */
3802 case MRw:
3803 case ADX:
3804 wbit = WBIT(opcode2);
3805 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3806 break;
3807
3808 /* register to memory or register operand, with 'w' bit */
3809 /* arpl happens to fit here also because it is odd */
3810 case RMw:
3811 if (opcode_bytes == 2)
3812 wbit = WBIT(opcode5);
3813 else
3814 wbit = WBIT(opcode2);
3815 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3816 break;
3817
3818 /* xaddb instruction */
3819 case XADDB:
3820 wbit = 0;
3821 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3822 break;
3823
3824 /* MMX register to memory or register operand */
3825 case MMS:
3826 case MMOS:
3827 #ifdef DIS_TEXT
3828 wbit = !LIT_STRNEQL(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
3829 #else
3830 wbit = LONG_OPND;
3831 #endif
3832 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3833 break;
3834
3835 /* MMX register to memory */
3836 case MMOMS:
3837 dtrace_get_modrm(x, &mode, &reg, &r_m);
3838 if (mode == REG_ONLY)
3839 goto error;
3840 wbit = MM_OPND;
3841 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3842 break;
3843
3844 /* Double shift. Has immediate operand specifying the shift. */
3845 case DSHIFT:
3846 wbit = LONG_OPND;
3847 dtrace_get_modrm(x, &mode, &reg, &r_m);
3848 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3849 dtrace_get_operand(x, mode, r_m, wbit, 2);
3850 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3851 dtrace_imm_opnd(x, wbit, 1, 0);
3852 break;
3853
3854 /*
3855 * Double shift. With no immediate operand, specifies using %cl.
3856 */
3857 case DSHIFTcl:
3858 wbit = LONG_OPND;
3859 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3860 break;
3861
3862 /* immediate to memory or register operand */
3863 case IMlw:
3864 wbit = WBIT(opcode2);
3865 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3866 dtrace_get_operand(x, mode, r_m, wbit, 1);
3867 /*
3868 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
3869 */
3870 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0);
3871 break;
3872
3873 /* immediate to memory or register operand with the */
3874 /* 'w' bit present */
3875 case IMw:
3876 wbit = WBIT(opcode2);
3877 dtrace_get_modrm(x, &mode, &reg, &r_m);
3878 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3879 dtrace_get_operand(x, mode, r_m, wbit, 1);
3880 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
3881 break;
3882
3883 /* immediate to register with register in low 3 bits */
3884 /* of op code */
3885 case IR:
3886 /* w-bit here (with regs) is bit 3 */
3887 wbit = opcode2 >>3 & 0x1;
3888 reg = REGNO(opcode2);
3889 dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
3890 mode = REG_ONLY;
3891 r_m = reg;
3892 dtrace_get_operand(x, mode, r_m, wbit, 1);
3893 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0);
3894 break;
3895
3896 /* MMX immediate shift of register */
3897 case MMSH:
3898 case MMOSH:
3899 wbit = MM_OPND;
3900 goto mm_shift; /* in next case */
3901
3902 /* SIMD immediate shift of register */
3903 case XMMSH:
3904 wbit = XMM_OPND;
3905 mm_shift:
3906 reg = REGNO(opcode7);
3907 dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
3908 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
3909 dtrace_imm_opnd(x, wbit, 1, 0);
3910 NOMEM;
3911 break;
3912
3913 /* accumulator to memory operand */
3914 case AO:
3915 vbit = 1;
3916 /*FALLTHROUGH*/
3917
3918 /* memory operand to accumulator */
3919 case OA:
3920 wbit = WBIT(opcode2);
3921 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit);
3922 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit);
3923 #ifdef DIS_TEXT
3924 x->d86_opnd[vbit].d86_mode = MODE_OFFSET;
3925 #endif
3926 break;
3927
3928
3929 /* segment register to memory or register operand */
3930 case SM:
3931 vbit = 1;
3932 /*FALLTHROUGH*/
3933
3934 /* memory or register operand to segment register */
3935 case MS:
3936 dtrace_get_modrm(x, &mode, &reg, &r_m);
3937 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3938 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit);
3939 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);
3940 break;
3941
3942 /*
3943 * rotate or shift instructions, which may shift by 1 or
3944 * consult the cl register, depending on the 'v' bit
3945 */
3946 case Mv:
3947 vbit = VBIT(opcode2);
3948 wbit = WBIT(opcode2);
3949 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3950 dtrace_get_operand(x, mode, r_m, wbit, 1);
3951 #ifdef DIS_TEXT
3952 if (vbit) {
3953 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN);
3954 } else {
3955 x->d86_opnd[0].d86_mode = MODE_SIGNED;
3956 x->d86_opnd[0].d86_value_size = 1;
3957 x->d86_opnd[0].d86_value = 1;
3958 }
3959 #endif
3960 break;
3961 /*
3962 * immediate rotate or shift instructions
3963 */
3964 case MvI:
3965 wbit = WBIT(opcode2);
3966 normal_imm_mem:
3967 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3968 dtrace_get_operand(x, mode, r_m, wbit, 1);
3969 dtrace_imm_opnd(x, wbit, 1, 0);
3970 break;
3971
3972 /* bit test instructions */
3973 case MIb:
3974 wbit = LONG_OPND;
3975 goto normal_imm_mem;
3976
3977 /* single memory or register operand with 'w' bit present */
3978 case Mw:
3979 wbit = WBIT(opcode2);
3980 just_mem:
3981 dtrace_get_modrm(x, &mode, &reg, &r_m);
3982 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3983 dtrace_get_operand(x, mode, r_m, wbit, 0);
3984 break;
3985
3986 case SWAPGS_RDTSCP:
3987 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
3988 #ifdef DIS_TEXT
3989 (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
3990 x->d86_mnem[OPLEN - 1] = '\0';
3991 #endif
3992 NOMEM;
3993 break;
3994 } else if (mode == 3 && r_m == 1) {
3995 #ifdef DIS_TEXT
3996 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
3997 #endif
3998 NOMEM;
3999 break;
4000 }
4001
4002 /*FALLTHROUGH*/
4003
4004 /* prefetch instruction - memory operand, but no memory acess */
4005 case PREF:
4006 NOMEM;
4007 /*FALLTHROUGH*/
4008
4009 /* single memory or register operand */
4010 case M:
4011 case MG9:
4012 wbit = LONG_OPND;
4013 goto just_mem;
4014
4015 /* single memory or register byte operand */
4016 case Mb:
4017 wbit = BYTE_OPND;
4018 goto just_mem;
4019
4020 case VMx:
4021 if (mode == 3) {
4022 #ifdef DIS_TEXT
4023 char *vminstr;
4024
4025 switch (r_m) {
4026 case 1:
4027 vminstr = "vmcall";
4028 break;
4029 case 2:
4030 vminstr = "vmlaunch";
4031 break;
4032 case 3:
4033 vminstr = "vmresume";
4034 break;
4035 case 4:
4036 vminstr = "vmxoff";
4037 break;
4038 default:
4039 goto error;
4040 }
4041
4042 (void) strncpy(x->d86_mnem, vminstr, OPLEN);
4043 #else
4044 if (r_m < 1 || r_m > 4)
4045 goto error;
4046 #endif
4047
4048 NOMEM;
4049 break;
4050 }
4051 /*FALLTHROUGH*/
4052 case SVM:
4053 if (mode == 3) {
4054 #if DIS_TEXT
4055 char *vinstr;
4056
4057 switch (r_m) {
4058 case 0:
4059 vinstr = "vmrun";
4060 break;
4061 case 1:
4062 vinstr = "vmmcall";
4063 break;
4064 case 2:
4065 vinstr = "vmload";
4066 break;
4067 case 3:
4068 vinstr = "vmsave";
4069 break;
4070 case 4:
4071 vinstr = "stgi";
4072 break;
4073 case 5:
4074 vinstr = "clgi";
4075 break;
4076 case 6:
4077 vinstr = "skinit";
4078 break;
4079 case 7:
4080 vinstr = "invlpga";
4081 break;
4082 }
4083
4084 (void) strncpy(x->d86_mnem, vinstr, OPLEN);
4085 #endif
4086 NOMEM;
4087 break;
4088 }
4089 /*FALLTHROUGH*/
4090 case MONITOR_MWAIT:
4091 if (mode == 3) {
4092 if (r_m == 0) {
4093 #ifdef DIS_TEXT
4094 (void) strncpy(x->d86_mnem, "monitor", OPLEN);
4095 x->d86_mnem[OPLEN - 1] = '\0';
4096 #endif
4097 NOMEM;
4098 break;
4099 } else if (r_m == 1) {
4100 #ifdef DIS_TEXT
4101 (void) strncpy(x->d86_mnem, "mwait", OPLEN);
4102 x->d86_mnem[OPLEN - 1] = '\0';
4103 #endif
4104 NOMEM;
4105 break;
4106 } else if (r_m == 2) {
4107 #ifdef DIS_TEXT
4108 (void) strncpy(x->d86_mnem, "clac", OPLEN);
4109 #endif
4110 NOMEM;
4111 break;
4112 } else if (r_m == 3) {
4113 #ifdef DIS_TEXT
4114 (void) strncpy(x->d86_mnem, "stac", OPLEN);
4115 #endif
4116 NOMEM;
4117 break;
4118 } else {
4119 goto error;
4120 }
4121 }
4122 /*FALLTHROUGH*/
4123 case XGETBV_XSETBV:
4124 if (mode == 3) {
4125 if (r_m == 0) {
4126 #ifdef DIS_TEXT
4127 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN);
4128 #endif
4129 NOMEM;
4130 break;
4131 } else if (r_m == 1) {
4132 #ifdef DIS_TEXT
4133 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN);
4134 #endif
4135 NOMEM;
4136 break;
4137 } else {
4138 goto error;
4139 }
4140
4141 }
4142 /*FALLTHROUGH*/
4143 case MO:
4144 /* Similar to M, but only memory (no direct registers) */
4145 wbit = LONG_OPND;
4146 dtrace_get_modrm(x, &mode, &reg, &r_m);
4147 if (mode == 3)
4148 goto error;
4149 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4150 dtrace_get_operand(x, mode, r_m, wbit, 0);
4151 break;
4152
4153 /* move special register to register or reverse if vbit */
4154 case SREG:
4155 switch (opcode5) {
4156
4157 case 2:
4158 vbit = 1;
4159 /*FALLTHROUGH*/
4160 case 0:
4161 wbit = CONTROL_OPND;
4162 break;
4163
4164 case 3:
4165 vbit = 1;
4166 /*FALLTHROUGH*/
4167 case 1:
4168 wbit = DEBUG_OPND;
4169 break;
4170
4171 case 6:
4172 vbit = 1;
4173 /*FALLTHROUGH*/
4174 case 4:
4175 wbit = TEST_OPND;
4176 break;
4177
4178 }
4179 dtrace_get_modrm(x, &mode, &reg, &r_m);
4180 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4181 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);
4182 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit);
4183 NOMEM;
4184 break;
4185
4186 /*
4187 * single register operand with register in the low 3
4188 * bits of op code
4189 */
4190 case R:
4191 if (opcode_bytes == 2)
4192 reg = REGNO(opcode5);
4193 else
4194 reg = REGNO(opcode2);
4195 dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
4196 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4197 NOMEM;
4198 break;
4199
4200 /*
4201 * register to accumulator with register in the low 3
4202 * bits of op code, xchg instructions
4203 */
4204 case RA:
4205 NOMEM;
4206 reg = REGNO(opcode2);
4207 dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
4208 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4209 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1);
4210 break;
4211
4212 /*
4213 * single segment register operand, with register in
4214 * bits 3-4 of op code byte
4215 */
4216 case SEG:
4217 NOMEM;
4218 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;
4219 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
4220 break;
4221
4222 /*
4223 * single segment register operand, with register in
4224 * bits 3-5 of op code
4225 */
4226 case LSEG:
4227 NOMEM;
4228 /* long seg reg from opcode */
4229 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;
4230 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
4231 break;
4232
4233 /* memory or register operand to register */
4234 case MR:
4235 if (vex_prefetch)
4236 x->d86_got_modrm = 1;
4237 wbit = LONG_OPND;
4238 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4239 break;
4240
4241 case RM:
4242 case RM_66r:
4243 wbit = LONG_OPND;
4244 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
4245 break;
4246
4247 /* MMX/SIMD-Int memory or mm reg to mm reg */
4248 case MM:
4249 case MMO:
4250 #ifdef DIS_TEXT
4251 wbit = !LIT_STRNEQL(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4252 #else
4253 wbit = LONG_OPND;
4254 #endif
4255 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
4256 break;
4257
4258 case MMOIMPL:
4259 #ifdef DIS_TEXT
4260 wbit = !LIT_STRNEQL(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4261 #else
4262 wbit = LONG_OPND;
4263 #endif
4264 dtrace_get_modrm(x, &mode, &reg, &r_m);
4265 if (mode != REG_ONLY)
4266 goto error;
4267
4268 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4269 dtrace_get_operand(x, mode, r_m, wbit, 0);
4270 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);
4271 mode = 0; /* change for memory access size... */
4272 break;
4273
4274 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
4275 case MMO3P:
4276 wbit = MM_OPND;
4277 goto xmm3p;
4278 case XMM3P:
4279 wbit = XMM_OPND;
4280 xmm3p:
4281 dtrace_get_modrm(x, &mode, &reg, &r_m);
4282 if (mode != REG_ONLY)
4283 goto error;
4284
4285 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,
4286 1);
4287 NOMEM;
4288 break;
4289
4290 case XMM3PM_66r:
4291 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,
4292 1, 0);
4293 break;
4294
4295 /* MMX/SIMD-Int predicated r32/mem to mm reg */
4296 case MMOPRM:
4297 wbit = LONG_OPND;
4298 w2 = MM_OPND;
4299 goto xmmprm;
4300 case XMMPRM:
4301 case XMMPRM_66r:
4302 wbit = LONG_OPND;
4303 w2 = XMM_OPND;
4304 xmmprm:
4305 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);
4306 break;
4307
4308 /* MMX/SIMD-Int predicated mm/mem to mm reg */
4309 case MMOPM:
4310 case MMOPM_66o:
4311 wbit = w2 = MM_OPND;
4312 goto xmmprm;
4313
4314 /* MMX/SIMD-Int mm reg to r32 */
4315 case MMOM3:
4316 NOMEM;
4317 dtrace_get_modrm(x, &mode, &reg, &r_m);
4318 if (mode != REG_ONLY)
4319 goto error;
4320 wbit = MM_OPND;
4321 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
4322 break;
4323
4324 /* SIMD memory or xmm reg operand to xmm reg */
4325 case XMM:
4326 case XMM_66o:
4327 case XMM_66r:
4328 case XMMO:
4329 case XMMXIMPL:
4330 wbit = XMM_OPND;
4331 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4332
4333 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY)
4334 goto error;
4335
4336 #ifdef DIS_TEXT
4337 /*
4338 * movlps and movhlps share opcodes. They differ in the
4339 * addressing modes allowed for their operands.
4340 * movhps and movlhps behave similarly.
4341 */
4342 if (mode == REG_ONLY) {
4343 if (LIT_STRNEQL(dp->it_name, "movlps")) {
4344 (void) strncpy(x->d86_mnem, "movhlps", OPLEN);
4345 x->d86_mnem[OPLEN - 1] = '\0';
4346 } else if (strcmp(dp->it_name, "movhps") == 0) {
4347 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
4348 x->d86_mnem[OPLEN - 1] = '\0';
4349 }
4350 }
4351 #endif
4352 if (dp->it_adrmode == XMMXIMPL)
4353 mode = 0; /* change for memory access size... */
4354 break;
4355
4356 /* SIMD xmm reg to memory or xmm reg */
4357 case XMMS:
4358 case XMMOS:
4359 case XMMMS:
4360 case XMMOMS:
4361 dtrace_get_modrm(x, &mode, &reg, &r_m);
4362 #ifdef DIS_TEXT
4363 if ((LIT_STRNEQL(dp->it_name, "movlps") ||
4364 LIT_STRNEQL(dp->it_name, "movhps") ||
4365 LIT_STRNEQL(dp->it_name, "movntps")) &&
4366 mode == REG_ONLY)
4367 goto error;
4368 #endif
4369 wbit = XMM_OPND;
4370 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
4371 break;
4372
4373 /* SIMD memory to xmm reg */
4374 case XMMM:
4375 case XMMM_66r:
4376 case XMMOM:
4377 wbit = XMM_OPND;
4378 dtrace_get_modrm(x, &mode, &reg, &r_m);
4379 #ifdef DIS_TEXT
4380 if (mode == REG_ONLY) {
4381 if (LIT_STRNEQL(dp->it_name, "movhps")) {
4382 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
4383 x->d86_mnem[OPLEN - 1] = '\0';
4384 } else
4385 goto error;
4386 }
4387 #endif
4388 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4389 break;
4390
4391 /* SIMD memory or r32 to xmm reg */
4392 case XMM3MX:
4393 wbit = LONG_OPND;
4394 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4395 break;
4396
4397 case XMM3MXS:
4398 wbit = LONG_OPND;
4399 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
4400 break;
4401
4402 /* SIMD memory or mm reg to xmm reg */
4403 case XMMOMX:
4404 /* SIMD mm to xmm */
4405 case XMMMX:
4406 wbit = MM_OPND;
4407 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4408 break;
4409
4410 /* SIMD memory or xmm reg to mm reg */
4411 case XMMXMM:
4412 case XMMOXMM:
4413 case XMMXM:
4414 wbit = XMM_OPND;
4415 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
4416 break;
4417
4418
4419 /* SIMD memory or xmm reg to r32 */
4420 case XMMXM3:
4421 wbit = XMM_OPND;
4422 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
4423 break;
4424
4425 /* SIMD xmm to r32 */
4426 case XMMX3:
4427 case XMMOX3:
4428 dtrace_get_modrm(x, &mode, &reg, &r_m);
4429 if (mode != REG_ONLY)
4430 goto error;
4431 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4432 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4433 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4434 NOMEM;
4435 break;
4436
4437 /* SIMD predicated memory or xmm reg with/to xmm reg */
4438 case XMMP:
4439 case XMMP_66r:
4440 case XMMP_66o:
4441 case XMMOPM:
4442 wbit = XMM_OPND;
4443 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,
4444 1);
4445
4446 #ifdef DIS_TEXT
4447 /*
4448 * cmpps and cmpss vary their instruction name based
4449 * on the value of imm8. Other XMMP instructions,
4450 * such as shufps, require explicit specification of
4451 * the predicate.
4452 */
4453 if (dp->it_name[0] == 'c' &&
4454 dp->it_name[1] == 'm' &&
4455 dp->it_name[2] == 'p' &&
4456 strlen(dp->it_name) == 5) {
4457 uchar_t pred = x->d86_opnd[0].d86_value & 0xff;
4458
4459 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *)))
4460 goto error;
4461
4462 (void) strncpy(x->d86_mnem, "cmp", OPLEN);
4463 x->d86_mnem[OPLEN - 1] = '\0';
4464 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred],
4465 OPLEN);
4466 (void) strlcat(x->d86_mnem,
4467 dp->it_name + strlen(dp->it_name) - 2,
4468 OPLEN);
4469 x->d86_opnd[0] = x->d86_opnd[1];
4470 x->d86_opnd[1] = x->d86_opnd[2];
4471 x->d86_numopnds = 2;
4472 }
4473 #endif
4474 break;
4475
4476 case XMMX2I:
4477 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,
4478 1);
4479 NOMEM;
4480 break;
4481
4482 case XMM2I:
4483 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);
4484 NOMEM;
4485 break;
4486
4487 /* immediate operand to accumulator */
4488 case IA:
4489 wbit = WBIT(opcode2);
4490 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4491 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
4492 NOMEM;
4493 break;
4494
4495 /* memory or register operand to accumulator */
4496 case MA:
4497 wbit = WBIT(opcode2);
4498 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4499 dtrace_get_operand(x, mode, r_m, wbit, 0);
4500 break;
4501
4502 /* si register to di register used to reference memory */
4503 case SD:
4504 #ifdef DIS_TEXT
4505 dtrace_check_override(x, 0);
4506 x->d86_numopnds = 2;
4507 if (addr_size == SIZE64) {
4508 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4509 OPLEN);
4510 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4511 OPLEN);
4512 } else if (addr_size == SIZE32) {
4513 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4514 OPLEN);
4515 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4516 OPLEN);
4517 } else {
4518 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4519 OPLEN);
4520 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4521 OPLEN);
4522 }
4523 #endif
4524 wbit = LONG_OPND;
4525 break;
4526
4527 /* accumulator to di register */
4528 case AD:
4529 wbit = WBIT(opcode2);
4530 #ifdef DIS_TEXT
4531 dtrace_check_override(x, 1);
4532 x->d86_numopnds = 2;
4533 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0);
4534 if (addr_size == SIZE64)
4535 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4536 OPLEN);
4537 else if (addr_size == SIZE32)
4538 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4539 OPLEN);
4540 else
4541 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4542 OPLEN);
4543 #endif
4544 break;
4545
4546 /* si register to accumulator */
4547 case SA:
4548 wbit = WBIT(opcode2);
4549 #ifdef DIS_TEXT
4550 dtrace_check_override(x, 0);
4551 x->d86_numopnds = 2;
4552 if (addr_size == SIZE64)
4553 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4554 OPLEN);
4555 else if (addr_size == SIZE32)
4556 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4557 OPLEN);
4558 else
4559 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4560 OPLEN);
4561 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4562 #endif
4563 break;
4564
4565 /*
4566 * single operand, a 16/32 bit displacement
4567 */
4568 case D:
4569 wbit = LONG_OPND;
4570 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4571 NOMEM;
4572 break;
4573
4574 /* jmp/call indirect to memory or register operand */
4575 case INM:
4576 #ifdef DIS_TEXT
4577 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN);
4578 #endif
4579 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4580 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4581 wbit = LONG_OPND;
4582 break;
4583
4584 /*
4585 * for long jumps and long calls -- a new code segment
4586 * register and an offset in IP -- stored in object
4587 * code in reverse order. Note - not valid in amd64
4588 */
4589 case SO:
4590 dtrace_check_override(x, 1);
4591 wbit = LONG_OPND;
4592 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1);
4593 #ifdef DIS_TEXT
4594 x->d86_opnd[1].d86_mode = MODE_SIGNED;
4595 #endif
4596 /* will now get segment operand */
4597 dtrace_imm_opnd(x, wbit, 2, 0);
4598 break;
4599
4600 /*
4601 * jmp/call. single operand, 8 bit displacement.
4602 * added to current EIP in 'compofff'
4603 */
4604 case BD:
4605 dtrace_disp_opnd(x, BYTE_OPND, 1, 0);
4606 NOMEM;
4607 break;
4608
4609 /* single 32/16 bit immediate operand */
4610 case I:
4611 wbit = LONG_OPND;
4612 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4613 break;
4614
4615 /* single 8 bit immediate operand */
4616 case Ib:
4617 wbit = LONG_OPND;
4618 dtrace_imm_opnd(x, wbit, 1, 0);
4619 break;
4620
4621 case ENTER:
4622 wbit = LONG_OPND;
4623 dtrace_imm_opnd(x, wbit, 2, 0);
4624 dtrace_imm_opnd(x, wbit, 1, 1);
4625 switch (opnd_size) {
4626 case SIZE64:
4627 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8;
4628 break;
4629 case SIZE32:
4630 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4;
4631 break;
4632 case SIZE16:
4633 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2;
4634 break;
4635 }
4636
4637 break;
4638
4639 /* 16-bit immediate operand */
4640 case RET:
4641 wbit = LONG_OPND;
4642 dtrace_imm_opnd(x, wbit, 2, 0);
4643 break;
4644
4645 /* single 8 bit port operand */
4646 case P:
4647 dtrace_check_override(x, 0);
4648 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4649 NOMEM;
4650 break;
4651
4652 /* single operand, dx register (variable port instruction) */
4653 case V:
4654 x->d86_numopnds = 1;
4655 dtrace_check_override(x, 0);
4656 #ifdef DIS_TEXT
4657 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN);
4658 #endif
4659 NOMEM;
4660 break;
4661
4662 /*
4663 * The int instruction, which has two forms:
4664 * int 3 (breakpoint) or
4665 * int n, where n is indicated in the subsequent
4666 * byte (format Ib). The int 3 instruction (opcode 0xCC),
4667 * where, although the 3 looks like an operand,
4668 * it is implied by the opcode. It must be converted
4669 * to the correct base and output.
4670 */
4671 case INT3:
4672 #ifdef DIS_TEXT
4673 x->d86_numopnds = 1;
4674 x->d86_opnd[0].d86_mode = MODE_SIGNED;
4675 x->d86_opnd[0].d86_value_size = 1;
4676 x->d86_opnd[0].d86_value = 3;
4677 #endif
4678 NOMEM;
4679 break;
4680
4681 /* single 8 bit immediate operand */
4682 case INTx:
4683 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4684 NOMEM;
4685 break;
4686
4687 /* an unused byte must be discarded */
4688 case U:
4689 if (x->d86_get_byte(x->d86_data) < 0)
4690 goto error;
4691 x->d86_len++;
4692 NOMEM;
4693 break;
4694
4695 case CBW:
4696 #ifdef DIS_TEXT
4697 if (opnd_size == SIZE16)
4698 (void) strlcat(x->d86_mnem, "cbtw", OPLEN);
4699 else if (opnd_size == SIZE32)
4700 (void) strlcat(x->d86_mnem, "cwtl", OPLEN);
4701 else
4702 (void) strlcat(x->d86_mnem, "cltq", OPLEN);
4703 #endif
4704 wbit = LONG_OPND;
4705 NOMEM;
4706 break;
4707
4708 case CWD:
4709 #ifdef DIS_TEXT
4710 if (opnd_size == SIZE16)
4711 (void) strlcat(x->d86_mnem, "cwtd", OPLEN);
4712 else if (opnd_size == SIZE32)
4713 (void) strlcat(x->d86_mnem, "cltd", OPLEN);
4714 else
4715 (void) strlcat(x->d86_mnem, "cqtd", OPLEN);
4716 #endif
4717 wbit = LONG_OPND;
4718 NOMEM;
4719 break;
4720
4721 case XMMSFNC:
4722 /*
4723 * sfence is sfence if mode is REG_ONLY. If mode isn't
4724 * REG_ONLY, mnemonic should be 'clflush'.
4725 */
4726 dtrace_get_modrm(x, &mode, &reg, &r_m);
4727
4728 /* sfence doesn't take operands */
4729 #ifdef DIS_TEXT
4730 if (mode == REG_ONLY) {
4731 (void) strlcat(x->d86_mnem, "sfence", OPLEN);
4732 } else {
4733 (void) strlcat(x->d86_mnem, "clflush", OPLEN);
4734 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4735 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4736 NOMEM;
4737 }
4738 #else
4739 if (mode != REG_ONLY) {
4740 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4741 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4742 NOMEM;
4743 }
4744 #endif
4745 break;
4746
4747 /*
4748 * no disassembly, the mnemonic was all there was so go on
4749 */
4750 case NORM:
4751 if (dp->it_invalid32 && cpu_mode != SIZE64)
4752 goto error;
4753 NOMEM;
4754 /*FALLTHROUGH*/
4755 case IMPLMEM:
4756 break;
4757
4758 case XMMFENCE:
4759 /*
4760 * XRSTOR and LFENCE share the same opcode but differ in mode
4761 */
4762 dtrace_get_modrm(x, &mode, &reg, &r_m);
4763
4764 if (mode == REG_ONLY) {
4765 /*
4766 * Only the following exact byte sequences are allowed:
4767 *
4768 * 0f ae e8 lfence
4769 * 0f ae f0 mfence
4770 */
4771 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
4772 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
4773 goto error;
4774 } else {
4775 #ifdef DIS_TEXT
4776 (void) strncpy(x->d86_mnem, "xrstor", OPLEN);
4777 #endif
4778 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4779 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4780 }
4781 break;
4782
4783 /* float reg */
4784 case F:
4785 #ifdef DIS_TEXT
4786 x->d86_numopnds = 1;
4787 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN);
4788 x->d86_opnd[0].d86_opnd[4] = r_m + '0';
4789 #endif
4790 NOMEM;
4791 break;
4792
4793 /* float reg to float reg, with ret bit present */
4794 case FF:
4795 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */
4796 /*FALLTHROUGH*/
4797 case FFC: /* case for vbit always = 0 */
4798 #ifdef DIS_TEXT
4799 x->d86_numopnds = 2;
4800 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN);
4801 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN);
4802 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0';
4803 #endif
4804 NOMEM;
4805 break;
4806
4807 /* AVX instructions */
4808 case VEX_MO:
4809 /* op(ModR/M.r/m) */
4810 x->d86_numopnds = 1;
4811 dtrace_get_modrm(x, &mode, &reg, &r_m);
4812 #ifdef DIS_TEXT
4813 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
4814 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN);
4815 #endif
4816 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4817 dtrace_get_operand(x, mode, r_m, wbit, 0);
4818 break;
4819 case VEX_RMrX:
4820 case FMA:
4821 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
4822 x->d86_numopnds = 3;
4823 dtrace_get_modrm(x, &mode, &reg, &r_m);
4824 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4825
4826 /*
4827 * In classic Intel fashion, the opcodes for all of the FMA
4828 * instructions all have two possible mnemonics which vary by
4829 * one letter, which is selected based on the value of the wbit.
4830 * When wbit is one, they have the 'd' suffix and when 'wbit' is
4831 * 0, they have the 's' suffix. Otherwise, the FMA instructions
4832 * are all a standard VEX_RMrX.
4833 */
4834 #ifdef DIS_TEXT
4835 if (dp->it_adrmode == FMA) {
4836 size_t len = strlen(dp->it_name);
4837 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
4838 if (len + 1 < OPLEN) {
4839 (void) strncpy(x->d86_mnem + len,
4840 vex_W != 0 ? "d" : "s", OPLEN - len);
4841 }
4842 }
4843 #endif
4844
4845 if (mode != REG_ONLY) {
4846 if ((dp == &dis_opAVXF20F[0x10]) ||
4847 (dp == &dis_opAVXF30F[0x10])) {
4848 /* vmovsd <m64>, <xmm> */
4849 /* or vmovss <m64>, <xmm> */
4850 x->d86_numopnds = 2;
4851 goto L_VEX_MX;
4852 }
4853 }
4854
4855 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4856 /*
4857 * VEX prefix uses the 1's complement form to encode the
4858 * XMM/YMM regs
4859 */
4860 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4861
4862 if ((dp == &dis_opAVXF20F[0x2A]) ||
4863 (dp == &dis_opAVXF30F[0x2A])) {
4864 /*
4865 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
4866 * <xmm>, <xmm>
4867 */
4868 wbit = LONG_OPND;
4869 }
4870 #ifdef DIS_TEXT
4871 else if ((mode == REG_ONLY) &&
4872 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */
4873 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN);
4874 } else if ((mode == REG_ONLY) &&
4875 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */
4876 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN);
4877 }
4878 #endif
4879 dtrace_get_operand(x, mode, r_m, wbit, 0);
4880
4881 break;
4882
4883 case VEX_VRMrX:
4884 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
4885 x->d86_numopnds = 3;
4886 dtrace_get_modrm(x, &mode, &reg, &r_m);
4887 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4888
4889 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4890 /*
4891 * VEX prefix uses the 1's complement form to encode the
4892 * XMM/YMM regs
4893 */
4894 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0);
4895
4896 dtrace_get_operand(x, mode, r_m, wbit, 1);
4897 break;
4898
4899 case VEX_SbVM:
4900 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
4901 x->d86_numopnds = 3;
4902 x->d86_vsib = 1;
4903
4904 /*
4905 * All instructions that use VSIB are currently a mess. See the
4906 * comment around the dis_gather_regs_t structure definition.
4907 */
4908
4909 vreg = &dis_vgather[opcode2][vex_W][vex_L];
4910
4911 #ifdef DIS_TEXT
4912 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
4913 (void) strlcat(x->d86_mnem + strlen(dp->it_name),
4914 vreg->dgr_suffix, OPLEN - strlen(dp->it_name));
4915 #endif
4916
4917 dtrace_get_modrm(x, &mode, &reg, &r_m);
4918 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4919
4920 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);
4921 /*
4922 * VEX prefix uses the 1's complement form to encode the
4923 * XMM/YMM regs
4924 */
4925 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0,
4926 0);
4927 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1);
4928 break;
4929
4930 case VEX_RRX:
4931 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
4932 x->d86_numopnds = 3;
4933
4934 dtrace_get_modrm(x, &mode, &reg, &r_m);
4935 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4936
4937 if (mode != REG_ONLY) {
4938 if ((dp == &dis_opAVXF20F[0x11]) ||
4939 (dp == &dis_opAVXF30F[0x11])) {
4940 /* vmovsd <xmm>, <m64> */
4941 /* or vmovss <xmm>, <m64> */
4942 x->d86_numopnds = 2;
4943 goto L_VEX_RM;
4944 }
4945 }
4946
4947 dtrace_get_operand(x, mode, r_m, wbit, 2);
4948 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4949 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
4950 break;
4951
4952 case VEX_RMRX:
4953 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
4954 x->d86_numopnds = 4;
4955
4956 dtrace_get_modrm(x, &mode, &reg, &r_m);
4957 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4958 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
4959 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
4960 if (dp == &dis_opAVX660F3A[0x18]) {
4961 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
4962 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1);
4963 } else if ((dp == &dis_opAVX660F3A[0x20]) ||
4964 (dp == & dis_opAVX660F[0xC4])) {
4965 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
4966 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
4967 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4968 } else if (dp == &dis_opAVX660F3A[0x22]) {
4969 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
4970 #ifdef DIS_TEXT
4971 if (vex_W)
4972 x->d86_mnem[6] = 'q';
4973 #endif
4974 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4975 } else {
4976 dtrace_get_operand(x, mode, r_m, wbit, 1);
4977 }
4978
4979 /* one byte immediate number */
4980 dtrace_imm_opnd(x, wbit, 1, 0);
4981
4982 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
4983 if ((dp == &dis_opAVX660F3A[0x4A]) ||
4984 (dp == &dis_opAVX660F3A[0x4B]) ||
4985 (dp == &dis_opAVX660F3A[0x4C])) {
4986 #ifdef DIS_TEXT
4987 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4;
4988 #endif
4989 x->d86_opnd[0].d86_mode = MODE_NONE;
4990 #ifdef DIS_TEXT
4991 if (vex_L)
4992 (void) strncpy(x->d86_opnd[0].d86_opnd,
4993 dis_YMMREG[regnum], OPLEN);
4994 else
4995 (void) strncpy(x->d86_opnd[0].d86_opnd,
4996 dis_XMMREG[regnum], OPLEN);
4997 #endif
4998 }
4999 break;
5000
5001 case VEX_MX:
5002 /* ModR/M.reg := op(ModR/M.rm) */
5003 x->d86_numopnds = 2;
5004
5005 dtrace_get_modrm(x, &mode, &reg, &r_m);
5006 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5007 L_VEX_MX:
5008
5009 if ((dp == &dis_opAVXF20F[0xE6]) ||
5010 (dp == &dis_opAVX660F[0x5A]) ||
5011 (dp == &dis_opAVX660F[0xE6])) {
5012 /* vcvtpd2dq <ymm>, <xmm> */
5013 /* or vcvtpd2ps <ymm>, <xmm> */
5014 /* or vcvttpd2dq <ymm>, <xmm> */
5015 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
5016 dtrace_get_operand(x, mode, r_m, wbit, 0);
5017 } else if ((dp == &dis_opAVXF30F[0xE6]) ||
5018 (dp == &dis_opAVX0F[0x5][0xA]) ||
5019 (dp == &dis_opAVX660F38[0x13]) ||
5020 (dp == &dis_opAVX660F38[0x18]) ||
5021 (dp == &dis_opAVX660F38[0x19]) ||
5022 (dp == &dis_opAVX660F38[0x58]) ||
5023 (dp == &dis_opAVX660F38[0x78]) ||
5024 (dp == &dis_opAVX660F38[0x79]) ||
5025 (dp == &dis_opAVX660F38[0x59])) {
5026 /* vcvtdq2pd <xmm>, <ymm> */
5027 /* or vcvtps2pd <xmm>, <ymm> */
5028 /* or vcvtph2ps <xmm>, <ymm> */
5029 /* or vbroadcasts* <xmm>, <ymm> */
5030 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5031 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
5032 } else if (dp == &dis_opAVX660F[0x6E]) {
5033 /* vmovd/q <reg/mem 32/64>, <xmm> */
5034 #ifdef DIS_TEXT
5035 if (vex_W)
5036 x->d86_mnem[4] = 'q';
5037 #endif
5038 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5039 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
5040 } else {
5041 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5042 dtrace_get_operand(x, mode, r_m, wbit, 0);
5043 }
5044
5045 break;
5046
5047 case VEX_MXI:
5048 /* ModR/M.reg := op(ModR/M.rm, imm8) */
5049 x->d86_numopnds = 3;
5050
5051 dtrace_get_modrm(x, &mode, &reg, &r_m);
5052 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5053
5054 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5055 dtrace_get_operand(x, mode, r_m, wbit, 1);
5056
5057 /* one byte immediate number */
5058 dtrace_imm_opnd(x, wbit, 1, 0);
5059 break;
5060
5061 case VEX_XXI:
5062 /* VEX.vvvv := op(ModR/M.rm, imm8) */
5063 x->d86_numopnds = 3;
5064
5065 dtrace_get_modrm(x, &mode, &reg, &r_m);
5066 #ifdef DIS_TEXT
5067 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
5068 OPLEN);
5069 #endif
5070 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5071
5072 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
5073 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1);
5074
5075 /* one byte immediate number */
5076 dtrace_imm_opnd(x, wbit, 1, 0);
5077 break;
5078
5079 case VEX_MR:
5080 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
5081 if (dp == &dis_opAVX660F[0xC5]) {
5082 /* vpextrw <imm8>, <xmm>, <reg> */
5083 x->d86_numopnds = 2;
5084 vbit = 2;
5085 } else {
5086 x->d86_numopnds = 2;
5087 vbit = 1;
5088 }
5089
5090 dtrace_get_modrm(x, &mode, &reg, &r_m);
5091 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5092 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
5093 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1);
5094
5095 if (vbit == 2)
5096 dtrace_imm_opnd(x, wbit, 1, 0);
5097
5098 break;
5099
5100 case VEX_RRI:
5101 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
5102 x->d86_numopnds = 2;
5103
5104 dtrace_get_modrm(x, &mode, &reg, &r_m);
5105 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5106 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5107 dtrace_get_operand(x, mode, r_m, wbit, 0);
5108 break;
5109
5110 case VEX_RX:
5111 /* ModR/M.rm := op(ModR/M.reg) */
5112 /* vextractf128 || vcvtps2ph */
5113 if (dp == &dis_opAVX660F3A[0x19] ||
5114 dp == &dis_opAVX660F3A[0x1d]) {
5115 x->d86_numopnds = 3;
5116
5117 dtrace_get_modrm(x, &mode, &reg, &r_m);
5118 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5119
5120 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
5121 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5122
5123 /* one byte immediate number */
5124 dtrace_imm_opnd(x, wbit, 1, 0);
5125 break;
5126 }
5127
5128 x->d86_numopnds = 2;
5129
5130 dtrace_get_modrm(x, &mode, &reg, &r_m);
5131 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5132 dtrace_get_operand(x, mode, r_m, wbit, 1);
5133 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5134 break;
5135
5136 case VEX_RR:
5137 /* ModR/M.rm := op(ModR/M.reg) */
5138 x->d86_numopnds = 2;
5139
5140 dtrace_get_modrm(x, &mode, &reg, &r_m);
5141 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5142
5143 if (dp == &dis_opAVX660F[0x7E]) {
5144 /* vmovd/q <reg/mem 32/64>, <xmm> */
5145 #ifdef DIS_TEXT
5146 if (vex_W)
5147 x->d86_mnem[4] = 'q';
5148 #endif
5149 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
5150 } else
5151 dtrace_get_operand(x, mode, r_m, wbit, 1);
5152
5153 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5154 break;
5155
5156 case VEX_RRi:
5157 /* ModR/M.rm := op(ModR/M.reg, imm) */
5158 x->d86_numopnds = 3;
5159
5160 dtrace_get_modrm(x, &mode, &reg, &r_m);
5161 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5162
5163 #ifdef DIS_TEXT
5164 if (dp == &dis_opAVX660F3A[0x16]) {
5165 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
5166 if (vex_W)
5167 x->d86_mnem[6] = 'q';
5168 }
5169 #endif
5170 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
5171 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5172
5173 /* one byte immediate number */
5174 dtrace_imm_opnd(x, wbit, 1, 0);
5175 break;
5176 case VEX_RIM:
5177 /* ModR/M.rm := op(ModR/M.reg, imm) */
5178 x->d86_numopnds = 3;
5179
5180 dtrace_get_modrm(x, &mode, &reg, &r_m);
5181 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5182
5183 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
5184 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5185 /* one byte immediate number */
5186 dtrace_imm_opnd(x, wbit, 1, 0);
5187 break;
5188
5189 case VEX_RM:
5190 /* ModR/M.rm := op(ModR/M.reg) */
5191 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */
5192 x->d86_numopnds = 3;
5193
5194 dtrace_get_modrm(x, &mode, &reg, &r_m);
5195 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5196
5197 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
5198 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5199 /* one byte immediate number */
5200 dtrace_imm_opnd(x, wbit, 1, 0);
5201 break;
5202 }
5203 x->d86_numopnds = 2;
5204
5205 dtrace_get_modrm(x, &mode, &reg, &r_m);
5206 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5207 L_VEX_RM:
5208 vbit = 1;
5209 dtrace_get_operand(x, mode, r_m, wbit, vbit);
5210 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
5211
5212 break;
5213
5214 case VEX_RRM:
5215 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
5216 x->d86_numopnds = 3;
5217
5218 dtrace_get_modrm(x, &mode, &reg, &r_m);
5219 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5220 dtrace_get_operand(x, mode, r_m, wbit, 2);
5221 /* VEX use the 1's complement form encode the XMM/YMM regs */
5222 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5223 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5224 break;
5225
5226 case VEX_RMX:
5227 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
5228 x->d86_numopnds = 3;
5229
5230 dtrace_get_modrm(x, &mode, &reg, &r_m);
5231 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5232 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5233 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5234 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0);
5235 break;
5236
5237 case VEX_NONE:
5238 #ifdef DIS_TEXT
5239 if (vex_L)
5240 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN);
5241 #endif
5242 break;
5243 case BLS: {
5244
5245 /*
5246 * The BLS instructions are VEX instructions that are based on
5247 * VEX.0F38.F3; however, they are considered special group 17
5248 * and like everything else, they use the bits in 3-5 of the
5249 * MOD R/M to determine the sub instruction. Unlike many others
5250 * like the VMX instructions, these are valid both for memory
5251 * and register forms.
5252 */
5253
5254 dtrace_get_modrm(x, &mode, &reg, &r_m);
5255 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5256
5257 switch (reg) {
5258 case 1:
5259 #ifdef DIS_TEXT
5260 blsinstr = "blsr";
5261 #endif
5262 break;
5263 case 2:
5264 #ifdef DIS_TEXT
5265 blsinstr = "blsmsk";
5266 #endif
5267 break;
5268 case 3:
5269 #ifdef DIS_TEXT
5270 blsinstr = "blsi";
5271 #endif
5272 break;
5273 default:
5274 goto error;
5275 }
5276
5277 x->d86_numopnds = 2;
5278 #ifdef DIS_TEXT
5279 (void) strncpy(x->d86_mnem, blsinstr, OPLEN);
5280 #endif
5281 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5282 dtrace_get_operand(x, mode, r_m, wbit, 0);
5283 break;
5284 }
5285 /* an invalid op code */
5286 case AM:
5287 case DM:
5288 case OVERRIDE:
5289 case PREFIX:
5290 case UNKNOWN:
5291 NOMEM;
5292 default:
5293 goto error;
5294 } /* end switch */
5295 if (x->d86_error)
5296 goto error;
5297
5298 done:
5299 #ifdef DIS_MEM
5300 /*
5301 * compute the size of any memory accessed by the instruction
5302 */
5303 if (x->d86_memsize != 0) {
5304 return (0);
5305 } else if (dp->it_stackop) {
5306 switch (opnd_size) {
5307 case SIZE16:
5308 x->d86_memsize = 2;
5309 break;
5310 case SIZE32:
5311 x->d86_memsize = 4;
5312 break;
5313 case SIZE64:
5314 x->d86_memsize = 8;
5315 break;
5316 }
5317 } else if (nomem || mode == REG_ONLY) {
5318 x->d86_memsize = 0;
5319
5320 } else if (dp->it_size != 0) {
5321 /*
5322 * In 64 bit mode descriptor table entries
5323 * go up to 10 bytes and popf/pushf are always 8 bytes
5324 */
5325 if (x->d86_mode == SIZE64 && dp->it_size == 6)
5326 x->d86_memsize = 10;
5327 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 &&
5328 (opcode2 == 0xc || opcode2 == 0xd))
5329 x->d86_memsize = 8;
5330 else
5331 x->d86_memsize = dp->it_size;
5332
5333 } else if (wbit == 0) {
5334 x->d86_memsize = 1;
5335
5336 } else if (wbit == LONG_OPND) {
5337 if (opnd_size == SIZE64)
5338 x->d86_memsize = 8;
5339 else if (opnd_size == SIZE32)
5340 x->d86_memsize = 4;
5341 else
5342 x->d86_memsize = 2;
5343
5344 } else if (wbit == SEG_OPND) {
5345 x->d86_memsize = 4;
5346
5347 } else {
5348 x->d86_memsize = 8;
5349 }
5350 #endif
5351 return (0);
5352
5353 error:
5354 #ifdef DIS_TEXT
5355 (void) strlcat(x->d86_mnem, "undef", OPLEN);
5356 #endif
5357 return (1);
5358 }
5359
5360 #ifdef DIS_TEXT
5361
5362 /*
5363 * Some instructions should have immediate operands printed
5364 * as unsigned integers. We compare against this table.
5365 */
5366 static char *unsigned_ops[] = {
5367 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp",
5368 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl",
5369 0
5370 };
5371
5372
5373 static int
5374 isunsigned_op(char *opcode)
5375 {
5376 char *where;
5377 int i;
5378 int is_unsigned = 0;
5379
5380 /*
5381 * Work back to start of last mnemonic, since we may have
5382 * prefixes on some opcodes.
5383 */
5384 where = opcode + strlen(opcode) - 1;
5385 while (where > opcode && *where != ' ')
5386 --where;
5387 if (*where == ' ')
5388 ++where;
5389
5390 for (i = 0; unsigned_ops[i]; ++i) {
5391 if (strncmp(where, unsigned_ops[i],
5392 strlen(unsigned_ops[i])))
5393 continue;
5394 is_unsigned = 1;
5395 break;
5396 }
5397 return (is_unsigned);
5398 }
5399
5400 /*
5401 * Print a numeric immediate into end of buf, maximum length buflen.
5402 * The immediate may be an address or a displacement. Mask is set
5403 * for address size. If the immediate is a "small negative", or
5404 * if it's a negative displacement of any magnitude, print as -<absval>.
5405 * Respect the "octal" flag. "Small negative" is defined as "in the
5406 * interval [NEG_LIMIT, 0)".
5407 *
5408 * Also, "isunsigned_op()" instructions never print negatives.
5409 *
5410 * Return whether we decided to print a negative value or not.
5411 */
5412
5413 #define NEG_LIMIT -255
5414 enum {IMM, DISP};
5415 enum {POS, TRY_NEG};
5416
5417 static int
5418 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf,
5419 size_t buflen, int disp, int try_neg)
5420 {
5421 int curlen;
5422 int64_t sv = (int64_t)usv;
5423 int octal = dis->d86_flags & DIS_F_OCTAL;
5424
5425 curlen = strlen(buf);
5426
5427 if (try_neg == TRY_NEG && sv < 0 &&
5428 (disp || sv >= NEG_LIMIT) &&
5429 !isunsigned_op(dis->d86_mnem)) {
5430 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5431 octal ? "-0%llo" : "-0x%llx", (-sv) & mask);
5432 return (1);
5433 } else {
5434 if (disp == DISP)
5435 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5436 octal ? "+0%llo" : "+0x%llx", usv & mask);
5437 else
5438 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5439 octal ? "0%llo" : "0x%llx", usv & mask);
5440 return (0);
5441
5442 }
5443 }
5444
5445
5446 static int
5447 log2(int size)
5448 {
5449 switch (size) {
5450 case 1: return (0);
5451 case 2: return (1);
5452 case 4: return (2);
5453 case 8: return (3);
5454 }
5455 return (0);
5456 }
5457
5458 /* ARGSUSED */
5459 void
5460 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,
5461 size_t buflen)
5462 {
5463 uint64_t reltgt = 0;
5464 uint64_t tgt = 0;
5465 int curlen;
5466 int (*lookup)(void *, uint64_t, char *, size_t);
5467 int i;
5468 int64_t sv;
5469 uint64_t usv, mask, save_mask, save_usv;
5470 static uint64_t masks[] =
5471 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL};
5472 save_usv = 0;
5473
5474 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem);
5475
5476 /*
5477 * For PC-relative jumps, the pc is really the next pc after executing
5478 * this instruction, so increment it appropriately.
5479 */
5480 pc += dis->d86_len;
5481
5482 for (i = 0; i < dis->d86_numopnds; i++) {
5483 d86opnd_t *op = &dis->d86_opnd[i];
5484
5485 if (i != 0)
5486 (void) strlcat(buf, ",", buflen);
5487
5488 (void) strlcat(buf, op->d86_prefix, buflen);
5489
5490 /*
5491 * sv is for the signed, possibly-truncated immediate or
5492 * displacement; usv retains the original size and
5493 * unsignedness for symbol lookup.
5494 */
5495
5496 sv = usv = op->d86_value;
5497
5498 /*
5499 * About masks: for immediates that represent
5500 * addresses, the appropriate display size is
5501 * the effective address size of the instruction.
5502 * This includes MODE_OFFSET, MODE_IPREL, and
5503 * MODE_RIPREL. Immediates that are simply
5504 * immediate values should display in the operand's
5505 * size, however, since they don't represent addresses.
5506 */
5507
5508 /* d86_addr_size is SIZEnn, which is log2(real size) */
5509 mask = masks[dis->d86_addr_size];
5510
5511 /* d86_value_size and d86_imm_bytes are in bytes */
5512 if (op->d86_mode == MODE_SIGNED ||
5513 op->d86_mode == MODE_IMPLIED)
5514 mask = masks[log2(op->d86_value_size)];
5515
5516 switch (op->d86_mode) {
5517
5518 case MODE_NONE:
5519
5520 (void) strlcat(buf, op->d86_opnd, buflen);
5521 break;
5522
5523 case MODE_SIGNED:
5524 case MODE_IMPLIED:
5525 case MODE_OFFSET:
5526
5527 tgt = usv;
5528
5529 if (dis->d86_seg_prefix)
5530 (void) strlcat(buf, dis->d86_seg_prefix,
5531 buflen);
5532
5533 if (op->d86_mode == MODE_SIGNED ||
5534 op->d86_mode == MODE_IMPLIED) {
5535 (void) strlcat(buf, "$", buflen);
5536 }
5537
5538 if (print_imm(dis, usv, mask, buf, buflen,
5539 IMM, TRY_NEG) &&
5540 (op->d86_mode == MODE_SIGNED ||
5541 op->d86_mode == MODE_IMPLIED)) {
5542
5543 /*
5544 * We printed a negative value for an
5545 * immediate that wasn't a
5546 * displacement. Note that fact so we can
5547 * print the positive value as an
5548 * annotation.
5549 */
5550
5551 save_usv = usv;
5552 save_mask = mask;
5553 }
5554 (void) strlcat(buf, op->d86_opnd, buflen);
5555
5556 break;
5557
5558 case MODE_IPREL:
5559 case MODE_RIPREL:
5560
5561 reltgt = pc + sv;
5562
5563 switch (mode) {
5564 case SIZE16:
5565 reltgt = (uint16_t)reltgt;
5566 break;
5567 case SIZE32:
5568 reltgt = (uint32_t)reltgt;
5569 break;
5570 }
5571
5572 (void) print_imm(dis, usv, mask, buf, buflen,
5573 DISP, TRY_NEG);
5574
5575 if (op->d86_mode == MODE_RIPREL)
5576 (void) strlcat(buf, "(%rip)", buflen);
5577 break;
5578 }
5579 }
5580
5581 /*
5582 * The symbol lookups may result in false positives,
5583 * particularly on object files, where small numbers may match
5584 * the 0-relative non-relocated addresses of symbols.
5585 */
5586
5587 lookup = dis->d86_sym_lookup;
5588 if (tgt != 0) {
5589 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 &&
5590 lookup(dis->d86_data, tgt, NULL, 0) == 0) {
5591 (void) strlcat(buf, "\t<", buflen);
5592 curlen = strlen(buf);
5593 lookup(dis->d86_data, tgt, buf + curlen,
5594 buflen - curlen);
5595 (void) strlcat(buf, ">", buflen);
5596 }
5597
5598 /*
5599 * If we printed a negative immediate above, print the
5600 * positive in case our heuristic was unhelpful
5601 */
5602 if (save_usv) {
5603 (void) strlcat(buf, "\t<", buflen);
5604 (void) print_imm(dis, save_usv, save_mask, buf, buflen,
5605 IMM, POS);
5606 (void) strlcat(buf, ">", buflen);
5607 }
5608 }
5609
5610 if (reltgt != 0) {
5611 /* Print symbol or effective address for reltgt */
5612
5613 (void) strlcat(buf, "\t<", buflen);
5614 curlen = strlen(buf);
5615 lookup(dis->d86_data, reltgt, buf + curlen,
5616 buflen - curlen);
5617 (void) strlcat(buf, ">", buflen);
5618 }
5619 }
5620
5621 #endif /* DIS_TEXT */
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