osfmk/ppc/scc_8530.h

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  34 /*
  35  * Mach Operating System
  36  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
  37  * All Rights Reserved.
  38  *
  39  * Permission to use, copy, modify and distribute this software and its
  40  * documentation is hereby granted, provided that both the copyright
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  42  * software, derivative works or modified versions, and any portions
  43  * thereof, and that both notices appear in supporting documentation.
  44  *
  45  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  46  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  47  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  48  *
  49  * Carnegie Mellon requests users of this software to return to
  50  *
  51  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  52  *  School of Computer Science
  53  *  Carnegie Mellon University
  54  *  Pittsburgh PA 15213-3890
  55  *
  56  * any improvements or extensions that they make and grant Carnegie Mellon
  57  * the rights to redistribute these changes.
  58  */
  59 /*
  60  */
  61 /*
  62  *      File: scc_8530.h
  63  *      Author: Alessandro Forin, Carnegie Mellon University
  64  *      Date:   6/91
  65  *
  66  *      Definitions for the Zilog Z8530 SCC serial line chip
  67  */
  68
  69 #ifndef _SCC_8530_H_
  70 #define _SCC_8530_H_
  71
  72 /*
  73  * Register map, needs definition of the alignment
  74  * used on the specific machine.
  75  * #define the 'scc_register_t' data type before
  76  * including this header file.  For restrictions on
  77  * access modes define the set/get_datum macros.
  78  * We provide defaults ifnot.
  79  */
  80
  81
  82 #define SCC_CHANNEL_A   1
  83 #define SCC_CHANNEL_B   0
  84
  85 #define SCC_MODEM       SCC_CHANNEL_A
  86 #define SCC_PRINTER     SCC_CHANNEL_B
  87
  88 #define SCC_DATA_OFFSET 4
  89
  90 typedef unsigned char *scc_regmap_t;
  91
  92 extern void     powermac_scc_set_datum(scc_regmap_t regs, unsigned int offset, unsigned char value);
  93 extern unsigned char powermac_scc_get_datum(scc_regmap_t regs, unsigned int offset);
  94
  95 #define scc_set_datum(regs, d, v)       powermac_scc_set_datum(regs, (d), (v))
  96 #define scc_get_datum(regs, d,v)        (v)  = powermac_scc_get_datum(regs, (d));
  97
  98 #define scc_init_reg(regs,chan)         { \
  99                 char tmp; \
 100                 scc_get_datum(regs, ((chan)<<1),tmp); \
 101                 scc_get_datum(regs, ((chan)<<1),tmp); \
 102         }
 103
 104 #define scc_read_reg(regs,chan,reg,val) { \
 105                 scc_set_datum(regs, ((chan)<<1),reg); \
 106                 scc_get_datum(regs, ((chan)<<1),val); \
 107         }
 108
 109 #define scc_read_reg_zero(regs,chan,val)        { \
 110                 scc_get_datum(regs, ((chan)<<1),val); \
 111         }
 112
 113 #define scc_write_reg(regs,chan,reg,val)        { \
 114                 scc_set_datum(regs, ((chan)<<1),reg); \
 115                 scc_set_datum(regs, ((chan)<<1),val); \
 116         }
 117
 118 #define scc_write_reg_zero(regs,chan,val) { \
 119                 scc_set_datum(regs, ((chan)<<1),val); \
 120         }
 121
 122 #define scc_read_data(regs,chan,val)    { \
 123                 scc_get_datum(regs, ((chan)<<1)+SCC_DATA_OFFSET,val); \
 124         }
 125
 126 #define scc_write_data(regs,chan,val) { \
 127                 scc_set_datum(regs, ((chan)<<1)+SCC_DATA_OFFSET,val); \
 128         }
 129
 130
 131 /*
 132  * Addressable registers
 133  */
 134
 135 #define SCC_RR0         0       /* status register */
 136 #define SCC_RR1         1       /* special receive conditions */
 137 #define SCC_RR2         2       /* (modified) interrupt vector */
 138 #define SCC_RR3         3       /* interrupts pending (cha A only) */
 139 #define SCC_RR8         8       /* recv buffer (alias for data) */
 140 #define SCC_RR10        10      /* sdlc status */
 141 #define SCC_RR12        12      /* BRG constant, low part */
 142 #define SCC_RR13        13      /* BRG constant, high part */
 143 #define SCC_RR15        15      /* interrupts currently enabled */
 144
 145 #define SCC_WR0         0       /* reg select, and commands */
 146 #define SCC_WR1         1       /* interrupt and DMA enables */
 147 #define SCC_WR2         2       /* interrupt vector */
 148 #define SCC_WR3         3       /* receiver params and enables */
 149 #define SCC_WR4         4       /* clock/char/parity params */
 150 #define SCC_WR5         5       /* xmit params and enables */
 151 #define SCC_WR6         6       /* synchr SYNCH/address */
 152 #define SCC_WR7         7       /* synchr SYNCH/flag */
 153 #define SCC_WR8         8       /* xmit buffer (alias for data) */
 154 #define SCC_WR9         9       /* vectoring and resets */
 155 #define SCC_WR10        10      /* synchr params */
 156 #define SCC_WR11        11      /* clocking definitions */
 157 #define SCC_WR12        12      /* BRG constant, low part */
 158 #define SCC_WR13        13      /* BRG constant, high part */
 159 #define SCC_WR14        14      /* BRG enables and commands */
 160 #define SCC_WR15        15      /* interrupt enables */
 161
 162 /*
 163  * Read registers defines
 164  */
 165
 166 #define SCC_RR0_BREAK           0x80    /* break detected (rings twice), or */
 167 #define SCC_RR0_ABORT           0x80    /* abort (synchr) */
 168 #define SCC_RR0_TX_UNDERRUN     0x40    /* xmit buffer empty/end of message */
 169 #define SCC_RR0_CTS             0x20    /* clear-to-send pin active (sampled
 170                                            only on intr and after RESI cmd */
 171 #define SCC_RR0_SYNCH           0x10    /* SYNCH found/still hunting */
 172 #define SCC_RR0_DCD             0x08    /* carrier-detect (same as CTS) */
 173 #define SCC_RR0_TX_EMPTY        0x04    /* xmit buffer empty */
 174 #define SCC_RR0_ZERO_COUNT      0x02    /* ? */
 175 #define SCC_RR0_RX_AVAIL        0x01    /* recv fifo not empty */
 176
 177 #define SCC_RR1_EOF             0x80    /* end-of-frame, SDLC mode */
 178 #define SCC_RR1_CRC_ERR         0x40    /* incorrect CRC or.. */
 179 #define SCC_RR1_FRAME_ERR       0x40    /* ..bad frame */
 180 #define SCC_RR1_RX_OVERRUN      0x20    /* rcv fifo overflow */
 181 #define SCC_RR1_PARITY_ERR      0x10    /* incorrect parity in data */
 182 #define SCC_RR1_RESIDUE0        0x08
 183 #define SCC_RR1_RESIDUE1        0x04
 184 #define SCC_RR1_RESIDUE2        0x02
 185 #define SCC_RR1_ALL_SENT        0x01
 186
 187 /* RR2 contains the interrupt vector unmodified (channel A) or
 188    modified as follows (channel B, if vector-include-status) */
 189
 190 #define SCC_RR2_STATUS(val)     ((val)&0xe)     /* 11/7/95 used to be 0xf */
 191
 192 #define SCC_RR2_B_XMIT_DONE     0x0
 193 #define SCC_RR2_B_EXT_STATUS    0x2
 194 #define SCC_RR2_B_RECV_DONE     0x4
 195 #define SCC_RR2_B_RECV_SPECIAL  0x6
 196 #define SCC_RR2_A_XMIT_DONE     0x8
 197 #define SCC_RR2_A_EXT_STATUS    0xa
 198 #define SCC_RR2_A_RECV_DONE     0xc
 199 #define SCC_RR2_A_RECV_SPECIAL  0xe
 200
 201 /* Interrupts pending, to be read from channel A only (B raz) */
 202 #define SCC_RR3_zero            0xc0
 203 #define SCC_RR3_RX_IP_A         0x20
 204 #define SCC_RR3_TX_IP_A         0x10
 205 #define SCC_RR3_EXT_IP_A        0x08
 206 #define SCC_RR3_RX_IP_B         0x04
 207 #define SCC_RR3_TX_IP_B         0x02
 208 #define SCC_RR3_EXT_IP_B        0x01
 209
 210 /* RR8 is the receive data buffer, a 3 deep FIFO */
 211 #define SCC_RECV_BUFFER         SCC_RR8
 212 #define SCC_RECV_FIFO_DEEP      3
 213
 214 #define SCC_RR10_1CLKS          0x80
 215 #define SCC_RR10_2CLKS          0x40
 216 #define SCC_RR10_zero           0x2d
 217 #define SCC_RR10_LOOP_SND       0x10
 218 #define SCC_RR10_ON_LOOP        0x02
 219
 220 /* RR12/RR13 hold the timing base, upper byte in RR13 */
 221
 222 #define scc_get_timing_base(scc,chan,val)       { \
 223                 register char   tmp;    \
 224                 scc_read_reg(scc,chan,SCC_RR12,val);\
 225                 scc_read_reg(scc,chan,SCC_RR13,tmp);\
 226                 (val) = ((val)<<8)|(tmp&0xff);\
 227         }
 228
 229 #define SCC_RR15_BREAK_IE       0x80
 230 #define SCC_RR15_TX_UNDERRUN_IE 0x40
 231 #define SCC_RR15_CTS_IE         0x20
 232 #define SCC_RR15_SYNCH_IE       0x10
 233 #define SCC_RR15_DCD_IE         0x08
 234 #define SCC_RR15_zero           0x05
 235 #define SCC_RR15_ZERO_COUNT_IE  0x02
 236
 237
 238 /*
 239  * Write registers defines
 240  */
 241
 242 /* WR0 is used for commands too */
 243 #define SCC_RESET_TXURUN_LATCH  0xc0
 244 #define SCC_RESET_TX_CRC        0x80
 245 #define SCC_RESET_RX_CRC        0x40
 246 #define SCC_RESET_HIGHEST_IUS   0x38    /* channel A only */
 247 #define SCC_RESET_ERROR         0x30
 248 #define SCC_RESET_TX_IP         0x28
 249 #define SCC_IE_NEXT_CHAR        0x20
 250 #define SCC_SEND_SDLC_ABORT     0x18
 251 #define SCC_RESET_EXT_IP        0x10
 252
 253 #define SCC_WR1_DMA_ENABLE      0x80    /* dma control */
 254 #define SCC_WR1_DMA_MODE        0x40    /* drive ~req for DMA controller */
 255 #define SCC_WR1_DMA_RECV_DATA   0x20    /* from wire to host memory */
 256                                         /* interrupt enable/conditions */
 257 #define SCC_WR1_RXI_SPECIAL_O   0x18    /* on special only */
 258 #define SCC_WR1_RXI_ALL_CHAR    0x10    /* on each char, or special */
 259 #define SCC_WR1_RXI_FIRST_CHAR  0x08    /* on first char, or special */
 260 #define SCC_WR1_RXI_DISABLE     0x00    /* never on recv */
 261 #define SCC_WR1_PARITY_IE       0x04    /* on parity errors */
 262 #define SCC_WR1_TX_IE           0x02
 263 #define SCC_WR1_EXT_IE          0x01
 264
 265 /* WR2 is common and contains the interrupt vector (high nibble) */
 266
 267 #define SCC_WR3_RX_8_BITS       0xc0
 268 #define SCC_WR3_RX_6_BITS       0x80
 269 #define SCC_WR3_RX_7_BITS       0x40
 270 #define SCC_WR3_RX_5_BITS       0x00
 271 #define SCC_WR3_AUTO_ENABLE     0x20
 272 #define SCC_WR3_HUNT_MODE       0x10
 273 #define SCC_WR3_RX_CRC_ENABLE   0x08
 274 #define SCC_WR3_SDLC_SRCH       0x04
 275 #define SCC_WR3_INHIBIT_SYNCH   0x02
 276 #define SCC_WR3_RX_ENABLE       0x01
 277
 278 /* Should be re-written after reset */
 279 #define SCC_WR4_CLK_x64         0xc0    /* clock divide factor */
 280 #define SCC_WR4_CLK_x32         0x80
 281 #define SCC_WR4_CLK_x16         0x40
 282 #define SCC_WR4_CLK_x1          0x00
 283 #define SCC_WR4_EXT_SYNCH_MODE  0x30    /* synch modes */
 284 #define SCC_WR4_SDLC_MODE       0x20
 285 #define SCC_WR4_16BIT_SYNCH     0x10
 286 #define SCC_WR4_8BIT_SYNCH      0x00
 287 #define SCC_WR4_2_STOP          0x0c    /* asynch modes */
 288 #define SCC_WR4_1_5_STOP        0x08
 289 #define SCC_WR4_1_STOP          0x04
 290 #define SCC_WR4_SYNCH_MODE      0x00
 291 #define SCC_WR4_EVEN_PARITY     0x02
 292 #define SCC_WR4_PARITY_ENABLE   0x01
 293
 294 #define SCC_WR5_DTR             0x80    /* drive DTR pin */
 295 #define SCC_WR5_TX_8_BITS       0x60
 296 #define SCC_WR5_TX_6_BITS       0x40
 297 #define SCC_WR5_TX_7_BITS       0x20
 298 #define SCC_WR5_TX_5_BITS       0x00
 299 #define SCC_WR5_SEND_BREAK      0x10
 300 #define SCC_WR5_TX_ENABLE       0x08
 301 #define SCC_WR5_CRC_16          0x04    /* CRC if non zero, .. */
 302 #define SCC_WR5_SDLC            0x00    /* ..SDLC otherwise  */
 303 #define SCC_WR5_RTS             0x02    /* drive RTS pin */
 304 #define SCC_WR5_TX_CRC_ENABLE   0x01
 305
 306 /* Registers WR6 and WR7 are for synch modes data, with among other things: */
 307
 308 #define SCC_WR6_BISYNCH_12      0x0f
 309 #define SCC_WR6_SDLC_RANGE_MASK 0x0f
 310 #define SCC_WR7_SDLC_FLAG       0x7e
 311
 312 /* Register WR7' (prime) controls some ESCC features */
 313 #define SCC_WR7P_RX_FIFO        0x08    /* Enable interrupt on FIFO 1/2 full */
 314
 315 /* WR8 is the transmit data buffer (no FIFO) */
 316 #define SCC_XMT_BUFFER          SCC_WR8
 317
 318 #define SCC_WR9_HW_RESET        0xc0    /* force hardware reset */
 319 #define SCC_WR9_RESET_CHA_A     0x80
 320 #define SCC_WR9_RESET_CHA_B     0x40
 321 #define SCC_WR9_NON_VECTORED    0x20    /* mbz for Zilog chip */
 322 #define SCC_WR9_STATUS_HIGH     0x10
 323 #define SCC_WR9_MASTER_IE       0x08
 324 #define SCC_WR9_DLC             0x04    /* disable-lower-chain */
 325 #define SCC_WR9_NV              0x02    /* no vector */
 326 #define SCC_WR9_VIS             0x01    /* vector-includes-status */
 327
 328 #define SCC_WR10_CRC_PRESET     0x80
 329 #define SCC_WR10_FM0            0x60
 330 #define SCC_WR10_FM1            0x40
 331 #define SCC_WR10_NRZI           0x20
 332 #define SCC_WR10_NRZ            0x00
 333 #define SCC_WR10_ACTIVE_ON_POLL 0x10
 334 #define SCC_WR10_MARK_IDLE      0x08    /* flag if zero */
 335 #define SCC_WR10_ABORT_ON_URUN  0x04    /* flag if zero */
 336 #define SCC_WR10_LOOP_MODE      0x02
 337 #define SCC_WR10_6BIT_SYNCH     0x01
 338 #define SCC_WR10_8BIT_SYNCH     0x00
 339
 340 #define SCC_WR11_RTxC_XTAL      0x80    /* RTxC pin is input (ext oscill) */
 341 #define SCC_WR11_RCLK_DPLL      0x60    /* clock received data on dpll */
 342 #define SCC_WR11_RCLK_BAUDR     0x40    /* .. on BRG */
 343 #define SCC_WR11_RCLK_TRc_PIN   0x20    /* .. on TRxC pin */
 344 #define SCC_WR11_RCLK_RTc_PIN   0x00    /* .. on RTxC pin */
 345 #define SCC_WR11_XTLK_DPLL      0x18
 346 #define SCC_WR11_XTLK_BAUDR     0x10
 347 #define SCC_WR11_XTLK_TRc_PIN   0x08
 348 #define SCC_WR11_XTLK_RTc_PIN   0x00
 349 #define SCC_WR11_TRc_OUT        0x04    /* drive TRxC pin as output from..*/
 350 #define SCC_WR11_TRcOUT_DPLL    0x03    /* .. the dpll */
 351 #define SCC_WR11_TRcOUT_BAUDR   0x02    /* .. the BRG */
 352 #define SCC_WR11_TRcOUT_XMTCLK  0x01    /* .. the xmit clock */
 353 #define SCC_WR11_TRcOUT_XTAL    0x00    /* .. the external oscillator */
 354
 355 /* WR12/WR13 are for timing base preset */
 356 #define scc_set_timing_base(scc,chan,val)       { \
 357                 scc_write_reg(scc,chan,SCC_RR12,val);\
 358                 scc_write_reg(scc,chan,SCC_RR13,(val)>>8);\
 359         }
 360
 361 /* More commands in this register */
 362 #define SCC_WR14_NRZI_MODE      0xe0    /* synch modulations */
 363 #define SCC_WR14_FM_MODE        0xc0
 364 #define SCC_WR14_RTc_SOURCE     0xa0    /* clock is from pin .. */
 365 #define SCC_WR14_BAUDR_SOURCE   0x80    /* .. or internal BRG */
 366 #define SCC_WR14_DISABLE_DPLL   0x60
 367 #define SCC_WR14_RESET_CLKMISS  0x40
 368 #define SCC_WR14_SEARCH_MODE    0x20
 369 /* ..and more bitsy */
 370 #define SCC_WR14_LOCAL_LOOPB    0x10
 371 #define SCC_WR14_AUTO_ECHO      0x08
 372 #define SCC_WR14_DTR_REQUEST    0x04
 373 #define SCC_WR14_BAUDR_SRC      0x02
 374 #define SCC_WR14_BAUDR_ENABLE   0x01
 375
 376 #define SCC_WR15_BREAK_IE       0x80
 377 #define SCC_WR15_TX_UNDERRUN_IE 0x40
 378 #define SCC_WR15_CTS_IE         0x20
 379 #define SCC_WR15_SYNCHUNT_IE    0x10
 380 #define SCC_WR15_DCD_IE         0x08
 381 #define SCC_WR15_zero           0x05
 382 #define SCC_WR15_ZERO_COUNT_IE  0x02
 383 #define SCC_WR15_ENABLE_ESCC    0x01    /* Enable some ESCC registers */
 384
 385 #define NSCC_LINE               2       /* How many lines are support per 8530 */
 386 /*
 387  * Driver status
 388  */
 389
 390 #define SCC_FLAGS_DMA_PAUSED    0x00001         /* DMA has been paused because of XON/XOFF */
 391 #define SCC_FLAGS_DMA_TX_BUSY   0x00002         /* On going DMA operation.. */
 392
 393 struct scc_softreg {
 394         unsigned char   wr1;
 395         unsigned char   wr4;
 396         unsigned char   wr5;
 397         unsigned char   wr14;
 398
 399         unsigned long   speed;
 400         unsigned long   flags;
 401         unsigned long   dma_flags;
 402 };
 403
 404
 405 struct scc_softc {
 406         scc_regmap_t            regs;
 407         struct scc_dma_ops      *dma_ops;
 408
 409         /* software copy of some write regs, for reg |= */
 410         struct scc_softreg softr[NSCC_LINE];
 411
 412         int             flags;
 413         int             modem[NSCC_LINE]; /* Mach modem bits (TM_DTR etc). */
 414         int             dcd_timer[NSCC_LINE];
 415         int             dma_initted;
 416
 417         char            polling_mode;
 418         char            probed_once;
 419
 420         boolean_t               full_modem;
 421 };
 422
 423 #define DCD_TIMEOUT 4
 424
 425 typedef struct scc_softc *scc_softc_t;
 426 extern struct scc_softc         scc_softc[];
 427
 428 #endif  /*_SCC_8530_H_*/