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1 /*
2 * Copyright (c) 2004-2006 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31
32 #ifndef _MACH_I386__STRUCTS_H_
33 #define _MACH_I386__STRUCTS_H_
34
35 #include <sys/cdefs.h> /* __DARWIN_UNIX03 */
36 #include <machine/types.h> /* __uint8_t */
37
38 /*
39 * i386 is the structure that is exported to user threads for
40 * use in status/mutate calls. This structure should never change.
41 *
42 */
43
44 #if __DARWIN_UNIX03
45 #define _STRUCT_X86_THREAD_STATE32 struct __darwin_i386_thread_state
46 _STRUCT_X86_THREAD_STATE32
47 {
48 unsigned int __eax;
49 unsigned int __ebx;
50 unsigned int __ecx;
51 unsigned int __edx;
52 unsigned int __edi;
53 unsigned int __esi;
54 unsigned int __ebp;
55 unsigned int __esp;
56 unsigned int __ss;
57 unsigned int __eflags;
58 unsigned int __eip;
59 unsigned int __cs;
60 unsigned int __ds;
61 unsigned int __es;
62 unsigned int __fs;
63 unsigned int __gs;
64 };
65 #else /* !__DARWIN_UNIX03 */
66 #define _STRUCT_X86_THREAD_STATE32 struct i386_thread_state
67 _STRUCT_X86_THREAD_STATE32
68 {
69 unsigned int eax;
70 unsigned int ebx;
71 unsigned int ecx;
72 unsigned int edx;
73 unsigned int edi;
74 unsigned int esi;
75 unsigned int ebp;
76 unsigned int esp;
77 unsigned int ss;
78 unsigned int eflags;
79 unsigned int eip;
80 unsigned int cs;
81 unsigned int ds;
82 unsigned int es;
83 unsigned int fs;
84 unsigned int gs;
85 };
86 #endif /* !__DARWIN_UNIX03 */
87
88 /* This structure should be double-word aligned for performance */
89
90 #if __DARWIN_UNIX03
91 #define _STRUCT_FP_CONTROL struct __darwin_fp_control
92 _STRUCT_FP_CONTROL
93 {
94 unsigned short __invalid :1,
95 __denorm :1,
96 __zdiv :1,
97 __ovrfl :1,
98 __undfl :1,
99 __precis :1,
100 :2,
101 __pc :2,
102 #if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
103 #define FP_PREC_24B 0
104 #define FP_PREC_53B 2
105 #define FP_PREC_64B 3
106 #endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
107 __rc :2,
108 #if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
109 #define FP_RND_NEAR 0
110 #define FP_RND_DOWN 1
111 #define FP_RND_UP 2
112 #define FP_CHOP 3
113 #endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
114 /*inf*/ :1,
115 :3;
116 };
117 typedef _STRUCT_FP_CONTROL __darwin_fp_control_t;
118 #else /* !__DARWIN_UNIX03 */
119 #define _STRUCT_FP_CONTROL struct fp_control
120 _STRUCT_FP_CONTROL
121 {
122 unsigned short invalid :1,
123 denorm :1,
124 zdiv :1,
125 ovrfl :1,
126 undfl :1,
127 precis :1,
128 :2,
129 pc :2,
130 #define FP_PREC_24B 0
131 #define FP_PREC_53B 2
132 #define FP_PREC_64B 3
133 rc :2,
134 #define FP_RND_NEAR 0
135 #define FP_RND_DOWN 1
136 #define FP_RND_UP 2
137 #define FP_CHOP 3
138 /*inf*/ :1,
139 :3;
140 };
141 typedef _STRUCT_FP_CONTROL fp_control_t;
142 #endif /* !__DARWIN_UNIX03 */
143
144 /*
145 * Status word.
146 */
147
148 #if __DARWIN_UNIX03
149 #define _STRUCT_FP_STATUS struct __darwin_fp_status
150 _STRUCT_FP_STATUS
151 {
152 unsigned short __invalid :1,
153 __denorm :1,
154 __zdiv :1,
155 __ovrfl :1,
156 __undfl :1,
157 __precis :1,
158 __stkflt :1,
159 __errsumm :1,
160 __c0 :1,
161 __c1 :1,
162 __c2 :1,
163 __tos :3,
164 __c3 :1,
165 __busy :1;
166 };
167 typedef _STRUCT_FP_STATUS __darwin_fp_status_t;
168 #else /* !__DARWIN_UNIX03 */
169 #define _STRUCT_FP_STATUS struct fp_status
170 _STRUCT_FP_STATUS
171 {
172 unsigned short invalid :1,
173 denorm :1,
174 zdiv :1,
175 ovrfl :1,
176 undfl :1,
177 precis :1,
178 stkflt :1,
179 errsumm :1,
180 c0 :1,
181 c1 :1,
182 c2 :1,
183 tos :3,
184 c3 :1,
185 busy :1;
186 };
187 typedef _STRUCT_FP_STATUS fp_status_t;
188 #endif /* !__DARWIN_UNIX03 */
189
190 /* defn of 80bit x87 FPU or MMX register */
191
192 #if __DARWIN_UNIX03
193 #define _STRUCT_MMST_REG struct __darwin_mmst_reg
194 _STRUCT_MMST_REG
195 {
196 char __mmst_reg[10];
197 char __mmst_rsrv[6];
198 };
199 #else /* !__DARWIN_UNIX03 */
200 #define _STRUCT_MMST_REG struct mmst_reg
201 _STRUCT_MMST_REG
202 {
203 char mmst_reg[10];
204 char mmst_rsrv[6];
205 };
206 #endif /* !__DARWIN_UNIX03 */
207
208
209 /* defn of 128 bit XMM regs */
210
211 #if __DARWIN_UNIX03
212 #define _STRUCT_XMM_REG struct __darwin_xmm_reg
213 _STRUCT_XMM_REG
214 {
215 char __xmm_reg[16];
216 };
217 #else /* !__DARWIN_UNIX03 */
218 #define _STRUCT_XMM_REG struct xmm_reg
219 _STRUCT_XMM_REG
220 {
221 char xmm_reg[16];
222 };
223 #endif /* !__DARWIN_UNIX03 */
224
225 /* defn of 256 bit YMM regs */
226
227 #if __DARWIN_UNIX03
228 #define _STRUCT_YMM_REG struct __darwin_ymm_reg
229 _STRUCT_YMM_REG
230 {
231 char __ymm_reg[32];
232 };
233 #else /* !__DARWIN_UNIX03 */
234 #define _STRUCT_YMM_REG struct ymm_reg
235 _STRUCT_YMM_REG
236 {
237 char ymm_reg[32];
238 };
239 #endif /* !__DARWIN_UNIX03 */
240
241 /* defn of 512 bit ZMM regs */
242
243 #if __DARWIN_UNIX03
244 #define _STRUCT_ZMM_REG struct __darwin_zmm_reg
245 _STRUCT_ZMM_REG
246 {
247 char __zmm_reg[64];
248 };
249 #else /* !__DARWIN_UNIX03 */
250 #define _STRUCT_ZMM_REG struct zmm_reg
251 _STRUCT_ZMM_REG
252 {
253 char zmm_reg[64];
254 };
255 #endif /* !__DARWIN_UNIX03 */
256
257 #if __DARWIN_UNIX03
258 #define _STRUCT_OPMASK_REG struct __darwin_opmask_reg
259 _STRUCT_OPMASK_REG
260 {
261 char __opmask_reg[8];
262 };
263 #else /* !__DARWIN_UNIX03 */
264 #define _STRUCT_OPMASK_REG struct opmask_reg
265 _STRUCT_OPMASK_REG
266 {
267 char opmask_reg[8];
268 };
269 #endif /* !__DARWIN_UNIX03 */
270
271 /*
272 * Floating point state.
273 */
274
275 #if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
276 #define FP_STATE_BYTES 512 /* number of chars worth of data from fpu_fcw */
277 #endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
278
279 #if __DARWIN_UNIX03
280 #define _STRUCT_X86_FLOAT_STATE32 struct __darwin_i386_float_state
281 _STRUCT_X86_FLOAT_STATE32
282 {
283 int __fpu_reserved[2];
284 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
285 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
286 __uint8_t __fpu_ftw; /* x87 FPU tag word */
287 __uint8_t __fpu_rsrv1; /* reserved */
288 __uint16_t __fpu_fop; /* x87 FPU Opcode */
289 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
290 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
291 __uint16_t __fpu_rsrv2; /* reserved */
292 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
293 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
294 __uint16_t __fpu_rsrv3; /* reserved */
295 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
296 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
297 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
298 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
299 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
300 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
301 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
302 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
303 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
304 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
305 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
306 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
307 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
308 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
309 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
310 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
311 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
312 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
313 char __fpu_rsrv4[14*16]; /* reserved */
314 int __fpu_reserved1;
315 };
316
317 #define _STRUCT_X86_AVX_STATE32 struct __darwin_i386_avx_state
318 _STRUCT_X86_AVX_STATE32
319 {
320 int __fpu_reserved[2];
321 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
322 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
323 __uint8_t __fpu_ftw; /* x87 FPU tag word */
324 __uint8_t __fpu_rsrv1; /* reserved */
325 __uint16_t __fpu_fop; /* x87 FPU Opcode */
326 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
327 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
328 __uint16_t __fpu_rsrv2; /* reserved */
329 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
330 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
331 __uint16_t __fpu_rsrv3; /* reserved */
332 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
333 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
334 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
335 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
336 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
337 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
338 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
339 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
340 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
341 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
342 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
343 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
344 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
345 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
346 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
347 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
348 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
349 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
350 char __fpu_rsrv4[14*16]; /* reserved */
351 int __fpu_reserved1;
352 char __avx_reserved1[64];
353 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
354 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
355 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
356 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
357 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
358 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
359 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
360 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
361 };
362
363 #define _STRUCT_X86_AVX512_STATE32 struct __darwin_i386_avx512_state
364 _STRUCT_X86_AVX512_STATE32
365 {
366 int __fpu_reserved[2];
367 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
368 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
369 __uint8_t __fpu_ftw; /* x87 FPU tag word */
370 __uint8_t __fpu_rsrv1; /* reserved */
371 __uint16_t __fpu_fop; /* x87 FPU Opcode */
372 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
373 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
374 __uint16_t __fpu_rsrv2; /* reserved */
375 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
376 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
377 __uint16_t __fpu_rsrv3; /* reserved */
378 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
379 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
380 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
381 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
382 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
383 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
384 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
385 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
386 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
387 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
388 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
389 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
390 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
391 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
392 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
393 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
394 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
395 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
396 char __fpu_rsrv4[14*16]; /* reserved */
397 int __fpu_reserved1;
398 char __avx_reserved1[64];
399 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
400 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
401 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
402 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
403 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
404 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
405 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
406 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
407 _STRUCT_OPMASK_REG __fpu_k0; /* K0 */
408 _STRUCT_OPMASK_REG __fpu_k1; /* K1 */
409 _STRUCT_OPMASK_REG __fpu_k2; /* K2 */
410 _STRUCT_OPMASK_REG __fpu_k3; /* K3 */
411 _STRUCT_OPMASK_REG __fpu_k4; /* K4 */
412 _STRUCT_OPMASK_REG __fpu_k5; /* K5 */
413 _STRUCT_OPMASK_REG __fpu_k6; /* K6 */
414 _STRUCT_OPMASK_REG __fpu_k7; /* K7 */
415 _STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
416 _STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
417 _STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
418 _STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
419 _STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
420 _STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
421 _STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
422 _STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
423 };
424
425 #else /* !__DARWIN_UNIX03 */
426 #define _STRUCT_X86_FLOAT_STATE32 struct i386_float_state
427 _STRUCT_X86_FLOAT_STATE32
428 {
429 int fpu_reserved[2];
430 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
431 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
432 __uint8_t fpu_ftw; /* x87 FPU tag word */
433 __uint8_t fpu_rsrv1; /* reserved */
434 __uint16_t fpu_fop; /* x87 FPU Opcode */
435 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
436 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
437 __uint16_t fpu_rsrv2; /* reserved */
438 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
439 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
440 __uint16_t fpu_rsrv3; /* reserved */
441 __uint32_t fpu_mxcsr; /* MXCSR Register state */
442 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
443 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
444 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
445 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
446 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
447 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
448 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
449 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
450 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
451 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
452 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
453 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
454 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
455 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
456 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
457 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
458 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
459 char fpu_rsrv4[14*16]; /* reserved */
460 int fpu_reserved1;
461 };
462
463 #define _STRUCT_X86_AVX_STATE32 struct i386_avx_state
464 _STRUCT_X86_AVX_STATE32
465 {
466 int fpu_reserved[2];
467 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
468 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
469 __uint8_t fpu_ftw; /* x87 FPU tag word */
470 __uint8_t fpu_rsrv1; /* reserved */
471 __uint16_t fpu_fop; /* x87 FPU Opcode */
472 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
473 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
474 __uint16_t fpu_rsrv2; /* reserved */
475 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
476 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
477 __uint16_t fpu_rsrv3; /* reserved */
478 __uint32_t fpu_mxcsr; /* MXCSR Register state */
479 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
480 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
481 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
482 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
483 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
484 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
485 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
486 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
487 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
488 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
489 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
490 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
491 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
492 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
493 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
494 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
495 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
496 char fpu_rsrv4[14*16]; /* reserved */
497 int fpu_reserved1;
498 char avx_reserved1[64];
499 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
500 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
501 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
502 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
503 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
504 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
505 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
506 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
507 };
508
509 #define _STRUCT_X86_AVX512_STATE32 struct i386_avx512_state
510 _STRUCT_X86_AVX512_STATE32
511 {
512 int fpu_reserved[2];
513 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
514 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
515 __uint8_t fpu_ftw; /* x87 FPU tag word */
516 __uint8_t fpu_rsrv1; /* reserved */
517 __uint16_t fpu_fop; /* x87 FPU Opcode */
518 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
519 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
520 __uint16_t fpu_rsrv2; /* reserved */
521 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
522 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
523 __uint16_t fpu_rsrv3; /* reserved */
524 __uint32_t fpu_mxcsr; /* MXCSR Register state */
525 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
526 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
527 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
528 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
529 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
530 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
531 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
532 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
533 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
534 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
535 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
536 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
537 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
538 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
539 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
540 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
541 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
542 char fpu_rsrv4[14*16]; /* reserved */
543 int fpu_reserved1;
544 char avx_reserved1[64];
545 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
546 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
547 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
548 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
549 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
550 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
551 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
552 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
553 _STRUCT_OPMASK_REG fpu_k0; /* K0 */
554 _STRUCT_OPMASK_REG fpu_k1; /* K1 */
555 _STRUCT_OPMASK_REG fpu_k2; /* K2 */
556 _STRUCT_OPMASK_REG fpu_k3; /* K3 */
557 _STRUCT_OPMASK_REG fpu_k4; /* K4 */
558 _STRUCT_OPMASK_REG fpu_k5; /* K5 */
559 _STRUCT_OPMASK_REG fpu_k6; /* K6 */
560 _STRUCT_OPMASK_REG fpu_k7; /* K7 */
561 _STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
562 _STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
563 _STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
564 _STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
565 _STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
566 _STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
567 _STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
568 _STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
569 };
570
571 #endif /* !__DARWIN_UNIX03 */
572
573 #if __DARWIN_UNIX03
574 #define _STRUCT_X86_EXCEPTION_STATE32 struct __darwin_i386_exception_state
575 _STRUCT_X86_EXCEPTION_STATE32
576 {
577 __uint16_t __trapno;
578 __uint16_t __cpu;
579 __uint32_t __err;
580 __uint32_t __faultvaddr;
581 };
582 #else /* !__DARWIN_UNIX03 */
583 #define _STRUCT_X86_EXCEPTION_STATE32 struct i386_exception_state
584 _STRUCT_X86_EXCEPTION_STATE32
585 {
586 __uint16_t trapno;
587 __uint16_t cpu;
588 __uint32_t err;
589 __uint32_t faultvaddr;
590 };
591 #endif /* !__DARWIN_UNIX03 */
592
593 #if __DARWIN_UNIX03
594 #define _STRUCT_X86_DEBUG_STATE32 struct __darwin_x86_debug_state32
595 _STRUCT_X86_DEBUG_STATE32
596 {
597 unsigned int __dr0;
598 unsigned int __dr1;
599 unsigned int __dr2;
600 unsigned int __dr3;
601 unsigned int __dr4;
602 unsigned int __dr5;
603 unsigned int __dr6;
604 unsigned int __dr7;
605 };
606
607 #define _STRUCT_X86_INSTRUCTION_STATE struct __x86_instruction_state
608 _STRUCT_X86_INSTRUCTION_STATE
609 {
610 int __insn_stream_valid_bytes;
611 int __insn_offset;
612 int __out_of_synch; /*
613 * non-zero when the cacheline that includes the insn_offset
614 * is replaced in the insn_bytes array due to a mismatch
615 * detected when comparing it with the same cacheline in memory
616 */
617 #define _X86_INSTRUCTION_STATE_MAX_INSN_BYTES (2448 - 64 - 4)
618 __uint8_t __insn_bytes[_X86_INSTRUCTION_STATE_MAX_INSN_BYTES];
619 #define _X86_INSTRUCTION_STATE_CACHELINE_SIZE 64
620 __uint8_t __insn_cacheline[_X86_INSTRUCTION_STATE_CACHELINE_SIZE];
621 };
622
623 #define _STRUCT_LAST_BRANCH_RECORD struct __last_branch_record
624 _STRUCT_LAST_BRANCH_RECORD
625 {
626 __uint64_t __from_ip;
627 __uint64_t __to_ip;
628 __uint32_t __mispredict : 1,
629 __tsx_abort : 1,
630 __in_tsx : 1,
631 __cycle_count: 16,
632 __reserved : 13;
633 };
634
635 #define _STRUCT_LAST_BRANCH_STATE struct __last_branch_state
636 _STRUCT_LAST_BRANCH_STATE
637 {
638 int __lbr_count;
639 __uint32_t __lbr_supported_tsx : 1,
640 __lbr_supported_cycle_count : 1,
641 __reserved : 30;
642 #define __LASTBRANCH_MAX 32
643 _STRUCT_LAST_BRANCH_RECORD __lbrs[__LASTBRANCH_MAX];
644 };
645
646 #else /* !__DARWIN_UNIX03 */
647
648 #define _STRUCT_X86_DEBUG_STATE32 struct x86_debug_state32
649 _STRUCT_X86_DEBUG_STATE32
650 {
651 unsigned int dr0;
652 unsigned int dr1;
653 unsigned int dr2;
654 unsigned int dr3;
655 unsigned int dr4;
656 unsigned int dr5;
657 unsigned int dr6;
658 unsigned int dr7;
659 };
660
661 #define _STRUCT_X86_INSTRUCTION_STATE struct __x86_instruction_state
662 _STRUCT_X86_INSTRUCTION_STATE
663 {
664 int insn_stream_valid_bytes;
665 int insn_offset;
666 int out_of_synch; /*
667 * non-zero when the cacheline that includes the insn_offset
668 * is replaced in the insn_bytes array due to a mismatch
669 * detected when comparing it with the same cacheline in memory
670 */
671 #define x86_INSTRUCTION_STATE_MAX_INSN_BYTES (2448 - 64 - 4)
672 __uint8_t insn_bytes[x86_INSTRUCTION_STATE_MAX_INSN_BYTES];
673 #define x86_INSTRUCTION_STATE_CACHELINE_SIZE 64
674 __uint8_t insn_cacheline[x86_INSTRUCTION_STATE_CACHELINE_SIZE];
675 };
676
677 #define _STRUCT_LAST_BRANCH_RECORD struct __last_branch_record
678 _STRUCT_LAST_BRANCH_RECORD
679 {
680 __uint64_t from_ip;
681 __uint64_t to_ip;
682 __uint32_t mispredict : 1,
683 tsx_abort : 1,
684 in_tsx : 1,
685 cycle_count: 16,
686 reserved : 13;
687 };
688
689 #define _STRUCT_LAST_BRANCH_STATE struct __last_branch_state
690 _STRUCT_LAST_BRANCH_STATE
691 {
692 int lbr_count;
693 __uint32_t lbr_supported_tsx : 1,
694 lbr_supported_cycle_count : 1,
695 reserved : 30;
696 #define __LASTBRANCH_MAX 32
697 _STRUCT_LAST_BRANCH_RECORD lbrs[__LASTBRANCH_MAX];
698 };
699 #endif /* !__DARWIN_UNIX03 */
700
701 #define _STRUCT_X86_PAGEIN_STATE struct __x86_pagein_state
702 _STRUCT_X86_PAGEIN_STATE
703 {
704 int __pagein_error;
705 };
706
707 /*
708 * 64 bit versions of the above
709 */
710
711 #if __DARWIN_UNIX03
712 #define _STRUCT_X86_THREAD_STATE64 struct __darwin_x86_thread_state64
713 _STRUCT_X86_THREAD_STATE64
714 {
715 __uint64_t __rax;
716 __uint64_t __rbx;
717 __uint64_t __rcx;
718 __uint64_t __rdx;
719 __uint64_t __rdi;
720 __uint64_t __rsi;
721 __uint64_t __rbp;
722 __uint64_t __rsp;
723 __uint64_t __r8;
724 __uint64_t __r9;
725 __uint64_t __r10;
726 __uint64_t __r11;
727 __uint64_t __r12;
728 __uint64_t __r13;
729 __uint64_t __r14;
730 __uint64_t __r15;
731 __uint64_t __rip;
732 __uint64_t __rflags;
733 __uint64_t __cs;
734 __uint64_t __fs;
735 __uint64_t __gs;
736 };
737 #else /* !__DARWIN_UNIX03 */
738 #define _STRUCT_X86_THREAD_STATE64 struct x86_thread_state64
739 _STRUCT_X86_THREAD_STATE64
740 {
741 __uint64_t rax;
742 __uint64_t rbx;
743 __uint64_t rcx;
744 __uint64_t rdx;
745 __uint64_t rdi;
746 __uint64_t rsi;
747 __uint64_t rbp;
748 __uint64_t rsp;
749 __uint64_t r8;
750 __uint64_t r9;
751 __uint64_t r10;
752 __uint64_t r11;
753 __uint64_t r12;
754 __uint64_t r13;
755 __uint64_t r14;
756 __uint64_t r15;
757 __uint64_t rip;
758 __uint64_t rflags;
759 __uint64_t cs;
760 __uint64_t fs;
761 __uint64_t gs;
762 };
763 #endif /* !__DARWIN_UNIX03 */
764
765 /*
766 * 64 bit versions of the above (complete)
767 */
768
769 #if __DARWIN_UNIX03
770 #define _STRUCT_X86_THREAD_FULL_STATE64 struct __darwin_x86_thread_full_state64
771 _STRUCT_X86_THREAD_FULL_STATE64
772 {
773 _STRUCT_X86_THREAD_STATE64 __ss64;
774 __uint64_t __ds;
775 __uint64_t __es;
776 __uint64_t __ss;
777 __uint64_t __gsbase;
778 };
779 #else /* !__DARWIN_UNIX03 */
780 #define _STRUCT_X86_THREAD_FULL_STATE64 struct x86_thread_full_state64
781 _STRUCT_X86_THREAD_FULL_STATE64
782 {
783 _STRUCT_X86_THREAD_STATE64 ss64;
784 __uint64_t ds;
785 __uint64_t es;
786 __uint64_t ss;
787 __uint64_t gsbase;
788 };
789 #endif /* !__DARWIN_UNIX03 */
790
791
792 #if __DARWIN_UNIX03
793 #define _STRUCT_X86_FLOAT_STATE64 struct __darwin_x86_float_state64
794 _STRUCT_X86_FLOAT_STATE64
795 {
796 int __fpu_reserved[2];
797 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
798 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
799 __uint8_t __fpu_ftw; /* x87 FPU tag word */
800 __uint8_t __fpu_rsrv1; /* reserved */
801 __uint16_t __fpu_fop; /* x87 FPU Opcode */
802
803 /* x87 FPU Instruction Pointer */
804 __uint32_t __fpu_ip; /* offset */
805 __uint16_t __fpu_cs; /* Selector */
806
807 __uint16_t __fpu_rsrv2; /* reserved */
808
809 /* x87 FPU Instruction Operand(Data) Pointer */
810 __uint32_t __fpu_dp; /* offset */
811 __uint16_t __fpu_ds; /* Selector */
812
813 __uint16_t __fpu_rsrv3; /* reserved */
814 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
815 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
816 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
817 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
818 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
819 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
820 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
821 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
822 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
823 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
824 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
825 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
826 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
827 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
828 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
829 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
830 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
831 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
832 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
833 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
834 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
835 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
836 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
837 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
838 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
839 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
840 char __fpu_rsrv4[6*16]; /* reserved */
841 int __fpu_reserved1;
842 };
843
844 #define _STRUCT_X86_AVX_STATE64 struct __darwin_x86_avx_state64
845 _STRUCT_X86_AVX_STATE64
846 {
847 int __fpu_reserved[2];
848 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
849 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
850 __uint8_t __fpu_ftw; /* x87 FPU tag word */
851 __uint8_t __fpu_rsrv1; /* reserved */
852 __uint16_t __fpu_fop; /* x87 FPU Opcode */
853
854 /* x87 FPU Instruction Pointer */
855 __uint32_t __fpu_ip; /* offset */
856 __uint16_t __fpu_cs; /* Selector */
857
858 __uint16_t __fpu_rsrv2; /* reserved */
859
860 /* x87 FPU Instruction Operand(Data) Pointer */
861 __uint32_t __fpu_dp; /* offset */
862 __uint16_t __fpu_ds; /* Selector */
863
864 __uint16_t __fpu_rsrv3; /* reserved */
865 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
866 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
867 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
868 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
869 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
870 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
871 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
872 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
873 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
874 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
875 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
876 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
877 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
878 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
879 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
880 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
881 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
882 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
883 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
884 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
885 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
886 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
887 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
888 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
889 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
890 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
891 char __fpu_rsrv4[6*16]; /* reserved */
892 int __fpu_reserved1;
893 char __avx_reserved1[64];
894 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
895 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
896 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
897 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
898 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
899 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
900 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
901 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
902 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
903 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
904 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
905 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
906 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
907 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
908 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
909 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
910 };
911
912 #define _STRUCT_X86_AVX512_STATE64 struct __darwin_x86_avx512_state64
913 _STRUCT_X86_AVX512_STATE64
914 {
915 int __fpu_reserved[2];
916 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
917 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
918 __uint8_t __fpu_ftw; /* x87 FPU tag word */
919 __uint8_t __fpu_rsrv1; /* reserved */
920 __uint16_t __fpu_fop; /* x87 FPU Opcode */
921
922 /* x87 FPU Instruction Pointer */
923 __uint32_t __fpu_ip; /* offset */
924 __uint16_t __fpu_cs; /* Selector */
925
926 __uint16_t __fpu_rsrv2; /* reserved */
927
928 /* x87 FPU Instruction Operand(Data) Pointer */
929 __uint32_t __fpu_dp; /* offset */
930 __uint16_t __fpu_ds; /* Selector */
931
932 __uint16_t __fpu_rsrv3; /* reserved */
933 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
934 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
935 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
936 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
937 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
938 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
939 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
940 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
941 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
942 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
943 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
944 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
945 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
946 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
947 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
948 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
949 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
950 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
951 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
952 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
953 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
954 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
955 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
956 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
957 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
958 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
959 char __fpu_rsrv4[6*16]; /* reserved */
960 int __fpu_reserved1;
961 char __avx_reserved1[64];
962 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
963 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
964 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
965 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
966 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
967 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
968 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
969 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
970 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
971 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
972 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
973 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
974 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
975 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
976 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
977 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
978 _STRUCT_OPMASK_REG __fpu_k0; /* K0 */
979 _STRUCT_OPMASK_REG __fpu_k1; /* K1 */
980 _STRUCT_OPMASK_REG __fpu_k2; /* K2 */
981 _STRUCT_OPMASK_REG __fpu_k3; /* K3 */
982 _STRUCT_OPMASK_REG __fpu_k4; /* K4 */
983 _STRUCT_OPMASK_REG __fpu_k5; /* K5 */
984 _STRUCT_OPMASK_REG __fpu_k6; /* K6 */
985 _STRUCT_OPMASK_REG __fpu_k7; /* K7 */
986 _STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
987 _STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
988 _STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
989 _STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
990 _STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
991 _STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
992 _STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
993 _STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
994 _STRUCT_YMM_REG __fpu_zmmh8; /* ZMMH 8 */
995 _STRUCT_YMM_REG __fpu_zmmh9; /* ZMMH 9 */
996 _STRUCT_YMM_REG __fpu_zmmh10; /* ZMMH 10 */
997 _STRUCT_YMM_REG __fpu_zmmh11; /* ZMMH 11 */
998 _STRUCT_YMM_REG __fpu_zmmh12; /* ZMMH 12 */
999 _STRUCT_YMM_REG __fpu_zmmh13; /* ZMMH 13 */
1000 _STRUCT_YMM_REG __fpu_zmmh14; /* ZMMH 14 */
1001 _STRUCT_YMM_REG __fpu_zmmh15; /* ZMMH 15 */
1002 _STRUCT_ZMM_REG __fpu_zmm16; /* ZMM 16 */
1003 _STRUCT_ZMM_REG __fpu_zmm17; /* ZMM 17 */
1004 _STRUCT_ZMM_REG __fpu_zmm18; /* ZMM 18 */
1005 _STRUCT_ZMM_REG __fpu_zmm19; /* ZMM 19 */
1006 _STRUCT_ZMM_REG __fpu_zmm20; /* ZMM 20 */
1007 _STRUCT_ZMM_REG __fpu_zmm21; /* ZMM 21 */
1008 _STRUCT_ZMM_REG __fpu_zmm22; /* ZMM 22 */
1009 _STRUCT_ZMM_REG __fpu_zmm23; /* ZMM 23 */
1010 _STRUCT_ZMM_REG __fpu_zmm24; /* ZMM 24 */
1011 _STRUCT_ZMM_REG __fpu_zmm25; /* ZMM 25 */
1012 _STRUCT_ZMM_REG __fpu_zmm26; /* ZMM 26 */
1013 _STRUCT_ZMM_REG __fpu_zmm27; /* ZMM 27 */
1014 _STRUCT_ZMM_REG __fpu_zmm28; /* ZMM 28 */
1015 _STRUCT_ZMM_REG __fpu_zmm29; /* ZMM 29 */
1016 _STRUCT_ZMM_REG __fpu_zmm30; /* ZMM 30 */
1017 _STRUCT_ZMM_REG __fpu_zmm31; /* ZMM 31 */
1018 };
1019
1020 #else /* !__DARWIN_UNIX03 */
1021 #define _STRUCT_X86_FLOAT_STATE64 struct x86_float_state64
1022 _STRUCT_X86_FLOAT_STATE64
1023 {
1024 int fpu_reserved[2];
1025 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1026 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1027 __uint8_t fpu_ftw; /* x87 FPU tag word */
1028 __uint8_t fpu_rsrv1; /* reserved */
1029 __uint16_t fpu_fop; /* x87 FPU Opcode */
1030
1031 /* x87 FPU Instruction Pointer */
1032 __uint32_t fpu_ip; /* offset */
1033 __uint16_t fpu_cs; /* Selector */
1034
1035 __uint16_t fpu_rsrv2; /* reserved */
1036
1037 /* x87 FPU Instruction Operand(Data) Pointer */
1038 __uint32_t fpu_dp; /* offset */
1039 __uint16_t fpu_ds; /* Selector */
1040
1041 __uint16_t fpu_rsrv3; /* reserved */
1042 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1043 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1044 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1045 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1046 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1047 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1048 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1049 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1050 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1051 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1052 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1053 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1054 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1055 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1056 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1057 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1058 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1059 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1060 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1061 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1062 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1063 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1064 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1065 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1066 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1067 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1068 char fpu_rsrv4[6*16]; /* reserved */
1069 int fpu_reserved1;
1070 };
1071
1072 #define _STRUCT_X86_AVX_STATE64 struct x86_avx_state64
1073 _STRUCT_X86_AVX_STATE64
1074 {
1075 int fpu_reserved[2];
1076 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1077 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1078 __uint8_t fpu_ftw; /* x87 FPU tag word */
1079 __uint8_t fpu_rsrv1; /* reserved */
1080 __uint16_t fpu_fop; /* x87 FPU Opcode */
1081
1082 /* x87 FPU Instruction Pointer */
1083 __uint32_t fpu_ip; /* offset */
1084 __uint16_t fpu_cs; /* Selector */
1085
1086 __uint16_t fpu_rsrv2; /* reserved */
1087
1088 /* x87 FPU Instruction Operand(Data) Pointer */
1089 __uint32_t fpu_dp; /* offset */
1090 __uint16_t fpu_ds; /* Selector */
1091
1092 __uint16_t fpu_rsrv3; /* reserved */
1093 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1094 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1095 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1096 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1097 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1098 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1099 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1100 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1101 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1102 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1103 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1104 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1105 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1106 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1107 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1108 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1109 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1110 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1111 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1112 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1113 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1114 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1115 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1116 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1117 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1118 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1119 char fpu_rsrv4[6*16]; /* reserved */
1120 int fpu_reserved1;
1121 char avx_reserved1[64];
1122 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
1123 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
1124 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
1125 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
1126 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
1127 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
1128 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
1129 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
1130 _STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
1131 _STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
1132 _STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
1133 _STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
1134 _STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
1135 _STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
1136 _STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
1137 _STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
1138 };
1139
1140 #define _STRUCT_X86_AVX512_STATE64 struct x86_avx512_state64
1141 _STRUCT_X86_AVX512_STATE64
1142 {
1143 int fpu_reserved[2];
1144 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1145 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1146 __uint8_t fpu_ftw; /* x87 FPU tag word */
1147 __uint8_t fpu_rsrv1; /* reserved */
1148 __uint16_t fpu_fop; /* x87 FPU Opcode */
1149
1150 /* x87 FPU Instruction Pointer */
1151 __uint32_t fpu_ip; /* offset */
1152 __uint16_t fpu_cs; /* Selector */
1153
1154 __uint16_t fpu_rsrv2; /* reserved */
1155
1156 /* x87 FPU Instruction Operand(Data) Pointer */
1157 __uint32_t fpu_dp; /* offset */
1158 __uint16_t fpu_ds; /* Selector */
1159
1160 __uint16_t fpu_rsrv3; /* reserved */
1161 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1162 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1163 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1164 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1165 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1166 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1167 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1168 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1169 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1170 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1171 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1172 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1173 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1174 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1175 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1176 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1177 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1178 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1179 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1180 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1181 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1182 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1183 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1184 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1185 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1186 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1187 char fpu_rsrv4[6*16]; /* reserved */
1188 int fpu_reserved1;
1189 char avx_reserved1[64];
1190 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
1191 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
1192 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
1193 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
1194 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
1195 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
1196 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
1197 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
1198 _STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
1199 _STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
1200 _STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
1201 _STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
1202 _STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
1203 _STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
1204 _STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
1205 _STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
1206 _STRUCT_OPMASK_REG fpu_k0; /* K0 */
1207 _STRUCT_OPMASK_REG fpu_k1; /* K1 */
1208 _STRUCT_OPMASK_REG fpu_k2; /* K2 */
1209 _STRUCT_OPMASK_REG fpu_k3; /* K3 */
1210 _STRUCT_OPMASK_REG fpu_k4; /* K4 */
1211 _STRUCT_OPMASK_REG fpu_k5; /* K5 */
1212 _STRUCT_OPMASK_REG fpu_k6; /* K6 */
1213 _STRUCT_OPMASK_REG fpu_k7; /* K7 */
1214 _STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
1215 _STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
1216 _STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
1217 _STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
1218 _STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
1219 _STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
1220 _STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
1221 _STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
1222 _STRUCT_YMM_REG fpu_zmmh8; /* ZMMH 8 */
1223 _STRUCT_YMM_REG fpu_zmmh9; /* ZMMH 9 */
1224 _STRUCT_YMM_REG fpu_zmmh10; /* ZMMH 10 */
1225 _STRUCT_YMM_REG fpu_zmmh11; /* ZMMH 11 */
1226 _STRUCT_YMM_REG fpu_zmmh12; /* ZMMH 12 */
1227 _STRUCT_YMM_REG fpu_zmmh13; /* ZMMH 13 */
1228 _STRUCT_YMM_REG fpu_zmmh14; /* ZMMH 14 */
1229 _STRUCT_YMM_REG fpu_zmmh15; /* ZMMH 15 */
1230 _STRUCT_ZMM_REG fpu_zmm16; /* ZMM 16 */
1231 _STRUCT_ZMM_REG fpu_zmm17; /* ZMM 17 */
1232 _STRUCT_ZMM_REG fpu_zmm18; /* ZMM 18 */
1233 _STRUCT_ZMM_REG fpu_zmm19; /* ZMM 19 */
1234 _STRUCT_ZMM_REG fpu_zmm20; /* ZMM 20 */
1235 _STRUCT_ZMM_REG fpu_zmm21; /* ZMM 21 */
1236 _STRUCT_ZMM_REG fpu_zmm22; /* ZMM 22 */
1237 _STRUCT_ZMM_REG fpu_zmm23; /* ZMM 23 */
1238 _STRUCT_ZMM_REG fpu_zmm24; /* ZMM 24 */
1239 _STRUCT_ZMM_REG fpu_zmm25; /* ZMM 25 */
1240 _STRUCT_ZMM_REG fpu_zmm26; /* ZMM 26 */
1241 _STRUCT_ZMM_REG fpu_zmm27; /* ZMM 27 */
1242 _STRUCT_ZMM_REG fpu_zmm28; /* ZMM 28 */
1243 _STRUCT_ZMM_REG fpu_zmm29; /* ZMM 29 */
1244 _STRUCT_ZMM_REG fpu_zmm30; /* ZMM 30 */
1245 _STRUCT_ZMM_REG fpu_zmm31; /* ZMM 31 */
1246 };
1247
1248 #endif /* !__DARWIN_UNIX03 */
1249
1250 #if __DARWIN_UNIX03
1251 #define _STRUCT_X86_EXCEPTION_STATE64 struct __darwin_x86_exception_state64
1252 _STRUCT_X86_EXCEPTION_STATE64
1253 {
1254 __uint16_t __trapno;
1255 __uint16_t __cpu;
1256 __uint32_t __err;
1257 __uint64_t __faultvaddr;
1258 };
1259 #else /* !__DARWIN_UNIX03 */
1260 #define _STRUCT_X86_EXCEPTION_STATE64 struct x86_exception_state64
1261 _STRUCT_X86_EXCEPTION_STATE64
1262 {
1263 __uint16_t trapno;
1264 __uint16_t cpu;
1265 __uint32_t err;
1266 __uint64_t faultvaddr;
1267 };
1268 #endif /* !__DARWIN_UNIX03 */
1269
1270 #if __DARWIN_UNIX03
1271 #define _STRUCT_X86_DEBUG_STATE64 struct __darwin_x86_debug_state64
1272 _STRUCT_X86_DEBUG_STATE64
1273 {
1274 __uint64_t __dr0;
1275 __uint64_t __dr1;
1276 __uint64_t __dr2;
1277 __uint64_t __dr3;
1278 __uint64_t __dr4;
1279 __uint64_t __dr5;
1280 __uint64_t __dr6;
1281 __uint64_t __dr7;
1282 };
1283 #else /* !__DARWIN_UNIX03 */
1284 #define _STRUCT_X86_DEBUG_STATE64 struct x86_debug_state64
1285 _STRUCT_X86_DEBUG_STATE64
1286 {
1287 __uint64_t dr0;
1288 __uint64_t dr1;
1289 __uint64_t dr2;
1290 __uint64_t dr3;
1291 __uint64_t dr4;
1292 __uint64_t dr5;
1293 __uint64_t dr6;
1294 __uint64_t dr7;
1295 };
1296 #endif /* !__DARWIN_UNIX03 */
1297
1298 #if __DARWIN_UNIX03
1299 #define _STRUCT_X86_CPMU_STATE64 struct __darwin_x86_cpmu_state64
1300 _STRUCT_X86_CPMU_STATE64
1301 {
1302 __uint64_t __ctrs[16];
1303 };
1304 #else /* __DARWIN_UNIX03 */
1305 #define _STRUCT_X86_CPMU_STATE64 struct x86_cpmu_state64
1306 _STRUCT_X86_CPMU_STATE64
1307 {
1308 __uint64_t ctrs[16];
1309 };
1310 #endif /* !__DARWIN_UNIX03 */
1311
1312 #endif /* _MACH_I386__STRUCTS_H_ */
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