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24 #include <sys/appleapiopts.h>
25 #include <ppc/asm.h> // EXT, LEXT
26 #include <machine/cpu_capabilities.h>
27 #include <machine/commpage.h>
33 // *********************************************
34 // * C O M M P A G E _ F L U S H _ D C A C H E *
35 // *********************************************
37 // Note that this routine is called both in 32 and 64-bit mode.
39 // r3 = ptr to 1st byte to flush
40 // r4 = length to flush (may be 0)
42 commpage_flush_dcache:
43 mr. r4,r4 // test length for 0 in mode-independent way
44 lhz r5,_COMM_PAGE_CACHE_LINESIZE(0)
45 subi r9,r5,1 // get (linesize-1)
46 and r0,r3,r9 // get offset within line of 1st byte
47 add r4,r4,r0 // adjust length so we flush them all
48 add r4,r4,r9 // round length up...
49 andc r4,r4,r9 // ...to multiple of cache lines
50 beqlr-- // length was 0, so exit
52 sub. r4,r4,r5 // more to go?
53 dcbf 0,r3 // flush another line
56 sync // make sure lines are flushed before we return
59 COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,kCommPageBoth)
62 // *********************************************
63 // * C O M M P A G E _ F L U S H _ I C A C H E *
64 // *********************************************
66 // Note that this routine is called both in 32 and 64-bit mode.
68 // r3 = ptr to 1st byte to flush
69 // r4 = length to flush (may be 0)
71 commpage_flush_icache:
72 mr. r4,r4 // test length for 0 in mode-independent way
73 lhz r5,_COMM_PAGE_CACHE_LINESIZE(0)
74 subi r9,r5,1 // get (linesize-1)
75 and r0,r3,r9 // get offset within line of 1st byte
76 add r4,r4,r0 // adjust length so we flush them all
78 add r4,r4,r9 // round length up...
79 andc r4,r4,r9 // ...to multiple of cache lines
80 mr r6,r4 // copy length
81 beqlr-- // length was 0, so exit
83 sub. r4,r4,r5 // more to go?
84 dcbf 0,r3 // flush another line
87 sync // make sure lines are flushed
89 sub. r6,r6,r5 // more to go?
94 // The following sync is only needed on MP machines, probably only on
95 // 7400-family MP machines. But because we're not certain of this, and
96 // this isn't a speed critical routine, we are conservative and always sync.
98 sync // wait until other processors see the icbi's
99 isync // make sure we haven't prefetched old instructions
103 COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,kCommPageBoth)