]> git.saurik.com Git - apple/xnu.git/blob - osfmk/ppc/commpage/cacheflush.s
xnu-792.10.96.tar.gz
[apple/xnu.git] / osfmk / ppc / commpage / cacheflush.s
1 /*
2 * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22
23 #define ASSEMBLER
24 #include <sys/appleapiopts.h>
25 #include <ppc/asm.h> // EXT, LEXT
26 #include <machine/cpu_capabilities.h>
27 #include <machine/commpage.h>
28
29 .text
30 .align 2
31
32
33 // *********************************************
34 // * C O M M P A G E _ F L U S H _ D C A C H E *
35 // *********************************************
36 //
37 // Note that this routine is called both in 32 and 64-bit mode.
38 //
39 // r3 = ptr to 1st byte to flush
40 // r4 = length to flush (may be 0)
41
42 commpage_flush_dcache:
43 mr. r4,r4 // test length for 0 in mode-independent way
44 lhz r5,_COMM_PAGE_CACHE_LINESIZE(0)
45 subi r9,r5,1 // get (linesize-1)
46 and r0,r3,r9 // get offset within line of 1st byte
47 add r4,r4,r0 // adjust length so we flush them all
48 add r4,r4,r9 // round length up...
49 andc r4,r4,r9 // ...to multiple of cache lines
50 beqlr-- // length was 0, so exit
51 1:
52 sub. r4,r4,r5 // more to go?
53 dcbf 0,r3 // flush another line
54 add r3,r3,r5
55 bne 1b
56 sync // make sure lines are flushed before we return
57 blr
58
59 COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,kCommPageBoth)
60
61
62 // *********************************************
63 // * C O M M P A G E _ F L U S H _ I C A C H E *
64 // *********************************************
65 //
66 // Note that this routine is called both in 32 and 64-bit mode.
67 //
68 // r3 = ptr to 1st byte to flush
69 // r4 = length to flush (may be 0)
70
71 commpage_flush_icache:
72 mr. r4,r4 // test length for 0 in mode-independent way
73 lhz r5,_COMM_PAGE_CACHE_LINESIZE(0)
74 subi r9,r5,1 // get (linesize-1)
75 and r0,r3,r9 // get offset within line of 1st byte
76 add r4,r4,r0 // adjust length so we flush them all
77 mr r7,r3 // copy ptr
78 add r4,r4,r9 // round length up...
79 andc r4,r4,r9 // ...to multiple of cache lines
80 mr r6,r4 // copy length
81 beqlr-- // length was 0, so exit
82 1:
83 sub. r4,r4,r5 // more to go?
84 dcbf 0,r3 // flush another line
85 add r3,r3,r5
86 bne 1b
87 sync // make sure lines are flushed
88 2:
89 sub. r6,r6,r5 // more to go?
90 icbi 0,r7
91 add r7,r7,r5
92 bne 2b
93
94 // The following sync is only needed on MP machines, probably only on
95 // 7400-family MP machines. But because we're not certain of this, and
96 // this isn't a speed critical routine, we are conservative and always sync.
97
98 sync // wait until other processors see the icbi's
99 isync // make sure we haven't prefetched old instructions
100
101 blr
102
103 COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,kCommPageBoth)
104
105