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24 #include <sys/appleapiopts.h>
26 #include <machine/cpu_capabilities.h>
27 #include <machine/commpage.h>
33 // *******************
34 // * B Z E R O _ 3 2 *
35 // *******************
37 // For 32-bit processors with a 32-byte cache line.
41 // r3 = original ptr, not changed since memset returns it
42 // r4 = count of bytes to set
43 // r9 = working operand ptr
44 // We do not touch r2 and r10-r12, which some callers depend on.
47 bzero_32: // void bzero(void *b, size_t len);
48 cmplwi cr7,r4,32 // too short for DCBZ?
50 neg r5,r3 // start to compute #bytes to align
51 mr r9,r3 // make copy of operand ptr (can't change r3)
52 blt cr7,Ltail // length < 32, too short for DCBZ
54 // At least 32 bytes long, so compute alignment and #cache blocks.
56 andi. r5,r5,0x1F // r5 <- #bytes to 32-byte align
57 sub r4,r4,r5 // adjust length
58 srwi r8,r4,5 // r8 <- #32-byte chunks
59 cmpwi cr1,r8,0 // any chunks?
60 mtctr r8 // set up loop count
61 beq 1f // skip if already 32-byte aligned (r8!=0)
63 // 32-byte align. We just store 32 0s, rather than test and use conditional
64 // branches. We've already stored the first few bytes above.
74 add r9,r9,r5 // now rp is 32-byte aligned
75 beq cr1,Ltail // skip if no 32-byte chunks
77 // Loop doing 32-byte version of DCBZ instruction.
78 // NB: we take alignment exceptions on cache-inhibited memory.
79 // The kernel could be changed to zero cr7 when emulating a
80 // dcbz (as it does on 64-bit processors), so we could avoid all
84 andi. r5,r4,0x1F // will there be trailing bytes?
88 dcbz 0,r9 // zero another 32 bytes
92 beqlr // no trailing bytes
94 // Store trailing bytes.
97 andi. r5,r4,0x10 // test bit 27 separately
98 mtcrf 0x01,r4 // remaining byte count to cr7
100 beq 2f // no 16-byte chunks
107 bf 28,4f // 8-byte chunk?
116 bf 30,6f // halfword?
124 COMMPAGE_DESCRIPTOR(bzero_32,_COMM_PAGE_BZERO,kCache32,0,kCommPage32)