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1 /*
2 * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_COPYRIGHT@
24 */
25 /*
26 * Mach Operating System
27 * Copyright (c) 1991,1990 Carnegie Mellon University
28 * All Rights Reserved.
29 *
30 * Permission to use, copy, modify and distribute this software and its
31 * documentation is hereby granted, provided that both the copyright
32 * notice and this permission notice appear in all copies of the
33 * software, derivative works or modified versions, and any portions
34 * thereof, and that both notices appear in supporting documentation.
35 *
36 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
37 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
38 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
39 *
40 * Carnegie Mellon requests users of this software to return to
41 *
42 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
43 * School of Computer Science
44 * Carnegie Mellon University
45 * Pittsburgh PA 15213-3890
46 *
47 * any improvements or extensions that they make and grant Carnegie Mellon
48 * the rights to redistribute these changes.
49 */
50
51 /*
52 */
53 #ifdef KERNEL_PRIVATE
54
55 #ifndef _I386AT_MP_H_
56 #define _I386AT_MP_H_
57
58 #ifndef DEBUG
59 #include <debug.h>
60 #endif
61 //#define MP_DEBUG 1
62
63 #include <i386/apic.h>
64 #include <i386/mp_events.h>
65
66 #define LAPIC_ID_MAX (LAPIC_ID_MASK)
67
68 #define MAX_CPUS (LAPIC_ID_MAX + 1)
69
70 #ifndef ASSEMBLER
71 #include <sys/cdefs.h>
72 #include <mach/boolean.h>
73 #include <mach/kern_return.h>
74 #include <mach/i386/thread_status.h>
75
76 __BEGIN_DECLS
77
78 extern kern_return_t intel_startCPU(int slot_num);
79 extern void i386_init_slave(void);
80 extern void smp_init(void);
81
82 extern void cpu_interrupt(int cpu);
83
84 extern void lapic_init(void);
85 extern void lapic_shutdown(void);
86 extern void lapic_smm_restore(void);
87 extern boolean_t lapic_probe(void);
88 extern void lapic_dump(void);
89 extern int lapic_interrupt(int interrupt, x86_saved_state_t *state);
90 extern void lapic_end_of_interrupt(void);
91 extern int lapic_to_cpu[];
92 extern int cpu_to_lapic[];
93 extern int lapic_interrupt_base;
94 extern void lapic_cpu_map(int lapic, int cpu_num);
95 extern uint32_t ml_get_apicid(uint32_t cpu);
96
97 extern void lapic_set_timer(
98 boolean_t interrupt,
99 lapic_timer_mode_t mode,
100 lapic_timer_divide_t divisor,
101 lapic_timer_count_t initial_count);
102
103 extern void lapic_get_timer(
104 lapic_timer_mode_t *mode,
105 lapic_timer_divide_t *divisor,
106 lapic_timer_count_t *initial_count,
107 lapic_timer_count_t *current_count);
108
109 typedef void (*i386_intr_func_t)(void *);
110 extern void lapic_set_timer_func(i386_intr_func_t func);
111 extern void lapic_set_pmi_func(i386_intr_func_t func);
112 extern void lapic_set_thermal_func(i386_intr_func_t func);
113
114 __END_DECLS
115
116 /*
117 * By default, use high vectors to leave vector space for systems
118 * with multiple I/O APIC's. However some systems that boot with
119 * local APIC disabled will hang in SMM when vectors greater than
120 * 0x5F are used. Those systems are not expected to have I/O APIC
121 * so 16 (0x50 - 0x40) vectors for legacy PIC support is perfect.
122 */
123 #define LAPIC_DEFAULT_INTERRUPT_BASE 0xD0
124 #define LAPIC_REDUCED_INTERRUPT_BASE 0x50
125 /*
126 * Specific lapic interrupts are relative to this base
127 * in priority order from high to low:
128 */
129
130 #define LAPIC_PERFCNT_INTERRUPT 0xF
131 #define LAPIC_TIMER_INTERRUPT 0xE
132 #define LAPIC_INTERPROCESSOR_INTERRUPT 0xD
133 #define LAPIC_THERMAL_INTERRUPT 0xC
134 #define LAPIC_ERROR_INTERRUPT 0xB
135 #define LAPIC_SPURIOUS_INTERRUPT 0xA
136 /* The vector field is ignored for NMI interrupts via the LAPIC
137 * or otherwise, so this is not an offset from the interrupt
138 * base.
139 */
140 #define LAPIC_NMI_INTERRUPT 0x2
141
142 #define LAPIC_REG(reg) \
143 (*((volatile uint32_t *)(lapic_start + LAPIC_##reg)))
144 #define LAPIC_REG_OFFSET(reg,off) \
145 (*((volatile uint32_t *)(lapic_start + LAPIC_##reg + (off))))
146
147 #define LAPIC_VECTOR(src) \
148 (lapic_interrupt_base + LAPIC_##src##_INTERRUPT)
149
150 #define LAPIC_ISR_IS_SET(base,src) \
151 (LAPIC_REG_OFFSET(ISR_BASE,((base+LAPIC_##src##_INTERRUPT)/32)*0x10) & \
152 (1 <<((base + LAPIC_##src##_INTERRUPT)%32)))
153
154 extern vm_offset_t lapic_start;
155
156 #endif /* ASSEMBLER */
157
158 #define CPU_NUMBER(r) \
159 movl %gs:CPU_NUMBER_GS,r
160
161 #define CPU_NUMBER_FROM_LAPIC(r) \
162 movl EXT(lapic_id),r; \
163 movl 0(r),r; \
164 shrl $(LAPIC_ID_SHIFT),r; \
165 andl $(LAPIC_ID_MASK),r; \
166 movl EXT(lapic_to_cpu)(,r,4),r
167
168
169 /* word describing the reason for the interrupt, one per cpu */
170
171 #ifndef ASSEMBLER
172 #include <kern/lock.h>
173
174 extern unsigned int real_ncpus; /* real number of cpus */
175 extern unsigned int max_ncpus; /* max number of cpus */
176 decl_simple_lock_data(extern,kdb_lock) /* kdb lock */
177
178 __BEGIN_DECLS
179
180 extern void console_init(void);
181 extern void *console_cpu_alloc(boolean_t boot_cpu);
182 extern void console_cpu_free(void *console_buf);
183
184 extern int kdb_cpu; /* current cpu running kdb */
185 extern int kdb_debug;
186 extern int kdb_active[];
187
188 extern volatile boolean_t mp_kdp_trap;
189 extern void mp_kdp_enter(void);
190 extern void mp_kdp_exit(void);
191
192 #if MACH_KDB
193 extern void mp_kdb_exit(void);
194 #endif
195
196 /*
197 * All cpu rendezvous:
198 */
199 extern void mp_rendezvous(
200 void (*setup_func)(void *),
201 void (*action_func)(void *),
202 void (*teardown_func)(void *),
203 void *arg);
204 extern void mp_rendezvous_no_intrs(
205 void (*action_func)(void *),
206 void *arg);
207 extern void mp_rendezvous_break_lock(void);
208
209 __END_DECLS
210
211 #if MP_DEBUG
212 typedef struct {
213 uint64_t time;
214 int cpu;
215 mp_event_t event;
216 } cpu_signal_event_t;
217
218 #define LOG_NENTRIES 100
219 typedef struct {
220 uint64_t count[MP_LAST];
221 int next_entry;
222 cpu_signal_event_t entry[LOG_NENTRIES];
223 } cpu_signal_event_log_t;
224
225 extern cpu_signal_event_log_t *cpu_signal[];
226 extern cpu_signal_event_log_t *cpu_handle[];
227
228 #define DBGLOG(log,_cpu,_event) { \
229 boolean_t spl = ml_set_interrupts_enabled(FALSE); \
230 cpu_signal_event_log_t *logp = log[cpu_number()]; \
231 int next = logp->next_entry; \
232 cpu_signal_event_t *eventp = &logp->entry[next]; \
233 \
234 logp->count[_event]++; \
235 \
236 eventp->time = rdtsc64(); \
237 eventp->cpu = _cpu; \
238 eventp->event = _event; \
239 if (next == (LOG_NENTRIES - 1)) \
240 logp->next_entry = 0; \
241 else \
242 logp->next_entry++; \
243 \
244 (void) ml_set_interrupts_enabled(spl); \
245 }
246
247 #define DBGLOG_CPU_INIT(cpu) { \
248 cpu_signal_event_log_t **sig_logpp = &cpu_signal[cpu]; \
249 cpu_signal_event_log_t **hdl_logpp = &cpu_handle[cpu]; \
250 \
251 if (*sig_logpp == NULL && \
252 kmem_alloc(kernel_map, \
253 (vm_offset_t *) sig_logpp, \
254 sizeof(cpu_signal_event_log_t)) != KERN_SUCCESS)\
255 panic("DBGLOG_CPU_INIT cpu_signal allocation failed\n");\
256 bzero(*sig_logpp, sizeof(cpu_signal_event_log_t)); \
257 if (*hdl_logpp == NULL && \
258 kmem_alloc(kernel_map, \
259 (vm_offset_t *) hdl_logpp, \
260 sizeof(cpu_signal_event_log_t)) != KERN_SUCCESS)\
261 panic("DBGLOG_CPU_INIT cpu_handle allocation failed\n");\
262 bzero(*sig_logpp, sizeof(cpu_signal_event_log_t)); \
263 }
264 #else /* MP_DEBUG */
265 #define DBGLOG(log,_cpu,_event)
266 #define DBGLOG_CPU_INIT(cpu)
267 #endif /* MP_DEBUG */
268
269 #endif /* ASSEMBLER */
270
271 #define i_bit(bit, word) ((long)(*(word)) & ((long)1 << (bit)))
272
273
274 /*
275 * Device driver synchronization.
276 *
277 * at386_io_lock(op) and at386_io_unlock() are called
278 * by device drivers when accessing H/W. The underlying
279 * Processing is machine dependant. But the op argument
280 * to the at386_io_lock is generic
281 */
282
283 #define MP_DEV_OP_MAX 4
284 #define MP_DEV_WAIT MP_DEV_OP_MAX /* Wait for the lock */
285
286 /*
287 * If the caller specifies an op value different than MP_DEV_WAIT, the
288 * at386_io_lock function must return true if lock was successful else
289 * false
290 */
291
292 #define MP_DEV_OP_START 0 /* If lock busy, register a pending start op */
293 #define MP_DEV_OP_INTR 1 /* If lock busy, register a pending intr */
294 #define MP_DEV_OP_TIMEO 2 /* If lock busy, register a pending timeout */
295 #define MP_DEV_OP_CALLB 3 /* If lock busy, register a pending callback */
296
297 #if MACH_RT
298 #define _DISABLE_PREEMPTION \
299 incl %gs:CPU_PREEMPTION_LEVEL
300
301 #define _ENABLE_PREEMPTION \
302 decl %gs:CPU_PREEMPTION_LEVEL ; \
303 jne 9f ; \
304 pushl %eax ; \
305 pushl %ecx ; \
306 pushl %edx ; \
307 call EXT(kernel_preempt_check) ; \
308 popl %edx ; \
309 popl %ecx ; \
310 popl %eax ; \
311 9:
312
313 #define _ENABLE_PREEMPTION_NO_CHECK \
314 decl %gs:CPU_PREEMPTION_LEVEL
315
316 #if MACH_ASSERT
317 #define DISABLE_PREEMPTION \
318 pushl %eax; \
319 pushl %ecx; \
320 pushl %edx; \
321 call EXT(_disable_preemption); \
322 popl %edx; \
323 popl %ecx; \
324 popl %eax
325 #define ENABLE_PREEMPTION \
326 pushl %eax; \
327 pushl %ecx; \
328 pushl %edx; \
329 call EXT(_enable_preemption); \
330 popl %edx; \
331 popl %ecx; \
332 popl %eax
333 #define ENABLE_PREEMPTION_NO_CHECK \
334 pushl %eax; \
335 pushl %ecx; \
336 pushl %edx; \
337 call EXT(_enable_preemption_no_check); \
338 popl %edx; \
339 popl %ecx; \
340 popl %eax
341 #define MP_DISABLE_PREEMPTION \
342 pushl %eax; \
343 pushl %ecx; \
344 pushl %edx; \
345 call EXT(_mp_disable_preemption); \
346 popl %edx; \
347 popl %ecx; \
348 popl %eax
349 #define MP_ENABLE_PREEMPTION \
350 pushl %eax; \
351 pushl %ecx; \
352 pushl %edx; \
353 call EXT(_mp_enable_preemption); \
354 popl %edx; \
355 popl %ecx; \
356 popl %eax
357 #define MP_ENABLE_PREEMPTION_NO_CHECK \
358 pushl %eax; \
359 pushl %ecx; \
360 pushl %edx; \
361 call EXT(_mp_enable_preemption_no_check); \
362 popl %edx; \
363 popl %ecx; \
364 popl %eax
365 #else /* MACH_ASSERT */
366 #define DISABLE_PREEMPTION _DISABLE_PREEMPTION
367 #define ENABLE_PREEMPTION _ENABLE_PREEMPTION
368 #define ENABLE_PREEMPTION_NO_CHECK _ENABLE_PREEMPTION_NO_CHECK
369 #define MP_DISABLE_PREEMPTION _DISABLE_PREEMPTION
370 #define MP_ENABLE_PREEMPTION _ENABLE_PREEMPTION
371 #define MP_ENABLE_PREEMPTION_NO_CHECK _ENABLE_PREEMPTION_NO_CHECK
372 #endif /* MACH_ASSERT */
373
374 #else /* MACH_RT */
375 #define DISABLE_PREEMPTION
376 #define ENABLE_PREEMPTION
377 #define ENABLE_PREEMPTION_NO_CHECK
378 #define MP_DISABLE_PREEMPTION
379 #define MP_ENABLE_PREEMPTION
380 #define MP_ENABLE_PREEMPTION_NO_CHECK
381 #endif /* MACH_RT */
382
383 #endif /* _I386AT_MP_H_ */
384
385 #endif /* KERNEL_PRIVATE */