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1 /*
2 * Copyright (c) 2000-2004 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_COPYRIGHT@
24 */
25
26 #define __APPLE_API_PRIVATE
27
28 #include <mach_kdb.h>
29 #include <mach_kdp.h>
30 #include <mach_kgdb.h>
31 #include <ppc/asm.h>
32 #include <ppc/proc_reg.h>
33 #include <ppc/spec_reg.h>
34 #include <machine/cpu_capabilities.h>
35 #include <mach/ppc/vm_param.h>
36 #include <assym.s>
37
38
39 ; Definitions of the processor type table format, which drives this code.
40 ; The table ("processor_types") is assembled in at the end of this file.
41
42 #define ptFilter 0
43 #define ptVersion 4
44 #define ptRevision 6
45 #define ptFeatures 8
46 #define ptCPUCap 12
47 #define ptPwrModes 16
48 #define ptPatch 20
49 #define ptInitRout 24
50 #define ptRptdProc 28
51 #define ptLineSize 32
52 #define ptl1iSize 36
53 #define ptl1dSize 40
54 #define ptPTEG 44
55 #define ptMaxVAddr 48
56 #define ptMaxPAddr 52
57 #define ptSize 56
58
59
60 ; We use cr2 for flags:
61
62 #define bootCPU 10
63 #define firstInit 9
64 #define firstBoot 8
65
66 /*
67 * Interrupt and bootup stack for initial processor
68 */
69
70 .file "start.s"
71
72 /*
73 * All CPUs start here.
74 *
75 * This code is called from SecondaryLoader
76 *
77 * Various arguments are passed via a table:
78 * R3 = pointer to other startup parameters
79 */
80 .text
81
82 ENTRY(resetPOR,TAG_NO_FRAME_USED)
83
84 li r12,0 ; Get a 0
85 stw r12,0xF0(0) ; Make sure the special flag is clear
86 mtmsrd r12 ; Make sure we are in 32-bit mode
87 isync ; Really make sure
88 lwz r3,0xF4(0) ; Get the boot_args pointer
89 b startJoin ; Join up...
90
91
92 ENTRY(_start_cpu,TAG_NO_FRAME_USED)
93 crclr bootCPU ; Set non-boot processor
94 crclr firstInit ; Set not first time init
95 lwz r30,ppe_paddr(r3) ; Set current per_proc
96 lwz r28,ppe_paddr+4(r3) ; Set current per_proc
97 rlwinm r30,r30,0,1,0 ; Copy low 32 bits to top 32
98 rlwimi r30,r28,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
99 subi r29,r3,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
100 mr r3,r30 ; Set current per_proc
101
102 ;
103 ; Note that we are just trying to get close. The real TB sync will take
104 ; place later. The value we are loading is set in two places. For the
105 ; main processor, it will be the TB at the last interrupt before we went
106 ; to sleep. For the others, it will be the time just before the main
107 ; processor woke us up.
108 ;
109
110 lwz r15,ruptStamp(r3) ; Get the timebase from the other processor
111 li r17,0 ; Clear this out
112 lwz r16,ruptStamp+4(r3) ; Get the timebase from the other processor
113 mtspr tbl,r17 ; Clear bottom so we do not tick
114 mtspr tbu,r15 ; Set top
115 mtspr tbl,r16 ; Then bottom again
116 b allstart
117
118 ENTRY(_start,TAG_NO_FRAME_USED)
119
120 startJoin:
121 mflr r2 ; Save the return address
122 lis r28,hi16(EXT(PerProcTable)) ; Set PerProcTable
123 lis r30,hi16(EXT(BootProcInfo)) ; Set current per_proc
124 ori r28,r28,lo16(EXT(PerProcTable)) ; Set PerProcTable
125 ori r30,r30,lo16(EXT(BootProcInfo)) ; Set current per_proc
126 stw r30,ppe_paddr+4(r28) ; Set per_proc_entry
127 stw r30,ppe_vaddr(r28) ; Set per_proc_entry
128 subi r29,r28,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
129 crset bootCPU ; Set boot processor
130
131 lwz r17,pfAvailable(r30) ; Get the available bits
132 rlwinm. r0,r17,0,pfValidb,pfValidb ; Have we initialized the feature flags yet?
133 crmove firstInit,cr0_eq ; Set if we are doing first time init
134 bne allstart ; Yeah, we must be waking up from sleep...
135
136 ;
137 ; Here is where we do any one time general low-level initialization
138
139 lis r20,HIGH_ADDR(fwdisplock) ; Get address of the firmware display lock
140 li r19,0 ; Zorch a register
141 ori r20,r20,LOW_ADDR(fwdisplock) ; Get address of the firmware display lock
142 stw r19,0(r20) ; Make sure the lock is free
143
144 allstart:
145 mr r31,r3 ; Save away arguments
146
147 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
148
149 mtsprg 0,r30 ; Set per_proc paddr
150 mtsprg 1,r29 ; Set spr1
151
152 li r9,0 ; Clear out a register
153 mtsprg 2,r9
154 mtsprg 3,r9
155
156 li r7,MSR_VM_OFF ; Get real mode MSR
157 mtmsr r7 ; Set the real mode SRR
158 isync
159
160 lis r26,hi16(processor_types) ; Point to processor table
161 ori r26,r26,lo16(processor_types) ; Other half
162 mfpvr r10 ; Get the PVR
163
164 nextPVR: lwz r28,ptFilter(r26) ; Get the filter
165 lwz r27,ptVersion(r26) ; Get the version and revision codes
166 and r28,r10,r28 ; Throw away dont care bits
167 cmplw r27,r28 ; Is this the right set?
168 beq donePVR ; We have the right one...
169 addi r26,r26,ptSize ; Point to the next type
170 b nextPVR ; Check it out...
171
172 donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine
173 mtlr r20 ; Setup to call the init
174
175 bf firstBoot,notFirst ; Not first boot, go...
176
177 ;
178 ; The following code just does a general initialization of the features just
179 ; after the initial first-time boot. This is not done after waking up or on
180 ; any "secondary" processor. Just after the boot-processor init, we copy the
181 ; features to any possible per_proc.
182 ;
183 ; We are just setting defaults. The specific initialization code will modify these
184 ; if necessary.
185 ;
186 lis r18,hi16(EXT(_cpu_capabilities)) ; Get the address of _cpu_capabilities
187 ori r18,r18,lo16(EXT(_cpu_capabilities))
188 lwz r17,ptCPUCap(r26) ; Get the default cpu capabilities
189 stw r17, 0(r18) ; Save the default value in _cpu_capabilities
190
191 lwz r17,ptFeatures(r26) ; Pick up the features
192
193 lwz r18,ptRptdProc(r26) ; Get the reported processor
194 sth r18,pfrptdProc(r30) ; Set the reported processor
195
196 lwz r13,ptPwrModes(r26) ; Get the supported power modes
197 stw r13,pfPowerModes(r30) ; Set the supported power modes
198
199 lwz r13,ptLineSize(r26) ; Get the cache line size
200 sth r13,pflineSize(r30) ; Save it
201 lwz r13,ptl1iSize(r26) ; Get icache size
202 stw r13,pfl1iSize(r30) ; Save it
203 lwz r13,ptl1dSize(r26) ; Get dcache size
204 stw r13,pfl1dSize(r30) ; Save it
205 lwz r13,ptPTEG(r26) ; Get PTEG size address
206 stw r13,pfPTEG(r30) ; Save it
207 lwz r13,ptMaxVAddr(r26) ; Get max virtual address
208 stw r13,pfMaxVAddr(r30) ; Save it
209 lwz r13,ptMaxPAddr(r26) ; Get max physical address
210 stw r13,pfMaxPAddr(r30) ; Save it
211
212
213 ; Go through the patch table, changing performance sensitive kernel routines based on the
214 ; processor type or other things.
215
216 lis r11,hi16(EXT(patch_table))
217 ori r11,r11,lo16(EXT(patch_table))
218 lwz r19,ptPatch(r26) ; Get ptPatch field
219 patch_loop:
220 lwz r16,patchType(r11) ; Load the patch type
221 lwz r15,patchValue(r11) ; Load the patch value
222 cmplwi cr1,r16,PATCH_FEATURE ; Is it a patch feature entry
223 cmplwi cr7,r16,PATCH_END_OF_TABLE ; end of table?
224 and. r14,r15,r19 ; Is it set in the patch feature
225 crandc cr0_eq,cr1_eq,cr0_eq ; Do we have a match
226 beq cr7,doOurInit ; end of table, Go do processor specific initialization
227 beq patch_apply ; proc feature matches, so patch memory
228 cmplwi cr1,r16,PATCH_PROCESSOR ; Is it a patch processor entry
229 cmplw cr0,r15,r18 ; Check matching processor
230 crand cr0_eq,cr1_eq,cr0_eq ; Do we have a match
231 bne patch_skip ; No, skip patch memory
232 patch_apply:
233 lwz r13,patchAddr(r11) ; Load the address to patch
234 lwz r14,patchData(r11) ; Load the patch data
235 stw r14,0(r13) ; Patch the location
236 dcbf 0,r13 ; Flush the old one
237 sync ; Make sure we see it all
238 icbi 0,r13 ; Flush the i-cache
239 isync ; Hang out
240 sync ; Hang out some more...
241 patch_skip:
242 addi r11,r11,peSize ; Point to the next patch entry
243 b patch_loop ; handle next
244
245
246 ; Additional processors join here after skipping above code.
247
248 notFirst: lwz r17,pfAvailable(r30) ; Get our features
249
250 doOurInit: mr. r20,r20 ; See if initialization routine
251 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
252 bnelrl ; Do the initialization
253
254 ori r17,r17,lo16(pfValid) ; Set the valid bit
255 stw r17,pfAvailable(r30) ; Set the available features
256
257 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
258 mtsprg 2,r17 ; Remember the feature flags
259
260 bne++ start64 ; Skip following if 64-bit...
261
262 mfspr r6,hid0 ; Get the HID0
263 rlwinm r6,r6,0,sleep+1,doze-1 ; Remove any vestiges of sleep
264 mtspr hid0,r6 ; Set the insominac HID0
265 isync
266
267 ; Clear the BAT registers
268
269 li r9,0 ; Clear out a register
270 sync
271 isync
272 mtdbatu 0,r9 ; Invalidate maps
273 mtdbatl 0,r9 ; Invalidate maps
274 mtdbatu 1,r9 ; Invalidate maps
275 mtdbatl 1,r9 ; Invalidate maps
276 mtdbatu 2,r9 ; Invalidate maps
277 mtdbatl 2,r9 ; Invalidate maps
278 mtdbatu 3,r9 ; Invalidate maps
279 mtdbatl 3,r9 ; Invalidate maps
280 sync
281 isync
282 mtibatu 0,r9 ; Invalidate maps
283 mtibatl 0,r9 ; Invalidate maps
284 mtibatu 1,r9 ; Invalidate maps
285 mtibatl 1,r9 ; Invalidate maps
286 mtibatu 2,r9 ; Invalidate maps
287 mtibatl 2,r9 ; Invalidate maps
288 mtibatu 3,r9 ; Invalidate maps
289 mtibatl 3,r9 ; Invalidate maps
290 sync
291 isync
292 b startcommon ; Go join up the common start routine
293
294 start64: lis r5,hi16(startcommon) ; Get top of address of continue point
295 mfspr r6,hid0 ; Get the HID0
296 ori r5,r5,lo16(startcommon) ; Get low of address of continue point
297 lis r9,hi16(MASK(MSR_HV)|MASK(MSR_SF)) ; ?
298 lis r20,hi16(dozem|napm|sleepm) ; Get mask of power saving features
299 li r7,MSR_VM_OFF ; Get real mode MSR
300 sldi r9,r9,32 ; Slide into position
301 sldi r20,r20,32 ; Slide power stuff into position
302 or r9,r9,r7 ; Form initial MSR
303 andc r6,r6,r20 ; Remove any vestiges of sleep
304 isync
305 mtspr hid0,r6 ; Set the insominac HID0
306 mfspr r6,hid0 ; Get it
307 mfspr r6,hid0 ; Get it
308 mfspr r6,hid0 ; Get it
309 mfspr r6,hid0 ; Get it
310 mfspr r6,hid0 ; Get it
311 mfspr r6,hid0 ; Get it
312 isync
313 mtsrr0 r5 ; Set the continue point
314 mtsrr1 r9 ; Set our normal disabled MSR
315 rfid ; Tally ho...
316
317 .align 5
318
319 startcommon:
320 rlwinm. r0,r17,0,pfFloatb,pfFloatb ; See if there is floating point
321 beq- noFloat ; Nope, this is a really stupid machine...
322
323 li r0,MSR_VM_OFF|MASK(MSR_FP) ; Enable for floating point
324 mtmsr r0 /* Set the standard MSR values */
325 isync
326
327 lis r5,HIGH_ADDR(EXT(FloatInit)) /* Get top of floating point init value */
328 ori r5,r5,LOW_ADDR(EXT(FloatInit)) /* Slam bottom */
329 lfd f0,0(r5) /* Initialize FP0 */
330 fmr f1,f0 /* Ours in not */
331 fmr f2,f0 /* to wonder why, */
332 fmr f3,f0 /* ours is but to */
333 fmr f4,f0 /* do or die! */
334 fmr f5,f0
335 fmr f6,f0
336 fmr f7,f0
337 fmr f8,f0
338 fmr f9,f0
339 fmr f10,f0
340 fmr f11,f0
341 fmr f12,f0
342 fmr f13,f0
343 fmr f14,f0
344 fmr f15,f0
345 fmr f16,f0
346 fmr f17,f0
347 fmr f18,f0
348 fmr f19,f0
349 fmr f20,f0
350 fmr f21,f0
351 fmr f22,f0
352 fmr f23,f0
353 fmr f24,f0
354 fmr f25,f0
355 fmr f26,f0
356 fmr f27,f0
357 fmr f28,f0
358 fmr f29,f0
359 fmr f30,f0
360 fmr f31,f0
361
362 li r0, MSR_VM_OFF ; Turn off floating point
363 mtmsr r0
364 isync
365
366 noFloat: rlwinm. r0,r17,0,pfAltivecb,pfAltivecb ; See if there is Altivec
367 beq- noVector ; Nope...
368
369 li r0,0 ; Clear out a register
370
371 lis r7,hi16(MSR_VEC_ON) ; Get real mode MSR + Altivec
372 ori r7,r7,lo16(MSR_VM_OFF) ; Get real mode MSR + Altivec
373 mtmsr r7 ; Set the real mode SRR */
374 isync ; Make sure it has happened
375
376 lis r5,hi16(EXT(QNaNbarbarian)) ; Altivec initializer
377 ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Altivec initializer
378
379 mtspr vrsave,r0 ; Set that no VRs are used yet */
380
381 vspltish v1,1 ; Turn on the non-Java bit and saturate
382 vspltisw v0,1 ; Turn on the saturate bit
383 vxor v1,v1,v0 ; Turn off saturate and leave non-Java set
384 lvx v0,br0,r5 ; Initialize VR0
385 mtvscr v1 ; Clear the vector status register
386 vor v2,v0,v0 ; Copy into the next register
387 vor v1,v0,v0 ; Copy into the next register
388 vor v3,v0,v0 ; Copy into the next register
389 vor v4,v0,v0 ; Copy into the next register
390 vor v5,v0,v0 ; Copy into the next register
391 vor v6,v0,v0 ; Copy into the next register
392 vor v7,v0,v0 ; Copy into the next register
393 vor v8,v0,v0 ; Copy into the next register
394 vor v9,v0,v0 ; Copy into the next register
395 vor v10,v0,v0 ; Copy into the next register
396 vor v11,v0,v0 ; Copy into the next register
397 vor v12,v0,v0 ; Copy into the next register
398 vor v13,v0,v0 ; Copy into the next register
399 vor v14,v0,v0 ; Copy into the next register
400 vor v15,v0,v0 ; Copy into the next register
401 vor v16,v0,v0 ; Copy into the next register
402 vor v17,v0,v0 ; Copy into the next register
403 vor v18,v0,v0 ; Copy into the next register
404 vor v19,v0,v0 ; Copy into the next register
405 vor v20,v0,v0 ; Copy into the next register
406 vor v21,v0,v0 ; Copy into the next register
407 vor v22,v0,v0 ; Copy into the next register
408 vor v23,v0,v0 ; Copy into the next register
409 vor v24,v0,v0 ; Copy into the next register
410 vor v25,v0,v0 ; Copy into the next register
411 vor v26,v0,v0 ; Copy into the next register
412 vor v27,v0,v0 ; Copy into the next register
413 vor v28,v0,v0 ; Copy into the next register
414 vor v29,v0,v0 ; Copy into the next register
415 vor v30,v0,v0 ; Copy into the next register
416 vor v31,v0,v0 ; Copy into the next register
417
418 li r0, MSR_VM_OFF ; Turn off vectors
419 mtmsr r0
420 isync
421
422 noVector:
423 bl EXT(cacheInit) ; Initializes all caches (including the TLB)
424
425 bt bootCPU,run32
426
427 mfsprg r30,0 ; Phys per proc
428 bl EXT(hw_setup_trans) ; Set up hardware needed for translation
429 bl EXT(hw_start_trans) ; Start translating
430
431 run32:
432 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
433 beq++ isnot64 ; Skip following if not 64-bit...
434
435 mfmsr r29 ; Get the MSR
436 rldicl r29,r29,0,MSR_SF_BIT+1 ; turn 64-bit mode off
437 mtmsrd r29 ; Set it
438 isync ; Make sure
439
440 isnot64: bf bootCPU,callcpu
441
442 lis r29,HIGH_ADDR(EXT(intstack)) ; move onto interrupt stack
443 ori r29,r29,LOW_ADDR(EXT(intstack))
444 addi r29,r29,INTSTACK_SIZE-FM_SIZE
445
446 li r28,0
447 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
448
449 mr r1,r29
450 mr r3,r31 ; Restore any arguments we may have trashed
451
452 ; Note that we exit from here with translation still off
453
454 bl EXT(ppc_init) ; Jump into boot init code
455 BREAKPOINT_TRAP
456
457 callcpu:
458 mfsprg r31,1 ; Fake activation pointer
459 lwz r31,ACT_PER_PROC(r31) ; Load per_proc
460 lwz r29,PP_INTSTACK_TOP_SS(r31) ; move onto interrupt stack
461
462 li r28,0
463 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
464
465 mr r1,r29 ; move onto new stack
466 mr r3,r31 ; Restore any arguments we may have trashed
467
468 ; Note that we exit from here with translation on
469
470 bl EXT(ppc_init_cpu) ; Jump into cpu init code
471 BREAKPOINT_TRAP ; Should never return
472
473 ;
474 ; Specific processor initialization routines
475 ;
476
477 ; 750
478
479 init750:
480 bf firstBoot, init750nb ; No init for wakeup....
481
482 mfspr r13,l2cr ; Get the L2CR
483 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
484 bne+ i750hl2 ; Yes...
485 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
486
487 i750hl2:
488 lis r14,hi16(256*1024) ; Base L2 size
489 addis r15,r13,0x3000 ; Hah... Figure this one out...
490 rlwinm r15,r15,4,30,31 ; Isolate
491 rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
492 slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
493 beq- init750l2none ; Not a valid setting...
494
495 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
496 stw r13,pfl2cr(r30) ; Shadow the L2CR
497 stw r14,pfl2Size(r30) ; Set the L2 size
498 b init750l2done ; Done with L2
499
500 init750l2none:
501 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
502
503 init750l2done:
504 mfspr r11,hid0 ; Get the current HID0
505 stw r11,pfHID0(r30) ; Save the HID0 value
506 blr ; Return...
507
508 init750nb:
509 lwz r11,pfHID0(r30) ; Get HID0
510 sync
511 mtspr hid0,r11 ; Set the HID
512 isync
513 sync
514 blr
515
516 ; 750CX
517
518 init750CX:
519 bf firstBoot, init750 ; No init for wakeup....
520 mfspr r13,hid1 ; Get HID1
521 li r14,lo16(0xFD5F) ; Get valid
522 rlwinm r13,r13,4,28,31 ; Isolate
523 slw r14,r14,r13 ; Position
524 rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it
525 b init750 ; Join common...
526
527
528 ; 750FX
529
530 init750FX:
531 bf firstBoot, init750FXnb
532 mfspr r11, hid1
533 stw r11, pfHID1(r30) ; Save the HID1 value
534 b init750
535
536 init750FXnb:
537 lwz r13, pfHID0(r30) ; Get HID0
538 lwz r11, pfHID1(r30) ; Get HID1
539
540 rlwinm. r0, r11, 0, hid1ps, hid1ps ; Isolate the hid1ps bit
541 beq init750FXnb2 ; Clear BTIC if hid1ps set
542 rlwinm r13, r13, 0, btic+1, btic-1 ; Clear the BTIC bit
543
544 init750FXnb2:
545 sync
546 mtspr hid0, r13 ; Set the HID
547 isync
548 sync
549
550 rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 ; Select PLL0
551 mtspr hid1, r12 ; Restore PLL config
552 mftb r13 ; Wait 5000 ticks (> 200 us)
553
554 init750FXnbloop:
555 mftb r14
556 sub r14, r14, r13
557 cmpli cr0, r14, 5000
558 ble init750FXnbloop
559 mtspr hid1, r11 ; Select the desired PLL
560 blr
561
562 ; 750FX vers 2.0 or later
563 init750FXV2:
564 bf firstBoot, init750FXV2nb ; Wake from sleep
565
566 mfspr r11, hid2
567 stw r11, pfHID2(r30) ; Save the HID2 value
568 b init750FX ; Continue with 750FX init
569
570 init750FXV2nb:
571 lwz r13, pfHID2(r30) ; Get HID2
572 rlwinm r13, r13, 0, hid2vmin+1, hid2vmin-1 ; Clear the vmin bit
573 mtspr hid2, r13 ; Restore HID2 value
574 sync ; Wait for it to be done
575 b init750FX
576
577 ; 7400
578
579 init7400: bf firstBoot,i7400nb ; Do different if not initial boot...
580 mfspr r13,l2cr ; Get the L2CR
581 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
582 bne+ i7400hl2 ; Yes...
583 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
584
585 i7400hl2: lis r14,hi16(256*1024) ; Base L2 size
586 addis r15,r13,0x3000 ; Hah... Figure this one out...
587 rlwinm r15,r15,4,30,31
588 slw r14,r14,r15 ; Set 256KB, 512KB, 1MB, or 2MB
589
590 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
591 stw r13,pfl2cr(r30) ; Shadow the L2CR
592 stw r14,pfl2Size(r30) ; Set the L2 size
593
594 mfspr r11,hid0 ; Get the current HID0
595 oris r11,r11,hi16(emcpm|eiecm) ; ?
596 mtspr hid0,r11 ; ?
597 isync
598 stw r11,pfHID0(r30) ; Save the HID0 value
599
600 mfspr r11,msscr0 ; Get the msscr0 register
601 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
602 mfspr r11,msscr1 ; Get the msscr1 register
603 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
604 blr ; Return...
605
606 i7400nb:
607 li r11,0
608 mtspr l2cr,r11 ; Make sure L2CR is zero
609 lwz r11,pfHID0(r30) ; Get HID0
610 sync
611 mtspr hid0,r11 ; Set the HID
612 isync
613 sync
614 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
615 isync
616 sync
617 mtspr msscr0,r11 ; Set the MSSCR0
618 lwz r11,pfMSSCR1(r30) ; Get msscr1
619 isync
620 sync
621 mtspr msscr1,r11 ; Set the msscr1
622 isync
623 sync
624 blr
625
626 ; 7400 (ver 2.0 - ver 2.7)
627
628 init7400v2_7:
629 bf firstBoot, init7400
630 mfspr r13, hid0 ; Get the HID0
631 ori r13, r13, nopdstm ; ?
632 mtspr hid0, r13 ; Set the HID0
633 isync
634 sync
635 b init7400
636
637 ; 7410
638 ; Note that this is the same as 7400 except we initialize the l2cr2 register
639
640 init7410: li r13,0 ; Clear
641 mtspr 1016,r13 ; Turn off direct cache
642 b init7400 ; Join up with common....
643
644
645 ; 745X - Any 7450 family processor
646
647 init745X:
648 bf firstBoot,init745Xnb ; Do different if not initial boot...
649
650 mfspr r13,l2cr ; Get the L2CR
651 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
652 bne+ init745Xhl2 ; Yes...
653 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
654
655 init745Xhl2:
656 mfpvr r14 ; Get processor version
657 rlwinm r14,r14,16,16,31 ; Isolate processor version
658 cmpli cr0, r14, PROCESSOR_VERSION_7457 ; Test for 7457 or
659 cmpli cr1, r14, PROCESSOR_VERSION_7447A ; 7447A
660 cror cr0_eq, cr1_eq, cr0_eq
661 lis r14,hi16(512*1024) ; 512KB L2
662 beq init745Xhl2_2
663
664 lis r14,hi16(256*1024) ; Base L2 size
665 rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k
666 add r14,r14,r15 ; Add in minimum
667
668 init745Xhl2_2:
669 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
670 stw r13,pfl2cr(r30) ; Shadow the L2CR
671 stw r14,pfl2Size(r30) ; Set the L2 size
672
673 ; Take care of level 3 cache
674
675 mfspr r13,l3cr ; Get the L3CR
676 rlwinm. r0,r13,0,l3e,l3e ; Any L3?
677 bne+ init745Xhl3 ; Yes...
678 rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L3, turn off feature
679
680 init745Xhl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero
681 beq- init745Xnone ; Go turn off the features...
682 lis r14,hi16(1024*1024) ; Base L3 size
683 rlwinm r15,r13,4,31,31 ; Get size multiplier
684 slw r14,r14,r15 ; Set 1 or 2MB
685
686 stw r13,pfl3crOriginal(r30) ; Shadow the L3CR
687 stw r13,pfl3cr(r30) ; Shadow the L3CR
688 stw r14,pfl3Size(r30) ; Set the L3 size
689 b init745Xfin ; Return....
690
691 init745Xnone:
692 rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
693 rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set
694 or r17,r17,r11
695
696 init745Xfin:
697 rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set
698
699 mfspr r11,hid0 ; Get the current HID0
700 stw r11,pfHID0(r30) ; Save the HID0 value
701 mfspr r11,hid1 ; Get the current HID1
702 stw r11,pfHID1(r30) ; Save the HID1 value
703 mfspr r11,msscr0 ; Get the msscr0 register
704 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
705 mfspr r11,msscr1 ; Get the msscr1 register
706 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
707 mfspr r11,ictrl ; Get the ictrl register
708 stw r11,pfICTRL(r30) ; Save the ICTRL value
709 mfspr r11,ldstcr ; Get the ldstcr register
710 stw r11,pfLDSTCR(r30) ; Save the LDSTCR value
711 mfspr r11,ldstdb ; Get the ldstdb register
712 stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
713 mfspr r11,pir ; Get the pir register
714 stw r11,pfBootConfig(r30) ; Save the BootConfig value
715 blr ; Return....
716
717
718 init745Xnb: lwz r11,pfHID0(r30) ; Get HID0
719 sync
720 mtspr hid0,r11 ; Set the HID
721 isync
722 lwz r11,pfHID1(r30) ; Get HID1
723 sync
724 mtspr hid1,r11 ; Set the HID
725 isync
726 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
727 sync
728 mtspr msscr0,r11 ; Set the MSSCR0
729 isync
730 sync
731 lwz r11,pfICTRL(r30) ; Get ICTRL
732 sync
733 mtspr ictrl,r11 ; Set the ICTRL
734 isync
735 sync
736 lwz r11,pfLDSTCR(r30) ; Get LDSTCR
737 sync
738 mtspr ldstcr,r11 ; Set the LDSTCR
739 isync
740 sync
741 lwz r11,pfLDSTDB(r30) ; Get LDSTDB
742 sync
743 mtspr ldstdb,r11 ; Set the LDSTDB
744 isync
745 sync
746 blr
747
748 ; 7450 - Specific
749
750 init7450:
751 bf firstBoot, init745X ; Not boot, use standard init
752
753 mfspr r13, pir ; Get BootConfig from PIR
754 rlwinm. r14, r13, 0, 20, 23 ; Is the pdet value zero
755 bne init7450done ; No, done for now
756
757 ori r13, r13, 0x0400 ; Force pdet value to 4
758 mtspr pir, r13 ; Write back the BootConfig
759
760 init7450done:
761 b init745X ; Continue with standard init
762
763
764 init970:
765 lis r20,8 ; Set up for 512K L2
766 init970x:
767 li r0,0 ; Clear this
768 mtspr hior,r0 ; Make sure that 0 is interrupt prefix
769 bf firstBoot,init970nb ; No init for wakeup or second processor....
770
771
772 ;
773 ; We can not query or change the L2 size. We will just
774 ; phoney up a L2CR to make sysctl "happy" and set the
775 ; L2 size to 512K.
776 ;
777
778 lis r0,0x8000 ; Synthesize a "valid" but non-existant L2CR
779 stw r0,pfl2crOriginal(r30) ; Set a dummy L2CR
780 stw r0,pfl2cr(r30) ; Set a dummy L2CR
781 stw r20,pfl2Size(r30) ; Set the L2 size
782
783 mfspr r11,hid0 ; Get original hid0
784 std r11,pfHID0(r30) ; Save original
785 mfspr r11,hid1 ; Get original hid1
786 std r11,pfHID1(r30) ; Save original
787 mfspr r11,hid4 ; Get original hid4
788 std r11,pfHID4(r30) ; Save original
789 mfspr r11,hid5 ; Get original hid5
790 std r11,pfHID5(r30) ; Save original
791
792 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
793 sldi r0, r0, 32 ; Shift to the top half
794 ld r11,pfHID0(r30) ; Load the hid0 value
795 andc r11, r11, r0 ; Clear the dnap bit
796 isync
797 mtspr hid0,r11 ; Stuff it
798 mfspr r11,hid0 ; Get it
799 mfspr r11,hid0 ; Get it
800 mfspr r11,hid0 ; Get it
801 mfspr r11,hid0 ; Get it
802 mfspr r11,hid0 ; Get it
803 mfspr r11,hid0 ; Get it
804 isync
805
806 lis r0,(pcfValid|pcfLarge|pcfDedSeg)<<8 ; Set the valid bit, dedicated segment, and large page flags
807 ori r0,r0,(24<<8)|24 ; Add in the 16M page size
808 stw r0,lgpPcfg+(pcfSize*pcfLargePcfg)(0) ; Set the 16M primary large page configuration entry
809
810 blr
811
812 ;
813 ; Start up code for second processor or wake up from sleep
814 ;
815
816 init970nb:
817 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
818 sldi r0, r0, 32 ; Shift to the top half
819 ld r11,pfHID0(r30) ; Load the hid0 value
820 andc r11, r11, r0 ; Clear the dnap bit
821 isync
822 mtspr hid0,r11 ; Stuff it
823 mfspr r11,hid0 ; Get it
824 mfspr r11,hid0 ; Get it
825 mfspr r11,hid0 ; Get it
826 mfspr r11,hid0 ; Get it
827 mfspr r11,hid0 ; Get it
828 mfspr r11,hid0 ; Get it
829 isync
830
831 ld r20,pfHID1(r30) ; Get it
832 isync
833 mtspr hid1,r20 ; Stick it
834 mtspr hid1,r20 ; Stick it again
835 isync
836
837 ld r11,pfHID4(r30) ; Get it
838 sync
839 mtspr hid4,r11 ; Stick it
840 isync
841
842 lis r11,0xE000 ; Get the unlikeliest ESID possible
843 srdi r11,r11,1 ; Make 0x7FFFFFFFF0000000
844 slbie r11 ; Make sure the ERAT is cleared
845
846 ld r11,pfHID5(r30) ; Get it
847 mtspr hid5,r11 ; Set it
848 isync
849 ;
850 ; May have changed dcbz mode so kill icache
851 ;
852
853 eqv r13,r13,r13 ; Get a constant -1
854 mr r14,r20 ; Save HID1
855 rldimi r14,r13,54,9 ; Set force icbi match mode
856
857 li r11,0 ; Set start if ICBI range
858 isync
859 mtspr hid1,r14 ; Stick it
860 mtspr hid1,r14 ; Stick it again
861 isync
862
863 inin970ki: icbi 0,r11 ; Kill I$
864 addi r11,r11,128 ; Next line
865 andis. r0,r11,1 ; Have we done them all?
866 beq++ inin970ki ; Not yet...
867
868 isync
869 mtspr hid1,r20 ; Stick it
870 mtspr hid1,r20 ; Stick it again
871 isync
872
873 blr ; Leave...
874
875
876
877 ; Unsupported Processors
878 initUnsupported:
879 mtlr r2 ; Restore the return address
880 blr ; Return to the booter
881
882
883 ;
884 ; Processor to feature table
885
886 ; .align 2 - Always on word boundary
887 ; .long ptFilter - Mask of significant bits in the Version/Revision code
888 ; - NOTE: Always order from most restrictive to least restrictive matching
889 ; .short ptVersion - Version code from PVR. Always start with 0 which is default
890 ; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific
891 ; .long ptFeatures - Available features
892 ; .long ptCPUCap - Default value for _cpu_capabilities
893 ; .long ptPwrModes - Available power management features
894 ; .long ptPatch - Patch features
895 ; .long ptInitRout - Initilization routine. Can modify any of the other attributes.
896 ; .long ptRptdProc - Processor type reported
897 ; .long ptLineSize - Level 1 cache line size
898 ; .long ptl1iSize - Level 1 instruction cache size
899 ; .long ptl1dSize - Level 1 data cache size
900 ; .long ptPTEG - Size of PTEG
901 ; .long ptMaxVAddr - Maximum effective address
902 ; .long ptMaxPAddr - Maximum physical address
903 ;
904
905 .align 2
906 processor_types:
907
908 ; 750CX (ver 2.x)
909
910 .align 2
911 .long 0xFFFF0F00 ; 2.x vers
912 .short PROCESSOR_VERSION_750
913 .short 0x0200
914 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
915 .long kCache32 | kHasGraphicsOps | kHasStfiwx
916 .long 0
917 .long PatchExt32
918 .long init750CX
919 .long CPU_SUBTYPE_POWERPC_750
920 .long 32
921 .long 32*1024
922 .long 32*1024
923 .long 64
924 .long 52
925 .long 32
926
927 ; 750 (generic)
928
929 .align 2
930 .long 0xFFFF0000 ; All revisions
931 .short PROCESSOR_VERSION_750
932 .short 0
933 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
934 .long kCache32 | kHasGraphicsOps | kHasStfiwx
935 .long 0
936 .long PatchExt32
937 .long init750
938 .long CPU_SUBTYPE_POWERPC_750
939 .long 32
940 .long 32*1024
941 .long 32*1024
942 .long 64
943 .long 52
944 .long 32
945
946 ; 750FX (ver 1.x)
947
948 .align 2
949 .long 0xFFFF0F00 ; 1.x vers
950 .short PROCESSOR_VERSION_750FX
951 .short 0x0100
952 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
953 .long kCache32 | kHasGraphicsOps | kHasStfiwx
954 .long pmDualPLL
955 .long PatchExt32
956 .long init750FX
957 .long CPU_SUBTYPE_POWERPC_750
958 .long 32
959 .long 32*1024
960 .long 32*1024
961 .long 64
962 .long 52
963 .long 32
964
965 ; 750FX (generic)
966
967 .align 2
968 .long 0xFFFF0000 ; All revisions
969 .short PROCESSOR_VERSION_750FX
970 .short 0
971 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
972 .long kCache32 | kHasGraphicsOps | kHasStfiwx
973 .long pmDualPLL | pmDPLLVmin
974 .long PatchExt32
975 .long init750FXV2
976 .long CPU_SUBTYPE_POWERPC_750
977 .long 32
978 .long 32*1024
979 .long 32*1024
980 .long 64
981 .long 52
982 .long 32
983
984 ; 7400 (ver 2.0 - ver 2.7)
985
986 .align 2
987 .long 0xFFFFFFF8 ; ver 2.0 - 2.7
988 .short PROCESSOR_VERSION_7400
989 .short 0x0200
990 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
991 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
992 .long 0
993 .long PatchExt32
994 .long init7400v2_7
995 .long CPU_SUBTYPE_POWERPC_7400
996 .long 32
997 .long 32*1024
998 .long 32*1024
999 .long 64
1000 .long 52
1001 .long 32
1002
1003 ; 7400 (generic)
1004
1005 .align 2
1006 .long 0xFFFF0000 ; All revisions
1007 .short PROCESSOR_VERSION_7400
1008 .short 0
1009 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1010 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1011 .long 0
1012 .long PatchExt32
1013 .long init7400
1014 .long CPU_SUBTYPE_POWERPC_7400
1015 .long 32
1016 .long 32*1024
1017 .long 32*1024
1018 .long 64
1019 .long 52
1020 .long 36
1021
1022 ; 7410 (ver 1.1)
1023
1024 .align 2
1025 .long 0xFFFFFFFF ; Exact match
1026 .short PROCESSOR_VERSION_7400
1027 .short 0x1101
1028 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1029 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1030 .long 0
1031 .long PatchExt32
1032 .long init7410
1033 .long CPU_SUBTYPE_POWERPC_7400
1034 .long 32
1035 .long 32*1024
1036 .long 32*1024
1037 .long 64
1038 .long 52
1039 .long 36
1040
1041 ; 7410 (generic)
1042
1043 .align 2
1044 .long 0xFFFF0000 ; All other revisions
1045 .short PROCESSOR_VERSION_7410
1046 .short 0
1047 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1048 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1049 .long 0
1050 .long PatchExt32
1051 .long init7410
1052 .long CPU_SUBTYPE_POWERPC_7400
1053 .long 32
1054 .long 32*1024
1055 .long 32*1024
1056 .long 64
1057 .long 52
1058 .long 36
1059
1060 ; 7450 (ver 1.xx)
1061
1062 .align 2
1063 .long 0xFFFFFF00 ; Just revisions 1.xx
1064 .short PROCESSOR_VERSION_7450
1065 .short 0x0100
1066 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1067 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1068 .long 0
1069 .long PatchExt32
1070 .long init7450
1071 .long CPU_SUBTYPE_POWERPC_7450
1072 .long 32
1073 .long 32*1024
1074 .long 32*1024
1075 .long 64
1076 .long 52
1077 .long 36
1078
1079 ; 7450 (2.0)
1080
1081 .align 2
1082 .long 0xFFFFFFFF ; Just revision 2.0
1083 .short PROCESSOR_VERSION_7450
1084 .short 0x0200
1085 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1086 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1087 .long 0
1088 .long PatchExt32
1089 .long init7450
1090 .long CPU_SUBTYPE_POWERPC_7450
1091 .long 32
1092 .long 32*1024
1093 .long 32*1024
1094 .long 64
1095 .long 52
1096 .long 36
1097
1098 ; 7450 (2.1)
1099
1100 .align 2
1101 .long 0xFFFF0000 ; All other revisions
1102 .short PROCESSOR_VERSION_7450
1103 .short 0
1104 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1105 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1106 .long 0
1107 .long PatchExt32
1108 .long init7450
1109 .long CPU_SUBTYPE_POWERPC_7450
1110 .long 32
1111 .long 32*1024
1112 .long 32*1024
1113 .long 64
1114 .long 52
1115 .long 36
1116
1117 ; 7455 (1.xx) Just like 7450 2.0
1118
1119 .align 2
1120 .long 0xFFFFFF00 ; Just revisions 1.xx
1121 .short PROCESSOR_VERSION_7455
1122 .short 0x0100
1123 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1124 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1125 .long 0
1126 .long PatchExt32
1127 .long init745X
1128 .long CPU_SUBTYPE_POWERPC_7450
1129 .long 32
1130 .long 32*1024
1131 .long 32*1024
1132 .long 64
1133 .long 52
1134 .long 36
1135
1136 ; 7455 (2.0)
1137
1138 .align 2
1139 .long 0xFFFFFFFF ; Just revision 2.0
1140 .short PROCESSOR_VERSION_7455
1141 .short 0x0200
1142 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1143 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1144 .long 0
1145 .long PatchExt32
1146 .long init745X
1147 .long CPU_SUBTYPE_POWERPC_7450
1148 .long 32
1149 .long 32*1024
1150 .long 32*1024
1151 .long 64
1152 .long 52
1153 .long 36
1154
1155 ; 7455 (2.1)
1156
1157 .align 2
1158 .long 0xFFFF0000 ; All other revisions
1159 .short PROCESSOR_VERSION_7455
1160 .short 0
1161 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1162 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1163 .long 0
1164 .long PatchExt32
1165 .long init745X
1166 .long CPU_SUBTYPE_POWERPC_7450
1167 .long 32
1168 .long 32*1024
1169 .long 32*1024
1170 .long 64
1171 .long 52
1172 .long 36
1173
1174 ; 7457
1175
1176 .align 2
1177 .long 0xFFFF0000 ; All revisions
1178 .short PROCESSOR_VERSION_7457
1179 .short 0
1180 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1181 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1182 .long 0
1183 .long PatchExt32
1184 .long init745X
1185 .long CPU_SUBTYPE_POWERPC_7450
1186 .long 32
1187 .long 32*1024
1188 .long 32*1024
1189 .long 64
1190 .long 52
1191 .long 36
1192
1193 ; 7447A
1194
1195 .align 2
1196 .long 0xFFFF0000 ; All revisions
1197 .short PROCESSOR_VERSION_7447A
1198 .short 0
1199 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1200 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1201 .long pmDFS
1202 .long PatchExt32
1203 .long init745X
1204 .long CPU_SUBTYPE_POWERPC_7450
1205 .long 32
1206 .long 32*1024
1207 .long 32*1024
1208 .long 64
1209 .long 52
1210 .long 36
1211
1212 ; 970
1213
1214 .align 2
1215 .long 0xFFFF0000 ; All versions so far
1216 .short PROCESSOR_VERSION_970
1217 .short 0
1218 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2 | pfSCOMFixUp
1219 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1220 .long 0
1221 .long PatchLwsync
1222 .long init970
1223 .long CPU_SUBTYPE_POWERPC_970
1224 .long 128
1225 .long 64*1024
1226 .long 32*1024
1227 .long 128
1228 .long 65
1229 .long 42
1230
1231 ; 970FX
1232
1233 .align 2
1234 .long 0xFFFF0000 ; All versions so far
1235 .short PROCESSOR_VERSION_970FX
1236 .short 0
1237 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2
1238 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1239 .long pmPowerTune
1240 .long PatchLwsync
1241 .long init970
1242 .long CPU_SUBTYPE_POWERPC_970
1243 .long 128
1244 .long 64*1024
1245 .long 32*1024
1246 .long 128
1247 .long 65
1248 .long 42
1249
1250
1251 ; All other processors are not supported
1252
1253 .align 2
1254 .long 0x00000000 ; Matches everything
1255 .short 0
1256 .short 0
1257 .long pfFloat | pf32Byte
1258 .long kCache32 | kHasGraphicsOps | kHasStfiwx
1259 .long 0
1260 .long PatchExt32
1261 .long initUnsupported
1262 .long CPU_SUBTYPE_POWERPC_ALL
1263 .long 32
1264 .long 32*1024
1265 .long 32*1024
1266 .long 64
1267 .long 52
1268 .long 32
1269
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