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[apple/xnu.git] / osfmk / chud / ppc / chud_cpu_ppc.c
1 /*
2 * Copyright (c) 2003-2007 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29 #include <mach/mach_types.h>
30 #include <mach/mach_host.h>
31
32 #include <kern/host.h>
33 #include <kern/processor.h>
34
35 #include <chud/chud_xnu.h>
36 #include <chud/ppc/chud_spr.h>
37 #include <chud/ppc/chud_cpu_asm.h>
38 #include <ppc/machine_routines.h>
39 #include <ppc/exception.h>
40 #include <ppc/hw_perfmon.h>
41 #include <ppc/Diagnostics.h>
42
43 // the macros in proc_reg.h fail with "expression must be absolute"
44
45 #undef mtsprg
46 #undef mfsprg
47 #define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
48 #define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
49
50 #undef mtspr
51 #undef mfspr
52 #define mtspr(spr, reg) __asm__ volatile ("mtspr %0, %1" : : "n" (spr), "r" (reg))
53 #define mfspr(reg, spr) __asm__ volatile("mfspr %0, %1" : "=r" (reg) : "n" (spr));
54
55 #undef mtsr
56 #undef mfsr
57 #define mtsr(sr, reg) __asm__ volatile("sync" "@" "mtsr sr%0, %1 " "@" "isync" : : "i" (sr), "r" (reg));
58 #define mfsr(reg, sr) __asm__ volatile("mfsr %0, sr%1" : "=r" (reg) : "i" (sr));
59
60 #if 0
61 #pragma mark **** cpu enable/disable ****
62 #endif
63
64 extern kern_return_t processor_start(processor_t processor); // osfmk/kern/processor.c
65 extern kern_return_t processor_exit(processor_t processor); // osfmk/kern/processor.c
66
67 __private_extern__
68 kern_return_t chudxnu_enable_cpu(int cpu, boolean_t enable)
69 {
70 chudxnu_unbind_thread(current_thread(), 0);
71
72 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
73 return KERN_FAILURE;
74 }
75
76 if((PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL)
77 && cpu != master_cpu) {
78 processor_t processor = cpu_to_processor(cpu);
79
80 if(enable) {
81 return processor_start(processor);
82 } else {
83 return processor_exit(processor);
84 }
85 }
86 return KERN_FAILURE;
87 }
88
89 #if 0
90 #pragma mark **** nap ****
91 #endif
92
93 __private_extern__
94 kern_return_t chudxnu_enable_cpu_nap(int cpu, boolean_t enable)
95 {
96 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
97 return KERN_FAILURE;
98 }
99
100 if(PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL) {
101 ml_enable_nap(cpu, enable);
102 return KERN_SUCCESS;
103 }
104
105 return KERN_FAILURE;
106 }
107
108 __private_extern__
109 boolean_t chudxnu_cpu_nap_enabled(int cpu)
110 {
111 boolean_t prev;
112
113 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
114 cpu = 0;
115 }
116
117 prev = ml_enable_nap(cpu, TRUE);
118 ml_enable_nap(cpu, prev);
119
120 return prev;
121 }
122
123 #if 0
124 #pragma mark **** shadowed spr ****
125 #endif
126
127 __private_extern__
128 kern_return_t chudxnu_set_shadowed_spr(int cpu, int spr, uint32_t val)
129 {
130 cpu_subtype_t target_cpu_subtype;
131 uint32_t available;
132 kern_return_t retval = KERN_FAILURE;
133 struct per_proc_info *per_proc;
134 boolean_t didBind = FALSE;
135
136 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
137 return KERN_FAILURE;
138 }
139
140 if(cpu<0) { // cpu<0 means don't bind (current cpu)
141 cpu = chudxnu_cpu_number();
142 didBind = FALSE;
143 } else {
144 chudxnu_bind_thread(current_thread(), cpu, 0);
145 didBind = TRUE;
146 }
147
148 per_proc = PerProcTable[cpu].ppe_vaddr;
149 available = per_proc->pf.Available;
150 target_cpu_subtype = per_proc->cpu_subtype;
151
152 if(spr==chud_750_l2cr) {
153 switch(target_cpu_subtype) {
154 case CPU_SUBTYPE_POWERPC_750:
155 case CPU_SUBTYPE_POWERPC_7400:
156 case CPU_SUBTYPE_POWERPC_7450:
157 if(available & pfL2) {
158 // int enable = (val & 0x80000000) ? TRUE : FALSE;
159 // if(enable) {
160 // per_proc->pf.l2cr = val;
161 // } else {
162 // per_proc->pf.l2cr = 0;
163 // }
164 per_proc->pf.l2cr = val;
165 cacheInit();
166 // mtspr(l2cr, per_proc->pf.l2cr); // XXXXXXX why is this necessary? XXXXXXX
167 retval = KERN_SUCCESS;
168 } else {
169 retval = KERN_FAILURE;
170 }
171 break;
172 default:
173 retval = KERN_INVALID_ARGUMENT;
174 break;
175 }
176 }
177 else if(spr==chud_7450_l3cr) {
178 switch(target_cpu_subtype) {
179 case CPU_SUBTYPE_POWERPC_7450:
180 if(available & pfL3) {
181 int enable = (val & 0x80000000) ? TRUE : FALSE;
182 if(enable) {
183 per_proc->pf.l3cr = val;
184 } else {
185 per_proc->pf.l3cr = 0;
186 }
187 cacheInit();
188 retval = KERN_SUCCESS;
189 } else {
190 retval = KERN_FAILURE;
191 }
192 break;
193 default:
194 retval = KERN_INVALID_ARGUMENT;
195 break;
196 }
197 }
198 else if(spr==chud_750_hid0) {
199 switch(target_cpu_subtype) {
200 case CPU_SUBTYPE_POWERPC_750:
201 cacheInit();
202 cacheDisable(); /* disable caches */
203 mtspr(chud_750_hid0, val);
204 per_proc->pf.pfHID0 = val;
205 cacheInit(); /* reenable caches */
206 retval = KERN_SUCCESS;
207 break;
208 case CPU_SUBTYPE_POWERPC_7400:
209 case CPU_SUBTYPE_POWERPC_7450:
210 mtspr(chud_750_hid0, val);
211 per_proc->pf.pfHID0 = val;
212 retval = KERN_SUCCESS;
213 break;
214 default:
215 retval = KERN_INVALID_ARGUMENT;
216 break;
217 }
218 }
219 else if(spr==chud_750_hid1) {
220 switch(target_cpu_subtype) {
221 case CPU_SUBTYPE_POWERPC_750:
222 case CPU_SUBTYPE_POWERPC_7400:
223 case CPU_SUBTYPE_POWERPC_7450:
224 mtspr(chud_750_hid1, val);
225 per_proc->pf.pfHID1 = val;
226 retval = KERN_SUCCESS;
227 break;
228 default:
229 retval = KERN_INVALID_ARGUMENT;
230 break;
231 }
232 }
233 else if(spr==chud_750fx_hid2 && target_cpu_subtype==CPU_SUBTYPE_POWERPC_750) {
234 mtspr(chud_750fx_hid2, val);
235 per_proc->pf.pfHID2 = val;
236 retval = KERN_SUCCESS;
237 }
238 else if(spr==chud_7400_msscr0 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) {
239 mtspr(chud_7400_msscr0, val);
240 per_proc->pf.pfMSSCR0 = val;
241 retval = KERN_SUCCESS;
242 }
243 else if(spr==chud_7400_msscr1 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) { // called msssr0 on 7450
244 mtspr(chud_7400_msscr1, val);
245 per_proc->pf.pfMSSCR1 = val;
246 retval = KERN_SUCCESS;
247 }
248 else if(spr==chud_7450_ldstcr && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
249 mtspr(chud_7450_ldstcr, val);
250 per_proc->pf.pfLDSTCR = val;
251 retval = KERN_SUCCESS;
252 }
253 else if(spr==chud_7450_ictrl && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
254 mtspr(chud_7450_ictrl, val);
255 per_proc->pf.pfICTRL = val;
256 retval = KERN_SUCCESS;
257 } else {
258 retval = KERN_INVALID_ARGUMENT;
259 }
260
261 if(didBind) {
262 chudxnu_unbind_thread(current_thread(), 0);
263 }
264
265 return retval;
266 }
267
268 __private_extern__
269 kern_return_t chudxnu_set_shadowed_spr64(int cpu, int spr, uint64_t val)
270 {
271 cpu_subtype_t target_cpu_subtype;
272 kern_return_t retval = KERN_FAILURE;
273 struct per_proc_info *per_proc;
274 boolean_t didBind = FALSE;
275
276 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
277 return KERN_FAILURE;
278 }
279
280 if(cpu<0) { // cpu<0 means don't bind (current cpu)
281 cpu = chudxnu_cpu_number();
282 didBind = FALSE;
283 } else {
284 chudxnu_bind_thread(current_thread(), cpu, 0);
285 didBind = TRUE;
286 }
287
288 per_proc = PerProcTable[cpu].ppe_vaddr;
289 target_cpu_subtype = per_proc->cpu_subtype;
290
291 if(spr==chud_970_hid0) {
292 switch(target_cpu_subtype) {
293 case CPU_SUBTYPE_POWERPC_970:
294 mtspr64(chud_970_hid0, &val);
295 per_proc->pf.pfHID0 = val;
296 retval = KERN_SUCCESS;
297 break;
298 default:
299 retval = KERN_INVALID_ARGUMENT;
300 break;
301 }
302 }
303 else if(spr==chud_970_hid1) {
304 switch(target_cpu_subtype) {
305 case CPU_SUBTYPE_POWERPC_970:
306 mtspr64(chud_970_hid1, &val);
307 per_proc->pf.pfHID1 = val;
308 retval = KERN_SUCCESS;
309 break;
310 default:
311 retval = KERN_INVALID_ARGUMENT;
312 break;
313 }
314 }
315 else if(spr==chud_970_hid4) {
316 switch(target_cpu_subtype) {
317 case CPU_SUBTYPE_POWERPC_970:
318 mtspr64(chud_970_hid4, &val);
319 per_proc->pf.pfHID4 = val;
320 retval = KERN_SUCCESS;
321 break;
322 default:
323 retval = KERN_INVALID_ARGUMENT;
324 break;
325 }
326 }
327 else if(spr==chud_970_hid5) {
328 switch(target_cpu_subtype) {
329 case CPU_SUBTYPE_POWERPC_970:
330 mtspr64(chud_970_hid5, &val);
331 per_proc->pf.pfHID5 = val;
332 retval = KERN_SUCCESS;
333 break;
334 default:
335 retval = KERN_INVALID_ARGUMENT;
336 break;
337 }
338 } else {
339 retval = KERN_INVALID_ARGUMENT;
340 }
341
342 if(didBind) {
343 chudxnu_unbind_thread(current_thread(), 0);
344 }
345
346 return retval;
347 }
348
349 __private_extern__
350 uint32_t chudxnu_get_orig_cpu_l2cr(int cpu)
351 {
352 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
353 cpu = 0;
354 }
355 return PerProcTable[cpu].ppe_vaddr->pf.l2crOriginal;
356 }
357
358 __private_extern__
359 uint32_t chudxnu_get_orig_cpu_l3cr(int cpu)
360 {
361 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
362 cpu = 0;
363 }
364 return PerProcTable[cpu].ppe_vaddr->pf.l3crOriginal;
365 }
366
367 #if 0
368 #pragma mark **** spr ****
369 #endif
370
371 __private_extern__
372 kern_return_t chudxnu_read_spr(int cpu, int spr, uint32_t *val_p)
373 {
374 kern_return_t retval = KERN_SUCCESS;
375 boolean_t oldlevel;
376 uint32_t val = 0xFFFFFFFF;
377
378 /* bind to requested CPU */
379 if(cpu>=0 && !(ml_at_interrupt_context() && cpu_number() == cpu)) { // cpu<0 means don't bind
380 if(chudxnu_bind_thread(current_thread(), cpu, 0)!=KERN_SUCCESS) {
381 return KERN_INVALID_ARGUMENT;
382 }
383 }
384
385 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
386
387 do {
388 /* PPC SPRs - 32-bit and 64-bit implementations */
389 if(spr==chud_ppc_srr0) { mfspr(val, chud_ppc_srr0); break; }
390 if(spr==chud_ppc_srr1) { mfspr(val, chud_ppc_srr1); break; }
391 if(spr==chud_ppc_dsisr) { mfspr(val, chud_ppc_dsisr); break; }
392 if(spr==chud_ppc_dar) { mfspr(val, chud_ppc_dar); break; }
393 if(spr==chud_ppc_dec) { mfspr(val, chud_ppc_dec); break; }
394 if(spr==chud_ppc_sdr1) { mfspr(val, chud_ppc_sdr1); break; }
395 if(spr==chud_ppc_sprg0) { mfspr(val, chud_ppc_sprg0); break; }
396 if(spr==chud_ppc_sprg1) { mfspr(val, chud_ppc_sprg1); break; }
397 if(spr==chud_ppc_sprg2) { mfspr(val, chud_ppc_sprg2); break; }
398 if(spr==chud_ppc_sprg3) { mfspr(val, chud_ppc_sprg3); break; }
399 if(spr==chud_ppc_ear) { mfspr(val, chud_ppc_ear); break; }
400 if(spr==chud_ppc_tbl) { mfspr(val, 268); break; } /* timebase consists of read registers and write registers */
401 if(spr==chud_ppc_tbu) { mfspr(val, 269); break; }
402 if(spr==chud_ppc_pvr) { mfspr(val, chud_ppc_pvr); break; }
403 if(spr==chud_ppc_ibat0u) { mfspr(val, chud_ppc_ibat0u); break; }
404 if(spr==chud_ppc_ibat0l) { mfspr(val, chud_ppc_ibat0l); break; }
405 if(spr==chud_ppc_ibat1u) { mfspr(val, chud_ppc_ibat1u); break; }
406 if(spr==chud_ppc_ibat1l) { mfspr(val, chud_ppc_ibat1l); break; }
407 if(spr==chud_ppc_ibat2u) { mfspr(val, chud_ppc_ibat2u); break; }
408 if(spr==chud_ppc_ibat2l) { mfspr(val, chud_ppc_ibat2l); break; }
409 if(spr==chud_ppc_ibat3u) { mfspr(val, chud_ppc_ibat3u); break; }
410 if(spr==chud_ppc_ibat3l) { mfspr(val, chud_ppc_ibat3l); break; }
411 if(spr==chud_ppc_dbat0u) { mfspr(val, chud_ppc_dbat0u); break; }
412 if(spr==chud_ppc_dbat0l) { mfspr(val, chud_ppc_dbat0l); break; }
413 if(spr==chud_ppc_dbat1u) { mfspr(val, chud_ppc_dbat1u); break; }
414 if(spr==chud_ppc_dbat1l) { mfspr(val, chud_ppc_dbat1l); break; }
415 if(spr==chud_ppc_dbat2u) { mfspr(val, chud_ppc_dbat2u); break; }
416 if(spr==chud_ppc_dbat2l) { mfspr(val, chud_ppc_dbat2l); break; }
417 if(spr==chud_ppc_dbat3u) { mfspr(val, chud_ppc_dbat3u); break; }
418 if(spr==chud_ppc_dbat3l) { mfspr(val, chud_ppc_dbat3l); break; }
419 if(spr==chud_ppc_dabr) { mfspr(val, chud_ppc_dabr); break; }
420 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
421 struct ppc_thread_state64 state;
422 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
423 kern_return_t kr;
424 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
425 if(KERN_SUCCESS==kr) {
426 val = state.srr1;
427 } else {
428 retval = KERN_FAILURE;
429 }
430 break;
431 }
432
433 /* PPC SPRs - 32-bit implementations */
434 if(spr==chud_ppc32_sr0) { mfsr(val, 0); break; }
435 if(spr==chud_ppc32_sr1) { mfsr(val, 1); break; }
436 if(spr==chud_ppc32_sr2) { mfsr(val, 2); break; }
437 if(spr==chud_ppc32_sr3) { mfsr(val, 3); break; }
438 if(spr==chud_ppc32_sr4) { mfsr(val, 4); break; }
439 if(spr==chud_ppc32_sr5) { mfsr(val, 5); break; }
440 if(spr==chud_ppc32_sr6) { mfsr(val, 6); break; }
441 if(spr==chud_ppc32_sr7) { mfsr(val, 7); break; }
442 if(spr==chud_ppc32_sr8) { mfsr(val, 8); break; }
443 if(spr==chud_ppc32_sr9) { mfsr(val, 9); break; }
444 if(spr==chud_ppc32_sr10) { mfsr(val, 10); break; }
445 if(spr==chud_ppc32_sr11) { mfsr(val, 11); break; }
446 if(spr==chud_ppc32_sr12) { mfsr(val, 12); break; }
447 if(spr==chud_ppc32_sr13) { mfsr(val, 13); break; }
448 if(spr==chud_ppc32_sr14) { mfsr(val, 14); break; }
449 if(spr==chud_ppc32_sr15) { mfsr(val, 15); break; }
450
451 /* PPC SPRs - 64-bit implementations */
452 if(spr==chud_ppc64_ctrl) { mfspr(val, chud_ppc64_ctrl); break; }
453
454 /* Implementation Specific SPRs */
455 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
456 if(spr==chud_750_mmcr0) { mfspr(val, chud_750_mmcr0); break; }
457 if(spr==chud_750_pmc1) { mfspr(val, chud_750_pmc1); break; }
458 if(spr==chud_750_pmc2) { mfspr(val, chud_750_pmc2); break; }
459 if(spr==chud_750_sia) { mfspr(val, chud_750_sia); break; }
460 if(spr==chud_750_mmcr1) { mfspr(val, chud_750_mmcr1); break; }
461 if(spr==chud_750_pmc3) { mfspr(val, chud_750_pmc3); break; }
462 if(spr==chud_750_pmc4) { mfspr(val, chud_750_pmc4); break; }
463 if(spr==chud_750_hid0) { mfspr(val, chud_750_hid0); break; }
464 if(spr==chud_750_hid1) { mfspr(val, chud_750_hid1); break; }
465 if(spr==chud_750_iabr) { mfspr(val, chud_750_iabr); break; }
466 if(spr==chud_750_ictc) { mfspr(val, chud_750_ictc); break; }
467 if(spr==chud_750_thrm1) { mfspr(val, chud_750_thrm1); break; }
468 if(spr==chud_750_thrm2) { mfspr(val, chud_750_thrm2); break; }
469 if(spr==chud_750_thrm3) { mfspr(val, chud_750_thrm3); break; }
470 if(spr==chud_750_l2cr) { mfspr(val, chud_750_l2cr); break; }
471
472 // 750FX only
473 if(spr==chud_750fx_ibat4u) { mfspr(val, chud_750fx_ibat4u); break; }
474 if(spr==chud_750fx_ibat4l) { mfspr(val, chud_750fx_ibat4l); break; }
475 if(spr==chud_750fx_ibat5u) { mfspr(val, chud_750fx_ibat5u); break; }
476 if(spr==chud_750fx_ibat5l) { mfspr(val, chud_750fx_ibat5l); break; }
477 if(spr==chud_750fx_ibat6u) { mfspr(val, chud_750fx_ibat6u); break; }
478 if(spr==chud_750fx_ibat6l) { mfspr(val, chud_750fx_ibat6l); break; }
479 if(spr==chud_750fx_ibat7u) { mfspr(val, chud_750fx_ibat7u); break; }
480 if(spr==chud_750fx_ibat7l) { mfspr(val, chud_750fx_ibat7l); break; }
481 if(spr==chud_750fx_dbat4u) { mfspr(val, chud_750fx_dbat4u); break; }
482 if(spr==chud_750fx_dbat4l) { mfspr(val, chud_750fx_dbat4l); break; }
483 if(spr==chud_750fx_dbat5u) { mfspr(val, chud_750fx_dbat5u); break; }
484 if(spr==chud_750fx_dbat5l) { mfspr(val, chud_750fx_dbat5l); break; }
485 if(spr==chud_750fx_dbat6u) { mfspr(val, chud_750fx_dbat6u); break; }
486 if(spr==chud_750fx_dbat6l) { mfspr(val, chud_750fx_dbat6l); break; }
487 if(spr==chud_750fx_dbat7u) { mfspr(val, chud_750fx_dbat7u); break; }
488 if(spr==chud_750fx_dbat7l) { mfspr(val, chud_750fx_dbat7l); break; }
489
490 // 750FX >= DDR2.x only
491 if(spr==chud_750fx_hid2) { mfspr(val, chud_750fx_hid2); break; }
492 }
493
494 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
495 if(spr==chud_7400_mmcr2) { mfspr(val, chud_7400_mmcr2); break; }
496 if(spr==chud_7400_bamr) { mfspr(val, chud_7400_bamr); break; }
497 if(spr==chud_7400_mmcr0) { mfspr(val, chud_7400_mmcr0); break; }
498 if(spr==chud_7400_pmc1) { mfspr(val, chud_7400_pmc1); break; }
499 if(spr==chud_7400_pmc2) { mfspr(val, chud_7400_pmc2); break; }
500 if(spr==chud_7400_siar) { mfspr(val, chud_7400_siar); break; }
501 if(spr==chud_7400_mmcr1) { mfspr(val, chud_7400_mmcr1); break; }
502 if(spr==chud_7400_pmc3) { mfspr(val, chud_7400_pmc3); break; }
503 if(spr==chud_7400_pmc4) { mfspr(val, chud_7400_pmc4); break; }
504 if(spr==chud_7400_hid0) { mfspr(val, chud_7400_hid0); break; }
505 if(spr==chud_7400_hid1) { mfspr(val, chud_7400_hid1); break; }
506 if(spr==chud_7400_iabr) { mfspr(val, chud_7400_iabr); break; }
507 if(spr==chud_7400_msscr0) { mfspr(val, chud_7400_msscr0); break; }
508 if(spr==chud_7400_msscr1) { mfspr(val, chud_7400_msscr1); break; } /* private */
509 if(spr==chud_7400_ictc) { mfspr(val, chud_7400_ictc); break; }
510 if(spr==chud_7400_thrm1) { mfspr(val, chud_7400_thrm1); break; }
511 if(spr==chud_7400_thrm2) { mfspr(val, chud_7400_thrm2); break; }
512 if(spr==chud_7400_thrm3) { mfspr(val, chud_7400_thrm3); break; }
513 if(spr==chud_7400_pir) { mfspr(val, chud_7400_pir); break; }
514 if(spr==chud_7400_l2cr) { mfspr(val, chud_7400_l2cr); break; }
515
516 // 7410 only
517 if(spr==chud_7410_l2pmcr) { mfspr(val, chud_7410_l2pmcr); break; }
518 }
519
520 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
521 if(spr==chud_7450_mmcr2) { mfspr(val, chud_7450_mmcr2); break; }
522 if(spr==chud_7450_pmc5) { mfspr(val, chud_7450_pmc5); break; }
523 if(spr==chud_7450_pmc6) { mfspr(val, chud_7450_pmc6); break; }
524 if(spr==chud_7450_bamr) { mfspr(val, chud_7450_bamr); break; }
525 if(spr==chud_7450_mmcr0) { mfspr(val, chud_7450_mmcr0); break; }
526 if(spr==chud_7450_pmc1) { mfspr(val, chud_7450_pmc1); break; }
527 if(spr==chud_7450_pmc2) { mfspr(val, chud_7450_pmc2); break; }
528 if(spr==chud_7450_siar) { mfspr(val, chud_7450_siar); break; }
529 if(spr==chud_7450_mmcr1) { mfspr(val, chud_7450_mmcr1); break; }
530 if(spr==chud_7450_pmc3) { mfspr(val, chud_7450_pmc3); break; }
531 if(spr==chud_7450_pmc4) { mfspr(val, chud_7450_pmc4); break; }
532 if(spr==chud_7450_tlbmiss) { mfspr(val, chud_7450_tlbmiss); break; }
533 if(spr==chud_7450_ptehi) { mfspr(val, chud_7450_ptehi); break; }
534 if(spr==chud_7450_ptelo) { mfspr(val, chud_7450_ptelo); break; }
535 if(spr==chud_7450_l3pm) { mfspr(val, chud_7450_l3pm); break; }
536 if(spr==chud_7450_hid0) { mfspr(val, chud_7450_hid0); break; }
537 if(spr==chud_7450_hid1) { mfspr(val, chud_7450_hid1); break; }
538 if(spr==chud_7450_iabr) { mfspr(val, chud_7450_iabr); break; }
539 if(spr==chud_7450_ldstdb) { mfspr(val, chud_7450_ldstdb); break; }
540 if(spr==chud_7450_msscr0) { mfspr(val, chud_7450_msscr0); break; }
541 if(spr==chud_7450_msssr0) { mfspr(val, chud_7450_msssr0); break; }
542 if(spr==chud_7450_ldstcr) { mfspr(val, chud_7450_ldstcr); break; }
543 if(spr==chud_7450_ictc) { mfspr(val, chud_7450_ictc); break; }
544 if(spr==chud_7450_ictrl) { mfspr(val, chud_7450_ictrl); break; }
545 if(spr==chud_7450_thrm1) { mfspr(val, chud_7450_thrm1); break; }
546 if(spr==chud_7450_thrm2) { mfspr(val, chud_7450_thrm2); break; }
547 if(spr==chud_7450_thrm3) { mfspr(val, chud_7450_thrm3); break; }
548 if(spr==chud_7450_pir) { mfspr(val, chud_7450_pir); break; }
549 if(spr==chud_7450_l2cr) { mfspr(val, chud_7450_l2cr); break; }
550 if(spr==chud_7450_l3cr) { mfspr(val, chud_7450_l3cr); break; }
551
552 // 7455/7457 only
553 if(spr==chud_7455_sprg4) { mfspr(val, chud_7455_sprg4); break; }
554 if(spr==chud_7455_sprg5) { mfspr(val, chud_7455_sprg5); break; }
555 if(spr==chud_7455_sprg6) { mfspr(val, chud_7455_sprg6); break; }
556 if(spr==chud_7455_sprg7) { mfspr(val, chud_7455_sprg7); break; }
557 if(spr==chud_7455_ibat4u) { mfspr(val, chud_7455_ibat4u); break; }
558 if(spr==chud_7455_ibat4l) { mfspr(val, chud_7455_ibat4l); break; }
559 if(spr==chud_7455_ibat5u) { mfspr(val, chud_7455_ibat5u); break; }
560 if(spr==chud_7455_ibat5l) { mfspr(val, chud_7455_ibat5l); break; }
561 if(spr==chud_7455_ibat6u) { mfspr(val, chud_7455_ibat6u); break; }
562 if(spr==chud_7455_ibat6l) { mfspr(val, chud_7455_ibat6l); break; }
563 if(spr==chud_7455_ibat7u) { mfspr(val, chud_7455_ibat7u); break; }
564 if(spr==chud_7455_ibat7l) { mfspr(val, chud_7455_ibat7l); break; }
565 if(spr==chud_7455_dbat4u) { mfspr(val, chud_7455_dbat4u); break; }
566 if(spr==chud_7455_dbat4l) { mfspr(val, chud_7455_dbat4l); break; }
567 if(spr==chud_7455_dbat5u) { mfspr(val, chud_7455_dbat5u); break; }
568 if(spr==chud_7455_dbat5l) { mfspr(val, chud_7455_dbat5l); break; }
569 if(spr==chud_7455_dbat6u) { mfspr(val, chud_7455_dbat6u); break; }
570 if(spr==chud_7455_dbat6l) { mfspr(val, chud_7455_dbat6l); break; }
571 if(spr==chud_7455_dbat7u) { mfspr(val, chud_7455_dbat7u); break; }
572 if(spr==chud_7455_dbat7l) { mfspr(val, chud_7455_dbat7l); break; }
573 }
574
575 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
576 if(spr==chud_970_pir) { mfspr(val, chud_970_pir); break; }
577 if(spr==chud_970_pmc1) { mfspr(val, chud_970_pmc1); break; }
578 if(spr==chud_970_pmc2) { mfspr(val, chud_970_pmc2); break; }
579 if(spr==chud_970_pmc3) { mfspr(val, chud_970_pmc3); break; }
580 if(spr==chud_970_pmc4) { mfspr(val, chud_970_pmc4); break; }
581 if(spr==chud_970_pmc5) { mfspr(val, chud_970_pmc5); break; }
582 if(spr==chud_970_pmc6) { mfspr(val, chud_970_pmc6); break; }
583 if(spr==chud_970_pmc7) { mfspr(val, chud_970_pmc7); break; }
584 if(spr==chud_970_pmc8) { mfspr(val, chud_970_pmc8); break; }
585 if(spr==chud_970_hdec) { mfspr(val, chud_970_hdec); break; }
586 }
587
588 /* we only get here if none of the above cases qualify */
589 retval = KERN_INVALID_ARGUMENT;
590 } while(0);
591
592 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
593
594 if(cpu>=0) { // cpu<0 means don't bind
595 chudxnu_unbind_thread(current_thread(), 0);
596 }
597
598 *val_p = val;
599
600 return retval;
601 }
602
603 __private_extern__
604 kern_return_t chudxnu_read_spr64(int cpu, int spr, uint64_t *val_p)
605 {
606 kern_return_t retval = KERN_SUCCESS;
607 boolean_t oldlevel;
608
609 /* bind to requested CPU */
610 if(cpu>=0 && !(ml_at_interrupt_context() && cpu_number() == cpu)) { // cpu<0 means don't bind
611 if(chudxnu_bind_thread(current_thread(), cpu, 0)!=KERN_SUCCESS) {
612 return KERN_INVALID_ARGUMENT;
613 }
614 }
615
616 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
617
618 do {
619 /* PPC SPRs - 32-bit and 64-bit implementations */
620 if(spr==chud_ppc_srr0) { retval = mfspr64(val_p, chud_ppc_srr0); break; }
621 if(spr==chud_ppc_srr1) { retval = mfspr64(val_p, chud_ppc_srr1); break; }
622 if(spr==chud_ppc_dar) { retval = mfspr64(val_p, chud_ppc_dar); break; }
623 if(spr==chud_ppc_dsisr) { retval = mfspr64(val_p, chud_ppc_dsisr); break; }
624 if(spr==chud_ppc_sdr1) { retval = mfspr64(val_p, chud_ppc_sdr1); break; }
625 if(spr==chud_ppc_sprg0) { retval = mfspr64(val_p, chud_ppc_sprg0); break; }
626 if(spr==chud_ppc_sprg1) { retval = mfspr64(val_p, chud_ppc_sprg1); break; }
627 if(spr==chud_ppc_sprg2) { retval = mfspr64(val_p, chud_ppc_sprg2); break; }
628 if(spr==chud_ppc_sprg3) { retval = mfspr64(val_p, chud_ppc_sprg3); break; }
629 if(spr==chud_ppc_dabr) { retval = mfspr64(val_p, chud_ppc_dabr); break; }
630 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
631 struct ppc_thread_state64 state;
632 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
633 kern_return_t kr;
634 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
635 if(KERN_SUCCESS==kr) {
636 *val_p = state.srr1;
637 } else {
638 retval = KERN_FAILURE;
639 }
640 break;
641 }
642
643 /* PPC SPRs - 64-bit implementations */
644 if(spr==chud_ppc64_asr) { retval = mfspr64(val_p, chud_ppc64_asr); break; }
645 if(spr==chud_ppc64_accr) { retval = mfspr64(val_p, chud_ppc64_accr); break; }
646
647 /* Implementation Specific SPRs */
648 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
649 if(spr==chud_970_hid0) { retval = mfspr64(val_p, chud_970_hid0); break; }
650 if(spr==chud_970_hid1) { retval = mfspr64(val_p, chud_970_hid1); break; }
651 if(spr==chud_970_hid4) { retval = mfspr64(val_p, chud_970_hid4); break; }
652 if(spr==chud_970_hid5) { retval = mfspr64(val_p, chud_970_hid5); break; }
653 if(spr==chud_970_mmcr0) { retval = mfspr64(val_p, chud_970_mmcr0); break; }
654 if(spr==chud_970_mmcr1) { retval = mfspr64(val_p, chud_970_mmcr1); break; }
655 if(spr==chud_970_mmcra) { retval = mfspr64(val_p, chud_970_mmcra); break; }
656 if(spr==chud_970_siar) { retval = mfspr64(val_p, chud_970_siar); break; }
657 if(spr==chud_970_sdar) { retval = mfspr64(val_p, chud_970_sdar); break; }
658 if(spr==chud_970_imc) { retval = mfspr64(val_p, chud_970_imc); break; }
659 if(spr==chud_970_rmor) { retval = mfspr64(val_p, chud_970_rmor); break; }
660 if(spr==chud_970_hrmor) { retval = mfspr64(val_p, chud_970_hrmor); break; }
661 if(spr==chud_970_hior) { retval = mfspr64(val_p, chud_970_hior); break; }
662 if(spr==chud_970_lpidr) { retval = mfspr64(val_p, chud_970_lpidr); break; }
663 if(spr==chud_970_lpcr) { retval = mfspr64(val_p, chud_970_lpcr); break; }
664 if(spr==chud_970_dabrx) { retval = mfspr64(val_p, chud_970_dabrx); break; }
665 if(spr==chud_970_hsprg0) { retval = mfspr64(val_p, chud_970_hsprg0); break; }
666 if(spr==chud_970_hsprg1) { retval = mfspr64(val_p, chud_970_hsprg1); break; }
667 if(spr==chud_970_hsrr0) { retval = mfspr64(val_p, chud_970_hsrr0); break; }
668 if(spr==chud_970_hsrr1) { retval = mfspr64(val_p, chud_970_hsrr1); break; }
669 if(spr==chud_970_hdec) { retval = mfspr64(val_p, chud_970_hdec); break; }
670 if(spr==chud_970_trig0) { retval = mfspr64(val_p, chud_970_trig0); break; }
671 if(spr==chud_970_trig1) { retval = mfspr64(val_p, chud_970_trig1); break; }
672 if(spr==chud_970_trig2) { retval = mfspr64(val_p, chud_970_trig2); break; }
673 if(spr==chud_970_scomc) { retval = mfspr64(val_p, chud_970_scomc); break; }
674 if(spr==chud_970_scomd) { retval = mfspr64(val_p, chud_970_scomd); break; }
675 }
676
677 /* we only get here if none of the above cases qualify */
678 *val_p = 0xFFFFFFFFFFFFFFFFLL;
679 retval = KERN_INVALID_ARGUMENT;
680 } while(0);
681
682 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
683
684 if(cpu>=0) { // cpu<0 means don't bind
685 chudxnu_unbind_thread(current_thread(), 0);
686 }
687
688 return retval;
689 }
690
691 __private_extern__
692 kern_return_t chudxnu_write_spr(int cpu, int spr, uint32_t val)
693 {
694 kern_return_t retval = KERN_SUCCESS;
695 boolean_t oldlevel;
696
697 /* bind to requested CPU */
698 if(cpu>=0 && !(ml_at_interrupt_context() && cpu_number() == cpu)) { // cpu<0 means don't bind
699 if(chudxnu_bind_thread(current_thread(), cpu, 0)!=KERN_SUCCESS) {
700 return KERN_INVALID_ARGUMENT;
701 }
702 }
703
704 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
705
706 do {
707 /* PPC SPRs - 32-bit and 64-bit implementations */
708 if(spr==chud_ppc_srr0) { mtspr(chud_ppc_srr0, val); break; }
709 if(spr==chud_ppc_srr1) { mtspr(chud_ppc_srr1, val); break; }
710 if(spr==chud_ppc_dsisr) { mtspr(chud_ppc_dsisr, val); break; }
711 if(spr==chud_ppc_dar) { mtspr(chud_ppc_dar, val); break; }
712 if(spr==chud_ppc_dec) { mtspr(chud_ppc_dec, val); break; }
713 if(spr==chud_ppc_sdr1) { mtspr(chud_ppc_sdr1, val); break; }
714 if(spr==chud_ppc_sprg0) { mtspr(chud_ppc_sprg0, val); break; }
715 if(spr==chud_ppc_sprg1) { mtspr(chud_ppc_sprg1, val); break; }
716 if(spr==chud_ppc_sprg2) { mtspr(chud_ppc_sprg2, val); break; }
717 if(spr==chud_ppc_sprg3) { mtspr(chud_ppc_sprg3, val); break; }
718 if(spr==chud_ppc_ear) { mtspr(chud_ppc_ear, val); break; }
719 if(spr==chud_ppc_tbl) { mtspr(284, val); break; } /* timebase consists of read registers and write registers */
720 if(spr==chud_ppc_tbu) { mtspr(285, val); break; }
721 if(spr==chud_ppc_pvr) { mtspr(chud_ppc_pvr, val); break; }
722 if(spr==chud_ppc_ibat0u) { mtspr(chud_ppc_ibat0u, val); break; }
723 if(spr==chud_ppc_ibat0l) { mtspr(chud_ppc_ibat0l, val); break; }
724 if(spr==chud_ppc_ibat1u) { mtspr(chud_ppc_ibat1u, val); break; }
725 if(spr==chud_ppc_ibat1l) { mtspr(chud_ppc_ibat1l, val); break; }
726 if(spr==chud_ppc_ibat2u) { mtspr(chud_ppc_ibat2u, val); break; }
727 if(spr==chud_ppc_ibat2l) { mtspr(chud_ppc_ibat2l, val); break; }
728 if(spr==chud_ppc_ibat3u) { mtspr(chud_ppc_ibat3u, val); break; }
729 if(spr==chud_ppc_ibat3l) { mtspr(chud_ppc_ibat3l, val); break; }
730 if(spr==chud_ppc_dbat0u) { mtspr(chud_ppc_dbat0u, val); break; }
731 if(spr==chud_ppc_dbat0l) { mtspr(chud_ppc_dbat0l, val); break; }
732 if(spr==chud_ppc_dbat1u) { mtspr(chud_ppc_dbat1u, val); break; }
733 if(spr==chud_ppc_dbat1l) { mtspr(chud_ppc_dbat1l, val); break; }
734 if(spr==chud_ppc_dbat2u) { mtspr(chud_ppc_dbat2u, val); break; }
735 if(spr==chud_ppc_dbat2l) { mtspr(chud_ppc_dbat2l, val); break; }
736 if(spr==chud_ppc_dbat3u) { mtspr(chud_ppc_dbat3u, val); break; }
737 if(spr==chud_ppc_dbat3l) { mtspr(chud_ppc_dbat3l, val); break; }
738 if(spr==chud_ppc_dabr) { mtspr(chud_ppc_dabr, val); break; }
739 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
740 struct ppc_thread_state64 state;
741 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
742 kern_return_t kr;
743 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
744 if(KERN_SUCCESS==kr) {
745 state.srr1 = val;
746 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
747 if(KERN_SUCCESS!=kr) {
748 retval = KERN_FAILURE;
749 }
750 } else {
751 retval = KERN_FAILURE;
752 }
753 break;
754 }
755
756 /* PPC SPRs - 32-bit implementations */
757 if(spr==chud_ppc32_sr0) { mtsr(0, val); break; }
758 if(spr==chud_ppc32_sr1) { mtsr(1, val); break; }
759 if(spr==chud_ppc32_sr2) { mtsr(2, val); break; }
760 if(spr==chud_ppc32_sr3) { mtsr(3, val); break; }
761 if(spr==chud_ppc32_sr4) { mtsr(4, val); break; }
762 if(spr==chud_ppc32_sr5) { mtsr(5, val); break; }
763 if(spr==chud_ppc32_sr6) { mtsr(6, val); break; }
764 if(spr==chud_ppc32_sr7) { mtsr(7, val); break; }
765 if(spr==chud_ppc32_sr8) { mtsr(8, val); break; }
766 if(spr==chud_ppc32_sr9) { mtsr(9, val); break; }
767 if(spr==chud_ppc32_sr10) { mtsr(10, val); break; }
768 if(spr==chud_ppc32_sr11) { mtsr(11, val); break; }
769 if(spr==chud_ppc32_sr12) { mtsr(12, val); break; }
770 if(spr==chud_ppc32_sr13) { mtsr(13, val); break; }
771 if(spr==chud_ppc32_sr14) { mtsr(14, val); break; }
772 if(spr==chud_ppc32_sr15) { mtsr(15, val); break; }
773
774 /* Implementation Specific SPRs */
775 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
776 if(spr==chud_750_mmcr0) { mtspr(chud_750_mmcr0, val); break; }
777 if(spr==chud_750_pmc1) { mtspr(chud_750_pmc1, val); break; }
778 if(spr==chud_750_pmc2) { mtspr(chud_750_pmc2, val); break; }
779 if(spr==chud_750_sia) { mtspr(chud_750_sia, val); break; }
780 if(spr==chud_750_mmcr1) { mtspr(chud_750_mmcr1, val); break; }
781 if(spr==chud_750_pmc3) { mtspr(chud_750_pmc3, val); break; }
782 if(spr==chud_750_pmc4) { mtspr(chud_750_pmc4, val); break; }
783 if(spr==chud_750_iabr) { mtspr(chud_750_iabr, val); break; }
784 if(spr==chud_750_ictc) { mtspr(chud_750_ictc, val); break; }
785 if(spr==chud_750_thrm1) { mtspr(chud_750_thrm1, val); break; }
786 if(spr==chud_750_thrm2) { mtspr(chud_750_thrm2, val); break; }
787 if(spr==chud_750_thrm3) { mtspr(chud_750_thrm3, val); break; }
788 if(spr==chud_750_l2cr) {
789 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
790 break;
791 }
792 if(spr==chud_750_hid0) {
793 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
794 break;
795 }
796 if(spr==chud_750_hid1) {
797 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
798 break;
799 }
800
801 // 750FX only
802 if(spr==chud_750fx_ibat4u) { mtspr(chud_750fx_ibat4u, val); break; }
803 if(spr==chud_750fx_ibat4l) { mtspr(chud_750fx_ibat4l, val); break; }
804 if(spr==chud_750fx_ibat5u) { mtspr(chud_750fx_ibat5u, val); break; }
805 if(spr==chud_750fx_ibat5l) { mtspr(chud_750fx_ibat5l, val); break; }
806 if(spr==chud_750fx_ibat6u) { mtspr(chud_750fx_ibat6u, val); break; }
807 if(spr==chud_750fx_ibat6l) { mtspr(chud_750fx_ibat6l, val); break; }
808 if(spr==chud_750fx_ibat7u) { mtspr(chud_750fx_ibat7u, val); break; }
809 if(spr==chud_750fx_ibat7l) { mtspr(chud_750fx_ibat7l, val); break; }
810 if(spr==chud_750fx_dbat4u) { mtspr(chud_750fx_dbat4u, val); break; }
811 if(spr==chud_750fx_dbat4l) { mtspr(chud_750fx_dbat4l, val); break; }
812 if(spr==chud_750fx_dbat5u) { mtspr(chud_750fx_dbat5u, val); break; }
813 if(spr==chud_750fx_dbat5l) { mtspr(chud_750fx_dbat5l, val); break; }
814 if(spr==chud_750fx_dbat6u) { mtspr(chud_750fx_dbat6u, val); break; }
815 if(spr==chud_750fx_dbat6l) { mtspr(chud_750fx_dbat6l, val); break; }
816 if(spr==chud_750fx_dbat7u) { mtspr(chud_750fx_dbat7u, val); break; }
817 if(spr==chud_750fx_dbat7l) { mtspr(chud_750fx_dbat7l, val); break; }
818
819 // 750FX >= DDR2.x
820 if(spr==chud_750fx_hid2) { mtspr(chud_750fx_hid2, val); break; }
821 }
822
823 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
824 if(spr==chud_7400_mmcr2) { mtspr(chud_7400_mmcr2, val); break; }
825 if(spr==chud_7400_bamr) { mtspr(chud_7400_bamr, val); break; }
826 if(spr==chud_7400_mmcr0) { mtspr(chud_7400_mmcr0, val); break; }
827 if(spr==chud_7400_pmc1) { mtspr(chud_7400_pmc1, val); break; }
828 if(spr==chud_7400_pmc2) { mtspr(chud_7400_pmc2, val); break; }
829 if(spr==chud_7400_siar) { mtspr(chud_7400_siar, val); break; }
830 if(spr==chud_7400_mmcr1) { mtspr(chud_7400_mmcr1, val); break; }
831 if(spr==chud_7400_pmc3) { mtspr(chud_7400_pmc3, val); break; }
832 if(spr==chud_7400_pmc4) { mtspr(chud_7400_pmc4, val); break; }
833 if(spr==chud_7400_iabr) { mtspr(chud_7400_iabr, val); break; }
834 if(spr==chud_7400_ictc) { mtspr(chud_7400_ictc, val); break; }
835 if(spr==chud_7400_thrm1) { mtspr(chud_7400_thrm1, val); break; }
836 if(spr==chud_7400_thrm2) { mtspr(chud_7400_thrm2, val); break; }
837 if(spr==chud_7400_thrm3) { mtspr(chud_7400_thrm3, val); break; }
838 if(spr==chud_7400_pir) { mtspr(chud_7400_pir, val); break; }
839
840 if(spr==chud_7400_l2cr) {
841 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
842 break;
843 }
844 if(spr==chud_7400_hid0) {
845 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
846 break;
847 }
848 if(spr==chud_7400_hid1) {
849 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
850 break;
851 }
852 if(spr==chud_7400_msscr0) {
853 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
854 break;
855 }
856 if(spr==chud_7400_msscr1) { /* private */
857 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
858 break;
859 }
860
861 // 7410 only
862 if(spr==chud_7410_l2pmcr) { mtspr(chud_7410_l2pmcr, val); break; }
863 }
864
865 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
866 if(spr==chud_7450_mmcr2) { mtspr(chud_7450_mmcr2, val); break; }
867 if(spr==chud_7450_pmc5) { mtspr(chud_7450_pmc5, val); break; }
868 if(spr==chud_7450_pmc6) { mtspr(chud_7450_pmc6, val); break; }
869 if(spr==chud_7450_bamr) { mtspr(chud_7450_bamr, val); break; }
870 if(spr==chud_7450_mmcr0) { mtspr(chud_7450_mmcr0, val); break; }
871 if(spr==chud_7450_pmc1) { mtspr(chud_7450_pmc1, val); break; }
872 if(spr==chud_7450_pmc2) { mtspr(chud_7450_pmc2, val); break; }
873 if(spr==chud_7450_siar) { mtspr(chud_7450_siar, val); break; }
874 if(spr==chud_7450_mmcr1) { mtspr(chud_7450_mmcr1, val); break; }
875 if(spr==chud_7450_pmc3) { mtspr(chud_7450_pmc3, val); break; }
876 if(spr==chud_7450_pmc4) { mtspr(chud_7450_pmc4, val); break; }
877 if(spr==chud_7450_tlbmiss) { mtspr(chud_7450_tlbmiss, val); break; }
878 if(spr==chud_7450_ptehi) { mtspr(chud_7450_ptehi, val); break; }
879 if(spr==chud_7450_ptelo) { mtspr(chud_7450_ptelo, val); break; }
880 if(spr==chud_7450_l3pm) { mtspr(chud_7450_l3pm, val); break; }
881 if(spr==chud_7450_iabr) { mtspr(chud_7450_iabr, val); break; }
882 if(spr==chud_7450_ldstdb) { mtspr(chud_7450_ldstdb, val); break; }
883 if(spr==chud_7450_ictc) { mtspr(chud_7450_ictc, val); break; }
884 if(spr==chud_7450_thrm1) { mtspr(chud_7450_thrm1, val); break; }
885 if(spr==chud_7450_thrm2) { mtspr(chud_7450_thrm2, val); break; }
886 if(spr==chud_7450_thrm3) { mtspr(chud_7450_thrm3, val); break; }
887 if(spr==chud_7450_pir) { mtspr(chud_7450_pir, val); break; }
888
889 if(spr==chud_7450_l2cr) {
890 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
891 break;
892 }
893
894 if(spr==chud_7450_l3cr) {
895 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
896 break;
897 }
898 if(spr==chud_7450_ldstcr) {
899 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
900 break;
901 }
902 if(spr==chud_7450_hid0) {
903 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
904 break;
905 }
906 if(spr==chud_7450_hid1) {
907 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
908 break;
909 }
910 if(spr==chud_7450_msscr0) {
911 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
912 break;
913 }
914 if(spr==chud_7450_msssr0) {
915 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
916 break;
917 }
918 if(spr==chud_7450_ictrl) {
919 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
920 break;
921 }
922
923 // 7455/7457 only
924 if(spr==chud_7455_sprg4) { mtspr(chud_7455_sprg4, val); break; }
925 if(spr==chud_7455_sprg5) { mtspr(chud_7455_sprg5, val); break; }
926 if(spr==chud_7455_sprg6) { mtspr(chud_7455_sprg6, val); break; }
927 if(spr==chud_7455_sprg7) { mtspr(chud_7455_sprg7, val); break; }
928 if(spr==chud_7455_ibat4u) { mtspr(chud_7455_ibat4u, val); break; }
929 if(spr==chud_7455_ibat4l) { mtspr(chud_7455_ibat4l, val); break; }
930 if(spr==chud_7455_ibat5u) { mtspr(chud_7455_ibat5u, val); break; }
931 if(spr==chud_7455_ibat5l) { mtspr(chud_7455_ibat5l, val); break; }
932 if(spr==chud_7455_ibat6u) { mtspr(chud_7455_ibat6u, val); break; }
933 if(spr==chud_7455_ibat6l) { mtspr(chud_7455_ibat6l, val); break; }
934 if(spr==chud_7455_ibat7u) { mtspr(chud_7455_ibat7u, val); break; }
935 if(spr==chud_7455_ibat7l) { mtspr(chud_7455_ibat7l, val); break; }
936 if(spr==chud_7455_dbat4u) { mtspr(chud_7455_dbat4u, val); break; }
937 if(spr==chud_7455_dbat4l) { mtspr(chud_7455_dbat4l, val); break; }
938 if(spr==chud_7455_dbat5u) { mtspr(chud_7455_dbat5u, val); break; }
939 if(spr==chud_7455_dbat5l) { mtspr(chud_7455_dbat5l, val); break; }
940 if(spr==chud_7455_dbat6u) { mtspr(chud_7455_dbat6u, val); break; }
941 if(spr==chud_7455_dbat6l) { mtspr(chud_7455_dbat6l, val); break; }
942 if(spr==chud_7455_dbat7u) { mtspr(chud_7455_dbat7u, val); break; }
943 if(spr==chud_7455_dbat7l) { mtspr(chud_7455_dbat7l, val); break; }
944 }
945
946 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
947 if(spr==chud_970_pir) { mtspr(chud_970_pir, val); break; }
948 if(spr==chud_970_pmc1) { mtspr(chud_970_pmc1, val); break; }
949 if(spr==chud_970_pmc2) { mtspr(chud_970_pmc2, val); break; }
950 if(spr==chud_970_pmc3) { mtspr(chud_970_pmc3, val); break; }
951 if(spr==chud_970_pmc4) { mtspr(chud_970_pmc4, val); break; }
952 if(spr==chud_970_pmc5) { mtspr(chud_970_pmc5, val); break; }
953 if(spr==chud_970_pmc6) { mtspr(chud_970_pmc6, val); break; }
954 if(spr==chud_970_pmc7) { mtspr(chud_970_pmc7, val); break; }
955 if(spr==chud_970_pmc8) { mtspr(chud_970_pmc8, val); break; }
956 if(spr==chud_970_hdec) { mtspr(chud_970_hdec, val); break; }
957 }
958
959 /* we only get here if none of the above cases qualify */
960 retval = KERN_INVALID_ARGUMENT;
961 } while(0);
962
963 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
964
965 if(cpu>=0) { // cpu<0 means don't bind
966 chudxnu_unbind_thread(current_thread(), 0);
967 }
968
969 return retval;
970 }
971
972 __private_extern__
973 kern_return_t chudxnu_write_spr64(int cpu, int spr, uint64_t val)
974 {
975 kern_return_t retval = KERN_SUCCESS;
976 boolean_t oldlevel;
977 uint64_t *val_p = &val;
978
979 /* bind to requested CPU */
980 if(cpu>=0 && !(ml_at_interrupt_context() && cpu_number() == cpu)) { // cpu<0 means don't bind
981 if(chudxnu_bind_thread(current_thread(), cpu, 0)!=KERN_SUCCESS) {
982 return KERN_INVALID_ARGUMENT;
983 }
984 }
985
986 oldlevel = ml_set_interrupts_enabled(FALSE); /* disable interrupts */
987
988 do {
989 /* PPC SPRs - 32-bit and 64-bit implementations */
990 if(spr==chud_ppc_srr0) { retval = mtspr64(chud_ppc_srr0, val_p); break; }
991 if(spr==chud_ppc_srr1) { retval = mtspr64(chud_ppc_srr1, val_p); break; }
992 if(spr==chud_ppc_dar) { retval = mtspr64(chud_ppc_dar, val_p); break; }
993 if(spr==chud_ppc_dsisr) { retval = mtspr64(chud_ppc_dsisr, val_p); break; }
994 if(spr==chud_ppc_sdr1) { retval = mtspr64(chud_ppc_sdr1, val_p); break; }
995 if(spr==chud_ppc_sprg0) { retval = mtspr64(chud_ppc_sprg0, val_p); break; }
996 if(spr==chud_ppc_sprg1) { retval = mtspr64(chud_ppc_sprg1, val_p); break; }
997 if(spr==chud_ppc_sprg2) { retval = mtspr64(chud_ppc_sprg2, val_p); break; }
998 if(spr==chud_ppc_sprg3) { retval = mtspr64(chud_ppc_sprg3, val_p); break; }
999 if(spr==chud_ppc_dabr) { retval = mtspr64(chud_ppc_dabr, val_p); break; }
1000 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
1001 struct ppc_thread_state64 state;
1002 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
1003 kern_return_t kr;
1004 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
1005 if(KERN_SUCCESS==kr) {
1006 state.srr1 = val;
1007 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
1008 if(KERN_SUCCESS!=kr) {
1009 retval = KERN_FAILURE;
1010 }
1011 } else {
1012 retval = KERN_FAILURE;
1013 }
1014 break;
1015 }
1016
1017 /* PPC SPRs - 64-bit implementations */
1018 if(spr==chud_ppc64_asr) { retval = mtspr64(chud_ppc64_asr, val_p); break; }
1019 if(spr==chud_ppc64_accr) { retval = mtspr64(chud_ppc64_accr, val_p); break; }
1020 if(spr==chud_ppc64_ctrl) { retval = mtspr64(chud_ppc64_ctrl, val_p); break; }
1021
1022 /* Implementation Specific SPRs */
1023 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
1024 if(spr==chud_970_hid0) { retval = mtspr64(chud_970_hid0, val_p); break; }
1025 if(spr==chud_970_hid1) { retval = mtspr64(chud_970_hid1, val_p); break; }
1026 if(spr==chud_970_hid4) { retval = mtspr64(chud_970_hid4, val_p); break; }
1027 if(spr==chud_970_hid5) { retval = mtspr64(chud_970_hid5, val_p); break; }
1028 if(spr==chud_970_mmcr0) { retval = mtspr64(chud_970_mmcr0, val_p); break; }
1029 if(spr==chud_970_mmcr1) { retval = mtspr64(chud_970_mmcr1, val_p); break; }
1030 if(spr==chud_970_mmcra) { retval = mtspr64(chud_970_mmcra, val_p); break; }
1031 if(spr==chud_970_siar) { retval = mtspr64(chud_970_siar, val_p); break; }
1032 if(spr==chud_970_sdar) { retval = mtspr64(chud_970_sdar, val_p); break; }
1033 if(spr==chud_970_imc) { retval = mtspr64(chud_970_imc, val_p); break; }
1034
1035 if(spr==chud_970_rmor) { retval = mtspr64(chud_970_rmor, val_p); break; }
1036 if(spr==chud_970_hrmor) { retval = mtspr64(chud_970_hrmor, val_p); break; }
1037 if(spr==chud_970_hior) { retval = mtspr64(chud_970_hior, val_p); break; }
1038 if(spr==chud_970_lpidr) { retval = mtspr64(chud_970_lpidr, val_p); break; }
1039 if(spr==chud_970_lpcr) { retval = mtspr64(chud_970_lpcr, val_p); break; }
1040 if(spr==chud_970_dabrx) { retval = mtspr64(chud_970_dabrx, val_p); break; }
1041
1042 if(spr==chud_970_hsprg0) { retval = mtspr64(chud_970_hsprg0, val_p); break; }
1043 if(spr==chud_970_hsprg1) { retval = mtspr64(chud_970_hsprg1, val_p); break; }
1044 if(spr==chud_970_hsrr0) { retval = mtspr64(chud_970_hsrr0, val_p); break; }
1045 if(spr==chud_970_hsrr1) { retval = mtspr64(chud_970_hsrr1, val_p); break; }
1046 if(spr==chud_970_hdec) { retval = mtspr64(chud_970_hdec, val_p); break; }
1047 if(spr==chud_970_trig0) { retval = mtspr64(chud_970_trig0, val_p); break; }
1048 if(spr==chud_970_trig1) { retval = mtspr64(chud_970_trig1, val_p); break; }
1049 if(spr==chud_970_trig2) { retval = mtspr64(chud_970_trig2, val_p); break; }
1050 if(spr==chud_970_scomc) { retval = mtspr64(chud_970_scomc, val_p); break; }
1051 if(spr==chud_970_scomd) { retval = mtspr64(chud_970_scomd, val_p); break; }
1052
1053 if(spr==chud_970_hid0) {
1054 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1055 break;
1056 }
1057
1058 if(spr==chud_970_hid1) {
1059 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1060 break;
1061 }
1062
1063 if(spr==chud_970_hid4) {
1064 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1065 break;
1066 }
1067
1068 if(spr==chud_970_hid5) {
1069 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1070 break;
1071 }
1072
1073 }
1074
1075 /* we only get here if none of the above cases qualify */
1076 retval = KERN_INVALID_ARGUMENT;
1077 } while(0);
1078
1079 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
1080
1081 if(cpu>=0) { // cpu<0 means don't bind
1082 chudxnu_unbind_thread(current_thread(), 0);
1083 }
1084
1085 return retval;
1086 }
1087
1088 #if 0
1089 #pragma mark **** perfmon facility ****
1090 #endif
1091
1092 __private_extern__
1093 kern_return_t chudxnu_perfmon_acquire_facility(task_t task)
1094 {
1095 return perfmon_acquire_facility(task);
1096 }
1097
1098 __private_extern__
1099 kern_return_t chudxnu_perfmon_release_facility(task_t task)
1100 {
1101 return perfmon_release_facility(task);
1102 }
1103
1104 #if 0
1105 #pragma mark **** rupt counters ****
1106 #endif
1107
1108 __private_extern__
1109 kern_return_t chudxnu_get_cpu_interrupt_counters(int cpu, interrupt_counters_t *rupts)
1110 {
1111 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1112 return KERN_FAILURE;
1113 }
1114
1115 if(rupts) {
1116 boolean_t oldlevel = ml_set_interrupts_enabled(FALSE);
1117 struct per_proc_info *per_proc;
1118
1119 per_proc = PerProcTable[cpu].ppe_vaddr;
1120 rupts->hwResets = per_proc->hwCtr.hwResets;
1121 rupts->hwMachineChecks = per_proc->hwCtr.hwMachineChecks;
1122 rupts->hwDSIs = per_proc->hwCtr.hwDSIs;
1123 rupts->hwISIs = per_proc->hwCtr.hwISIs;
1124 rupts->hwExternals = per_proc->hwCtr.hwExternals;
1125 rupts->hwAlignments = per_proc->hwCtr.hwAlignments;
1126 rupts->hwPrograms = per_proc->hwCtr.hwPrograms;
1127 rupts->hwFloatPointUnavailable = per_proc->hwCtr.hwFloatPointUnavailable;
1128 rupts->hwDecrementers = per_proc->hwCtr.hwDecrementers;
1129 rupts->hwIOErrors = per_proc->hwCtr.hwIOErrors;
1130 rupts->hwSystemCalls = per_proc->hwCtr.hwSystemCalls;
1131 rupts->hwTraces = per_proc->hwCtr.hwTraces;
1132 rupts->hwFloatingPointAssists = per_proc->hwCtr.hwFloatingPointAssists;
1133 rupts->hwPerformanceMonitors = per_proc->hwCtr.hwPerformanceMonitors;
1134 rupts->hwAltivecs = per_proc->hwCtr.hwAltivecs;
1135 rupts->hwInstBreakpoints = per_proc->hwCtr.hwInstBreakpoints;
1136 rupts->hwSystemManagements = per_proc->hwCtr.hwSystemManagements;
1137 rupts->hwAltivecAssists = per_proc->hwCtr.hwAltivecAssists;
1138 rupts->hwThermal = per_proc->hwCtr.hwThermal;
1139 rupts->hwSoftPatches = per_proc->hwCtr.hwSoftPatches;
1140 rupts->hwMaintenances = per_proc->hwCtr.hwMaintenances;
1141 rupts->hwInstrumentations = per_proc->hwCtr.hwInstrumentations;
1142
1143 ml_set_interrupts_enabled(oldlevel);
1144 return KERN_SUCCESS;
1145 } else {
1146 return KERN_FAILURE;
1147 }
1148 }
1149
1150 __private_extern__
1151 kern_return_t chudxnu_clear_cpu_interrupt_counters(int cpu)
1152 {
1153 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1154 return KERN_FAILURE;
1155 }
1156
1157 bzero((char *)&(PerProcTable[cpu].ppe_vaddr->hwCtr), sizeof(struct hwCtrs));
1158 return KERN_SUCCESS;
1159 }
1160
1161 #if 0
1162 #pragma mark *** deprecated ***
1163 #endif
1164
1165 //DEPRECATED
1166 __private_extern__
1167 void chudxnu_flush_caches(void)
1168 {
1169 cacheInit();
1170 }
1171
1172 //DEPRECATED
1173 __private_extern__
1174 void chudxnu_enable_caches(boolean_t enable)
1175 {
1176 if(!enable) {
1177 cacheInit();
1178 cacheDisable();
1179 } else {
1180 cacheInit();
1181 }
1182 }
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