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29 /***** Tunables that apply to all cores, all revisions *****/
31 // IC prefetch configuration
32 // <rdar://problem/23019425>
33 HID_INSERT_BITS ARM64_REG_HID0, ARM64_REG_HID0_ICPrefDepth_bmsk, ARM64_REG_HID0_ICPrefDepth_VALUE, $1
34 HID_SET_BITS ARM64_REG_HID0, ARM64_REG_HID0_ICPrefLimitOneBrn, $1
36 // disable reporting of TLB-multi-hit-error
37 // <rdar://problem/22163216>
38 HID_CLEAR_BITS ARM64_REG_LSU_ERR_CTL, ARM64_REG_LSU_ERR_CTL_L1DTlbMultiHitEN, $1
40 // disable crypto fusion across decode groups
41 // <rdar://problem/27306424>
42 HID_SET_BITS ARM64_REG_HID1, ARM64_REG_HID1_disAESFuseAcrossGrp, $1
44 /***** Tunables that apply to all P cores, all revisions *****/
47 /***** Tunables that apply to all E cores, all revisions *****/
50 /***** Tunables that apply to specific cores, all revisions *****/
51 EXEC_COREEQ_REVALL MIDR_MYST, $0, $1
52 // Clear DisDcZvaCmdOnly
53 // Per Myst A0/B0 tunables document
54 // <rdar://problem/27627428> Myst: Confirm ACC Per-CPU Tunables
55 HID_CLEAR_BITS ARM64_REG_HID3, ARM64_REG_HID3_DisDcZvaCmdOnly, $1
56 HID_CLEAR_BITS ARM64_REG_EHID3, ARM64_REG_HID3_DisDcZvaCmdOnly, $1
59 /***** Tunables that apply to specific cores and revisions *****/