osfmk/arm64/proc_reg.h

   1 /*
   2  * Copyright (c) 2007-2013 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * Processor registers for ARM64
  30  */
  31 #ifndef _ARM64_PROC_REG_H_
  32 #define _ARM64_PROC_REG_H_
  33
  34 #include <arm/proc_reg.h>
  35
  36 #if __ARM_KERNEL_PROTECT__
  37 /*
  38  * __ARM_KERNEL_PROTECT__ is a feature intended to guard against potential
  39  * architectural or microarchitectural vulnerabilities that could allow cores to
  40  * read/access EL1-only mappings while in EL0 mode.  This is achieved by
  41  * removing as many mappings as possible when the core transitions to EL0 mode
  42  * from EL1 mode, and restoring those mappings when the core transitions to EL1
  43  * mode from EL0 mode.
  44  *
  45  * At the moment, this is achieved through use of ASIDs and TCR_EL1.  TCR_EL1 is
  46  * used to map and unmap the ordinary kernel mappings, by contracting and
  47  * expanding translation zone size for TTBR1 when exiting and entering EL1,
  48  * respectively:
  49  *
  50  * Kernel EL0 Mappings: TTBR1 mappings that must remain mapped while the core is
  51  *   is in EL0.
  52  * Kernel EL1 Mappings: TTBR1 mappings that must be mapped while the core is in
  53  *   EL1.
  54  *
  55  * T1SZ_USER: T1SZ_BOOT + 1
  56  * TTBR1_EL1_BASE_BOOT: (2^64) - (2^(64 - T1SZ_BOOT)
  57  * TTBR1_EL1_BASE_USER: (2^64) - (2^(64 - T1SZ_USER)
  58  * TTBR1_EL1_MAX: (2^64) - 1
  59  *
  60  * When in EL1, we program TCR_EL1 (specifically, TCR_EL1.T1SZ) to give the
  61  * the following TTBR1 layout:
  62  *
  63  *  TTBR1_EL1_BASE_BOOT   TTBR1_EL1_BASE_USER   TTBR1_EL1_MAX
  64  * +---------------------------------------------------------+
  65  * | Kernel EL0 Mappings |        Kernel EL1 Mappings        |
  66  * +---------------------------------------------------------+
  67  *
  68  * And when in EL0, we program TCR_EL1 to give the following TTBR1 layout:
  69  *
  70  *  TTBR1_EL1_BASE_USER                         TTBR1_EL1_MAX
  71  * +---------------------------------------------------------+
  72  * |                   Kernel EL0 Mappings                   |
  73  * +---------------------------------------------------------+
  74  *
  75  * With the current implementation, both the EL0 and EL1 mappings for the kernel
  76  * use otherwise empty translation tables for mapping the exception vectors (so
  77  * that we do not need to TLB flush the exception vector address when switching
  78  * between EL0 and EL1).  The rationale here is that the TLBI would require a
  79  * DSB, and DSBs can be extremely expensive.
  80  *
  81  * Each pmap is given two ASIDs: (n & ~1) as an EL0 ASID, and (n | 1) as an EL1
  82  * ASID.  The core switches between ASIDs on EL transitions, so that the TLB
  83  * does not need to be fully invalidated on an EL transition.
  84  *
  85  * Most kernel mappings will be marked non-global in this configuration, as
  86  * global mappings would be visible to userspace unless we invalidate them on
  87  * eret.
  88  */
  89 #if XNU_MONITOR
  90 /*
  91  * Please note that because we indirect through the thread register in order to
  92  * locate the kernel, and because we unmap most of the kernel, the security
  93  * model of the PPL is undermined by __ARM_KERNEL_PROTECT__, as we rely on
  94  * kernel controlled data to direct codeflow in the exception vectors.
  95  *
  96  * If we want to ship XNU_MONITOR paired with __ARM_KERNEL_PROTECT__, we will
  97  * need to find a performant solution to this problem.
  98  */
  99 #endif
 100 #endif /* __ARM_KERNEL_PROTECT */
 101
 102 #if ARM_PARAMETERIZED_PMAP
 103 /*
 104  * ARM_PARAMETERIZED_PMAP configures the kernel to get the characteristics of
 105  * the page tables (number of levels, size of the root allocation) from the
 106  * pmap data structure, rather than treating them as compile-time constants.
 107  * This allows the pmap code to dynamically adjust how it deals with page
 108  * tables.
 109  */
 110 #endif /* ARM_PARAMETERIZED_PMAP */
 111
 112 #if __ARM_MIXED_PAGE_SIZE__
 113 /*
 114  * __ARM_MIXED_PAGE_SIZE__ configures the kernel to support page tables that do
 115  * not use the kernel page size.  This is primarily meant to support running
 116  * 4KB page processes on a 16KB page kernel.
 117  *
 118  * This only covers support in the pmap/machine dependent layers.  Any support
 119  * elsewhere in the kernel must be managed separately.
 120  */
 121 #if !ARM_PARAMETERIZED_PMAP
 122 /*
 123  * Page tables that use non-kernel page sizes require us to reprogram TCR based
 124  * on the page tables we are switching to.  This means that the parameterized
 125  * pmap support is required.
 126  */
 127 #error __ARM_MIXED_PAGE_SIZE__ requires ARM_PARAMETERIZED_PMAP
 128 #endif /* !ARM_PARAMETERIZED_PMAP */
 129 #if __ARM_KERNEL_PROTECT__
 130 /*
 131  * Because switching the page size requires updating TCR based on the pmap, and
 132  * __ARM_KERNEL_PROTECT__ relies on TCR being programmed with constants, XNU
 133  * does not currently support support configurations that use both
 134  * __ARM_KERNEL_PROTECT__ and __ARM_MIXED_PAGE_SIZE__.
 135  */
 136 #error __ARM_MIXED_PAGE_SIZE__ and __ARM_KERNEL_PROTECT__ are mutually exclusive
 137 #endif /* __ARM_KERNEL_PROTECT__ */
 138 #endif /* __ARM_MIXED_PAGE_SIZE__ */
 139
 140 /*
 141  * 64-bit Program Status Register (PSR64)
 142  *
 143  *  31      27 23  22 21 20 19      10 9       5 4   0
 144  * +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+
 145  * |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0|  M  |
 146  * +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+
 147  *
 148  * where:
 149  *   NZCV: Comparison flags
 150  *   PAN:  Privileged Access Never
 151  *   SS:   Single step
 152  *   IL:   Illegal state
 153  *   DAIF: Interrupt masks
 154  *   M:    Mode field
 155  */
 156
 157 #define PSR64_NZCV_SHIFT 28
 158 #define PSR64_NZCV_MASK  (0xF << PSR64_NZCV_SHIFT)
 159
 160 #define PSR64_N_SHIFT    31
 161 #define PSR64_N          (1 << PSR64_N_SHIFT)
 162
 163 #define PSR64_Z_SHIFT    30
 164 #define PSR64_Z          (1 << PSR64_Z_SHIFT)
 165
 166 #define PSR64_C_SHIFT    29
 167 #define PSR64_C          (1 << PSR64_C_SHIFT)
 168
 169 #define PSR64_V_SHIFT    28
 170 #define PSR64_V          (1 << PSR64_V_SHIFT)
 171
 172 #define PSR64_PAN_SHIFT  22
 173 #define PSR64_PAN        (1 << PSR64_PAN_SHIFT)
 174
 175 #define PSR64_SS_SHIFT   21
 176 #define PSR64_SS         (1 << PSR64_SS_SHIFT)
 177
 178 #define PSR64_IL_SHIFT   20
 179 #define PSR64_IL         (1 << PSR64_IL_SHIFT)
 180
 181 /*
 182  * SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR
 183  * I do not want to talk about it!
 184  */
 185 #define PSR64_SSBS_SHIFT_32   23
 186 #define PSR64_SSBS_SHIFT_64   12
 187 #define PSR64_SSBS_32         (1 << PSR64_SSBS_SHIFT_32)
 188 #define PSR64_SSBS_64         (1 << PSR64_SSBS_SHIFT_64)
 189
 190 /*
 191  * msr DAIF, Xn and mrs Xn, DAIF transfer into
 192  * and out of bits 9:6
 193  */
 194 #define DAIF_DEBUG_SHIFT      9
 195 #define DAIF_DEBUGF           (1 << DAIF_DEBUG_SHIFT)
 196
 197 #define DAIF_ASYNC_SHIFT      8
 198 #define DAIF_ASYNCF           (1 << DAIF_ASYNC_SHIFT)
 199
 200 #define DAIF_IRQF_SHIFT       7
 201 #define DAIF_IRQF             (1 << DAIF_IRQF_SHIFT)
 202
 203 #define DAIF_FIQF_SHIFT       6
 204 #define DAIF_FIQF             (1 << DAIF_FIQF_SHIFT)
 205
 206 #define DAIF_ALL              (DAIF_DEBUGF | DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF)
 207 #define DAIF_STANDARD_DISABLE (DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF)
 208
 209 #define SPSR_INTERRUPTS_ENABLED(x) (!(x & DAIF_FIQF))
 210
 211 #if __ARM_ARCH_8_5__
 212 #define PSR64_SSBS_U32_DEFAULT  PSR64_SSBS_32
 213 #define PSR64_SSBS_U64_DEFAULT  PSR64_SSBS_64
 214 #define PSR64_SSBS_KRN_DEFAULT  PSR64_SSBS_64
 215 #else
 216 #define PSR64_SSBS_U32_DEFAULT  (0)
 217 #define PSR64_SSBS_U64_DEFAULT  (0)
 218 #define PSR64_SSBS_KRN_DEFAULT  (0)
 219 #endif
 220
 221 /*
 222  * msr DAIFSet, Xn, and msr DAIFClr, Xn transfer
 223  * from bits 3:0.
 224  */
 225 #define DAIFSC_DEBUGF           (1 << 3)
 226 #define DAIFSC_ASYNCF           (1 << 2)
 227 #define DAIFSC_IRQF             (1 << 1)
 228 #define DAIFSC_FIQF             (1 << 0)
 229 #define DAIFSC_ALL              (DAIFSC_DEBUGF | DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF)
 230 #define DAIFSC_STANDARD_DISABLE (DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF)
 231
 232 /*
 233  * ARM64_TODO: unify with ARM?
 234  */
 235 #define PSR64_CF         0x20000000 /* Carry/Borrow/Extend */
 236
 237 #define PSR64_MODE_MASK         0x1F
 238
 239 #define PSR64_USER_MASK         PSR64_NZCV_MASK
 240
 241 #define PSR64_MODE_USER32_THUMB 0x20
 242
 243 #define PSR64_MODE_RW_SHIFT     4
 244 #define PSR64_MODE_RW_64        0
 245 #define PSR64_MODE_RW_32        (0x1 << PSR64_MODE_RW_SHIFT)
 246
 247 #define PSR64_MODE_EL_SHIFT     2
 248 #define PSR64_MODE_EL_MASK      (0x3 << PSR64_MODE_EL_SHIFT)
 249 #define PSR64_MODE_EL3          (0x3 << PSR64_MODE_EL_SHIFT)
 250 #define PSR64_MODE_EL2          (0x2 << PSR64_MODE_EL_SHIFT)
 251 #define PSR64_MODE_EL1          (0x1 << PSR64_MODE_EL_SHIFT)
 252 #define PSR64_MODE_EL0          0
 253
 254 #define PSR64_MODE_SPX          0x1
 255 #define PSR64_MODE_SP0          0
 256
 257 #define PSR64_USER32_DEFAULT    (PSR64_MODE_RW_32 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U32_DEFAULT)
 258 #define PSR64_USER64_DEFAULT    (PSR64_MODE_RW_64 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U64_DEFAULT)
 259 #define PSR64_KERNEL_STANDARD   (DAIF_STANDARD_DISABLE | PSR64_MODE_RW_64 | PSR64_MODE_EL1 | PSR64_MODE_SP0 | PSR64_SSBS_KRN_DEFAULT)
 260 #if __ARM_PAN_AVAILABLE__
 261 #define PSR64_KERNEL_DEFAULT    (PSR64_KERNEL_STANDARD | PSR64_PAN)
 262 #else
 263 #define PSR64_KERNEL_DEFAULT    PSR64_KERNEL_STANDARD
 264 #endif
 265 #define PSR64_KERNEL_POISON     (PSR64_IL | PSR64_MODE_EL1)
 266
 267 #define PSR64_IS_KERNEL(x)      ((x & PSR64_MODE_EL_MASK) > PSR64_MODE_EL0)
 268 #define PSR64_IS_USER(x)        ((x & PSR64_MODE_EL_MASK) == PSR64_MODE_EL0)
 269
 270 #define PSR64_IS_USER32(x)      (PSR64_IS_USER(x) && (x & PSR64_MODE_RW_32))
 271 #define PSR64_IS_USER64(x)      (PSR64_IS_USER(x) && !(x & PSR64_MODE_RW_32))
 272
 273
 274
 275 /*
 276  * System Control Register (SCTLR)
 277  */
 278
 279 #define SCTLR_DSSBS               (1ULL << 44)
 280
 281 #define SCTLR_RESERVED     ((3ULL << 28) | (1ULL << 20))
 282 #if defined(HAS_APPLE_PAC)
 283
 284 // 31    PACIA_ENABLED AddPACIA and AuthIA functions enabled
 285 #define SCTLR_PACIA_ENABLED_SHIFT 31
 286 #define SCTLR_PACIA_ENABLED       (1ULL << SCTLR_PACIA_ENABLED_SHIFT)
 287 // 30    PACIB_ENABLED AddPACIB and AuthIB functions enabled
 288 #define SCTLR_PACIB_ENABLED       (1ULL << 30)
 289 // 29:28 RES1 11
 290 // 27    PACDA_ENABLED AddPACDA and AuthDA functions enabled
 291 #define SCTLR_PACDA_ENABLED       (1ULL << 27)
 292 // 13    PACDB_ENABLED  AddPACDB and AuthDB functions enabled
 293 #define SCTLR_PACDB_ENABLED       (1ULL << 13)
 294
 295 #define SCTLR_JOP_KEYS_ENABLED (SCTLR_PACIA_ENABLED | SCTLR_PACDA_ENABLED | SCTLR_PACDB_ENABLED)
 296 #endif /* defined(HAS_APPLE_PAC) */
 297
 298 // 26    UCI User Cache Instructions
 299 #define SCTLR_UCI_ENABLED         (1ULL << 26)
 300
 301 // 25    EE             Exception Endianness
 302 #define SCTLR_EE_BIG_ENDIAN       (1ULL << 25)
 303
 304 // 24    E0E            EL0 Endianness
 305 #define SCTLR_E0E_BIG_ENDIAN      (1ULL << 24)
 306
 307 // 23    SPAN           Set PAN
 308 #define SCTLR_PAN_UNCHANGED       (1ULL << 23)
 309
 310 // 22    EIS            Taking an exception is a context synchronization event
 311 #define SCTLR_EIS                 (1ULL << 22)
 312
 313 // 21    RES0           0
 314 // 20    RES1           1
 315
 316 // 19    WXN            Writeable implies eXecute Never
 317 #define SCTLR_WXN_ENABLED         (1ULL << 19)
 318
 319 // 18    nTWE           Not trap WFE from EL0
 320 #define SCTLR_nTWE_WFE_ENABLED    (1ULL << 18)
 321
 322 // 17    RES0           0
 323
 324 // 16    nTWI           Not trap WFI from EL0
 325 #define SCTRL_nTWI_WFI_ENABLED    (1ULL << 16)
 326
 327 // 15    UCT            User Cache Type register (CTR_EL0)
 328 #define SCTLR_UCT_ENABLED         (1ULL << 15)
 329
 330 // 14    DZE            User Data Cache Zero (DC ZVA)
 331 #define SCTLR_DZE_ENABLED         (1ULL << 14)
 332
 333 // 12    I              Instruction cache enable
 334 #define SCTLR_I_ENABLED           (1ULL << 12)
 335
 336 // 11    EOS            Exception return is a context synchronization event
 337 #define SCTLR_EOS                 (1ULL << 11)
 338
 339 // 10    RES0           0
 340
 341 // 9     UMA            User Mask Access
 342 #define SCTLR_UMA_ENABLED         (1ULL << 9)
 343
 344 // 8     SED            SETEND Disable
 345 #define SCTLR_SED_DISABLED        (1ULL << 8)
 346
 347 // 7     ITD            IT Disable
 348 #define SCTLR_ITD_DISABLED        (1ULL << 7)
 349
 350 // 6     RES0           0
 351
 352 // 5     CP15BEN        CP15 Barrier ENable
 353 #define SCTLR_CP15BEN_ENABLED     (1ULL << 5)
 354
 355 // 4     SA0            Stack Alignment check for EL0
 356 #define SCTLR_SA0_ENABLED         (1ULL << 4)
 357
 358 // 3     SA             Stack Alignment check
 359 #define SCTLR_SA_ENABLED          (1ULL << 3)
 360
 361 // 2     C              Cache enable
 362 #define SCTLR_C_ENABLED           (1ULL << 2)
 363
 364 // 1     A              Alignment check
 365 #define SCTLR_A_ENABLED           (1ULL << 1)
 366
 367 // 0     M              MMU enable
 368 #define SCTLR_M_ENABLED           (1ULL << 0)
 369
 370 #if __ARM_ARCH_8_5__
 371 #define SCTLR_CSEH_DEFAULT        (0)
 372 #define SCTLR_DSSBS_DEFAULT       SCTLR_DSSBS
 373 #else
 374 #define SCTLR_CSEH_DEFAULT        (SCTLR_EIS | SCTLR_EOS)
 375 #define SCTLR_DSSBS_DEFAULT       (0)
 376 #endif
 377
 378 #define SCTLR_EL1_DEFAULT \
 379         (SCTLR_RESERVED | SCTLR_UCI_ENABLED | SCTLR_nTWE_WFE_ENABLED | SCTLR_DZE_ENABLED | \
 380          SCTLR_I_ENABLED | SCTLR_SED_DISABLED | SCTLR_CP15BEN_ENABLED |                    \
 381          SCTLR_SA0_ENABLED | SCTLR_SA_ENABLED | SCTLR_C_ENABLED | SCTLR_M_ENABLED |        \
 382          SCTLR_CSEH_DEFAULT | SCTLR_DSSBS_DEFAULT)
 383
 384 /*
 385  * Coprocessor Access Control Register (CPACR)
 386  *
 387  *  31  28  27  22 21  20 19                 0
 388  * +---+---+------+------+--------------------+
 389  * |000|TTA|000000| FPEN |00000000000000000000|
 390  * +---+---+------+------+--------------------+
 391  *
 392  * where:
 393  *   TTA:  Trace trap
 394  *   FPEN: Floating point enable
 395  */
 396 #define CPACR_TTA_SHIFT     28
 397 #define CPACR_TTA           (1 << CPACR_TTA_SHIFT)
 398
 399 #define CPACR_FPEN_SHIFT    20
 400 #define CPACR_FPEN_EL0_TRAP (0x1 << CPACR_FPEN_SHIFT)
 401 #define CPACR_FPEN_ENABLE   (0x3 << CPACR_FPEN_SHIFT)
 402
 403 /*
 404  *  FPSR: Floating Point Status Register
 405  *
 406  *  31 30 29 28 27 26                  7   6  4   3   2   1   0
 407  * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+
 408  * | N| Z| C| V|QC|0000000000000000000|IDC|00|IXC|UFC|OFC|DZC|IOC|
 409  * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+
 410  */
 411
 412 #define FPSR_N_SHIFT   31
 413 #define FPSR_Z_SHIFT   30
 414 #define FPSR_C_SHIFT   29
 415 #define FPSR_V_SHIFT   28
 416 #define FPSR_QC_SHIFT  27
 417 #define FPSR_IDC_SHIFT 7
 418 #define FPSR_IXC_SHIFT 4
 419 #define FPSR_UFC_SHIFT 3
 420 #define FPSR_OFC_SHIFT 2
 421 #define FPSR_DZC_SHIFT 1
 422 #define FPSR_IOC_SHIFT 0
 423 #define FPSR_N         (1 << FPSR_N_SHIFT)
 424 #define FPSR_Z         (1 << FPSR_Z_SHIFT)
 425 #define FPSR_C         (1 << FPSR_C_SHIFT)
 426 #define FPSR_V         (1 << FPSR_V_SHIFT)
 427 #define FPSR_QC        (1 << FPSR_QC_SHIFT)
 428 #define FPSR_IDC       (1 << FPSR_IDC_SHIFT)
 429 #define FPSR_IXC       (1 << FPSR_IXC_SHIFT)
 430 #define FPSR_UFC       (1 << FPSR_UFC_SHIFT)
 431 #define FPSR_OFC       (1 << FPSR_OFC_SHIFT)
 432 #define FPSR_DZC       (1 << FPSR_DZC_SHIFT)
 433 #define FPSR_IOC       (1 << FPSR_IOC_SHIFT)
 434
 435 /*
 436  * A mask for all for all of the bits that are not RAZ for FPSR; this
 437  * is primarily for converting between a 32-bit view of NEON state
 438  * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR).
 439  */
 440 #define FPSR_MASK \
 441         (FPSR_N | FPSR_Z | FPSR_C | FPSR_V | FPSR_QC | FPSR_IDC | FPSR_IXC | \
 442          FPSR_UFC | FPSR_OFC | FPSR_DZC | FPSR_IOC)
 443
 444 /*
 445  *  FPCR: Floating Point Control Register
 446  *
 447  *  31    26  25 24 23    21     19 18  15  14 12  11  10  9   8   7      0
 448  * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+
 449  * |00000|AHP|DN|FZ|RMODE|STRIDE| 0|LEN|IDE|00|IXE|UFE|OFE|DZE|IOE|00000000|
 450  * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+
 451  */
 452
 453 #define FPCR_AHP_SHIFT    26
 454 #define FPCR_DN_SHIFT     25
 455 #define FPCR_FZ_SHIFT     24
 456 #define FPCR_RMODE_SHIFT  22
 457 #define FPCR_STRIDE_SHIFT 20
 458 #define FPCR_LEN_SHIFT    16
 459 #define FPCR_IDE_SHIFT    15
 460 #define FPCR_IXE_SHIFT    12
 461 #define FPCR_UFE_SHIFT    11
 462 #define FPCR_OFE_SHIFT    10
 463 #define FPCR_DZE_SHIFT    9
 464 #define FPCR_IOE_SHIFT    8
 465 #define FPCR_AHP          (1 << FPCR_AHP_SHIFT)
 466 #define FPCR_DN           (1 << FPCR_DN_SHIFT)
 467 #define FPCR_FZ           (1 << FPCR_FZ_SHIFT)
 468 #define FPCR_RMODE        (0x3 << FPCR_RMODE_SHIFT)
 469 #define FPCR_STRIDE       (0x3 << FPCR_STRIDE_SHIFT)
 470 #define FPCR_LEN          (0x7 << FPCR_LEN_SHIFT)
 471 #define FPCR_IDE          (1 << FPCR_IDE_SHIFT)
 472 #define FPCR_IXE          (1 << FPCR_IXE_SHIFT)
 473 #define FPCR_UFE          (1 << FPCR_UFE_SHIFT)
 474 #define FPCR_OFE          (1 << FPCR_OFE_SHIFT)
 475 #define FPCR_DZE          (1 << FPCR_DZE_SHIFT)
 476 #define FPCR_IOE          (1 << FPCR_IOE_SHIFT)
 477 #define FPCR_DEFAULT      (0)
 478 #define FPCR_DEFAULT_32   (FPCR_DN|FPCR_FZ)
 479
 480 /*
 481  * A mask for all for all of the bits that are not RAZ for FPCR; this
 482  * is primarily for converting between a 32-bit view of NEON state
 483  * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR).
 484  */
 485 #define FPCR_MASK \
 486         (FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE | FPCR_STRIDE | FPCR_LEN | \
 487          FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE)
 488
 489 /*
 490  * Translation Control Register (TCR)
 491  *
 492  * Legacy:
 493  *
 494  *  63  39   38   37 36   34 32    30 29 28 27 26 25 24   23 22 21  16    14 13 12 11 10 9   8    7   5  0
 495  * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+
 496  * | zero |TBI1|TBI0|AS|z| IPS |z|TG1| SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ |z|TG0| SH0 |ORGN0|IRGN0|EPD0|z|T0SZ|
 497  * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+
 498  *
 499  * Current (with 16KB granule support):
 500  *
 501  *  63  39   38   37 36   34 32    30 29 28 27 26 25 24   23 22 21  16    14 13 12 11 10 9   8    7   5  0
 502  * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+
 503  * | zero |TBI1|TBI0|AS|z| IPS | TG1 | SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ | TG0 | SH0 |ORGN0|IRGN0|EPD0|z|T0SZ|
 504  * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+
 505  *
 506  * TBI1:  Top Byte Ignored for TTBR1 region
 507  * TBI0:  Top Byte Ignored for TTBR0 region
 508  * AS:    ASID Size
 509  * IPS:   Physical Address Size limit
 510  * TG1:   Granule Size for TTBR1 region
 511  * SH1:   Shareability for TTBR1 region
 512  * ORGN1: Outer Cacheability for TTBR1 region
 513  * IRGN1: Inner Cacheability for TTBR1 region
 514  * EPD1:  Translation table walk disable for TTBR1
 515  * A1:    ASID selection from TTBR1 enable
 516  * T1SZ:  Virtual address size for TTBR1
 517  * TG0:   Granule Size for TTBR0 region
 518  * SH0:   Shareability for TTBR0 region
 519  * ORGN0: Outer Cacheability for TTBR0 region
 520  * IRGN0: Inner Cacheability for TTBR0 region
 521  * T0SZ:  Virtual address size for TTBR0
 522  */
 523
 524 #define TCR_T0SZ_SHIFT          0ULL
 525 #define TCR_TSZ_BITS            6ULL
 526 #define TCR_TSZ_MASK            ((1ULL << TCR_TSZ_BITS) - 1ULL)
 527
 528 #define TCR_IRGN0_SHIFT         8ULL
 529 #define TCR_IRGN0_DISABLED      (0ULL << TCR_IRGN0_SHIFT)
 530 #define TCR_IRGN0_WRITEBACK     (1ULL << TCR_IRGN0_SHIFT)
 531 #define TCR_IRGN0_WRITETHRU     (2ULL << TCR_IRGN0_SHIFT)
 532 #define TCR_IRGN0_WRITEBACKNO   (3ULL << TCR_IRGN0_SHIFT)
 533
 534 #define TCR_ORGN0_SHIFT         10ULL
 535 #define TCR_ORGN0_DISABLED      (0ULL << TCR_ORGN0_SHIFT)
 536 #define TCR_ORGN0_WRITEBACK     (1ULL << TCR_ORGN0_SHIFT)
 537 #define TCR_ORGN0_WRITETHRU     (2ULL << TCR_ORGN0_SHIFT)
 538 #define TCR_ORGN0_WRITEBACKNO   (3ULL << TCR_ORGN0_SHIFT)
 539
 540 #define TCR_SH0_SHIFT           12ULL
 541 #define TCR_SH0_NONE            (0ULL << TCR_SH0_SHIFT)
 542 #define TCR_SH0_OUTER           (2ULL << TCR_SH0_SHIFT)
 543 #define TCR_SH0_INNER           (3ULL << TCR_SH0_SHIFT)
 544
 545 #define TCR_TG0_GRANULE_SHIFT   (14ULL)
 546 #define TCR_TG0_GRANULE_BITS    (2ULL)
 547 #define TCR_TG0_GRANULE_MASK    ((1ULL << TCR_TG0_GRANULE_BITS) - 1ULL)
 548
 549 #define TCR_TG0_GRANULE_4KB     (0ULL << TCR_TG0_GRANULE_SHIFT)
 550 #define TCR_TG0_GRANULE_64KB    (1ULL << TCR_TG0_GRANULE_SHIFT)
 551 #define TCR_TG0_GRANULE_16KB    (2ULL << TCR_TG0_GRANULE_SHIFT)
 552
 553 #if __ARM_16K_PG__
 554 #define TCR_TG0_GRANULE_SIZE    (TCR_TG0_GRANULE_16KB)
 555 #else
 556 #define TCR_TG0_GRANULE_SIZE    (TCR_TG0_GRANULE_4KB)
 557 #endif
 558
 559 #define TCR_T1SZ_SHIFT          16ULL
 560
 561 #define TCR_A1_ASID1            (1ULL << 22ULL)
 562 #define TCR_EPD1_TTBR1_DISABLED (1ULL << 23ULL)
 563
 564 #define TCR_IRGN1_SHIFT          24ULL
 565 #define TCR_IRGN1_DISABLED       (0ULL << TCR_IRGN1_SHIFT)
 566 #define TCR_IRGN1_WRITEBACK      (1ULL << TCR_IRGN1_SHIFT)
 567 #define TCR_IRGN1_WRITETHRU      (2ULL << TCR_IRGN1_SHIFT)
 568 #define TCR_IRGN1_WRITEBACKNO    (3ULL << TCR_IRGN1_SHIFT)
 569
 570 #define TCR_ORGN1_SHIFT          26ULL
 571 #define TCR_ORGN1_DISABLED       (0ULL << TCR_ORGN1_SHIFT)
 572 #define TCR_ORGN1_WRITEBACK      (1ULL << TCR_ORGN1_SHIFT)
 573 #define TCR_ORGN1_WRITETHRU      (2ULL << TCR_ORGN1_SHIFT)
 574 #define TCR_ORGN1_WRITEBACKNO    (3ULL << TCR_ORGN1_SHIFT)
 575
 576 #define TCR_SH1_SHIFT            28ULL
 577 #define TCR_SH1_NONE             (0ULL << TCR_SH1_SHIFT)
 578 #define TCR_SH1_OUTER            (2ULL << TCR_SH1_SHIFT)
 579 #define TCR_SH1_INNER            (3ULL << TCR_SH1_SHIFT)
 580
 581 #define TCR_TG1_GRANULE_SHIFT    30ULL
 582
 583 #define TCR_TG1_GRANULE_16KB     (1ULL << TCR_TG1_GRANULE_SHIFT)
 584 #define TCR_TG1_GRANULE_4KB      (2ULL << TCR_TG1_GRANULE_SHIFT)
 585 #define TCR_TG1_GRANULE_64KB     (3ULL << TCR_TG1_GRANULE_SHIFT)
 586
 587 #if __ARM_16K_PG__
 588 #define TCR_TG1_GRANULE_SIZE     (TCR_TG1_GRANULE_16KB)
 589 #else
 590 #define TCR_TG1_GRANULE_SIZE     (TCR_TG1_GRANULE_4KB)
 591 #endif
 592
 593 #define TCR_IPS_SHIFT            32ULL
 594 #define TCR_IPS_BITS             3ULL
 595 #define TCR_IPS_MASK             ((1ULL << TCR_IPS_BITS) - 1ULL)
 596 #define TCR_IPS_32BITS           (0ULL << TCR_IPS_SHIFT)
 597 #define TCR_IPS_36BITS           (1ULL << TCR_IPS_SHIFT)
 598 #define TCR_IPS_40BITS           (2ULL << TCR_IPS_SHIFT)
 599 #define TCR_IPS_42BITS           (3ULL << TCR_IPS_SHIFT)
 600 #define TCR_IPS_44BITS           (4ULL << TCR_IPS_SHIFT)
 601 #define TCR_IPS_48BITS           (5ULL << TCR_IPS_SHIFT)
 602
 603 #define TCR_AS_16BIT_ASID        (1ULL << 36)
 604 #define TCR_TBI0_TOPBYTE_IGNORED (1ULL << 37)
 605 #define TCR_TBI1_TOPBYTE_IGNORED (1ULL << 38)
 606 #define TCR_TBID0_TBI_DATA_ONLY  (1ULL << 51)
 607 #define TCR_TBID1_TBI_DATA_ONLY  (1ULL << 52)
 608
 609 #if defined(HAS_APPLE_PAC)
 610 #define TCR_TBID0_ENABLE         TCR_TBID0_TBI_DATA_ONLY
 611 #else
 612 #define TCR_TBID0_ENABLE         0
 613 #endif
 614
 615 #define TCR_E0PD0_BIT            (1ULL << 55)
 616 #define TCR_E0PD1_BIT            (1ULL << 56)
 617
 618 #if defined(HAS_E0PD)
 619 #define TCR_E0PD_VALUE           (TCR_E0PD1_BIT)
 620 #else
 621 #define TCR_E0PD_VALUE           0
 622 #endif
 623
 624
 625 /*
 626  * Multiprocessor Affinity Register (MPIDR_EL1)
 627  *
 628  * +64-----------------------------31+30+29-25+24+23-16+15-8+7--0+
 629  * |000000000000000000000000000000001| U|00000|MT| Aff2|Aff1|Aff0|
 630  * +---------------------------------+--+-----+--+-----+----+----+
 631  *
 632  * where
 633  *   U:    Uniprocessor
 634  *   MT:   Multi-threading at lowest affinity level
 635  *   Aff2: "1" - PCORE, "0" - ECORE
 636  *   Aff1: Cluster ID
 637  *   Aff0: CPU ID
 638  */
 639 #define MPIDR_AFF0_SHIFT 0
 640 #define MPIDR_AFF0_WIDTH 8
 641 #define MPIDR_AFF0_MASK  (((1 << MPIDR_AFF0_WIDTH) - 1) << MPIDR_AFF0_SHIFT)
 642 #define MPIDR_AFF1_SHIFT 8
 643 #define MPIDR_AFF1_WIDTH 8
 644 #define MPIDR_AFF1_MASK  (((1 << MPIDR_AFF1_WIDTH) - 1) << MPIDR_AFF1_SHIFT)
 645 #define MPIDR_AFF2_SHIFT 16
 646 #define MPIDR_AFF2_WIDTH 8
 647 #define MPIDR_AFF2_MASK  (((1 << MPIDR_AFF2_WIDTH) - 1) << MPIDR_AFF2_SHIFT)
 648
 649 /*
 650  * TXSZ indicates the size of the range a TTBR covers.  Currently,
 651  * we support the following:
 652  *
 653  * 4KB pages, full page L1: 39 bit range.
 654  * 4KB pages, sub-page L1: 38 bit range.
 655  * 16KB pages, full page L1: 47 bit range.
 656  * 16KB pages, sub-page L1: 39 bit range.
 657  * 16KB pages, two level page tables: 36 bit range.
 658  */
 659 #if __ARM_KERNEL_PROTECT__
 660 /*
 661  * If we are configured to use __ARM_KERNEL_PROTECT__, the first half of the
 662  * address space is used for the mappings that will remain in place when in EL0.
 663  * As a result, 1 bit less of address space is available to the rest of the
 664  * the kernel.
 665  */
 666 #endif /* __ARM_KERNEL_PROTECT__ */
 667 #ifdef __ARM_16K_PG__
 668 #if __ARM64_PMAP_SUBPAGE_L1__
 669 #define T0SZ_BOOT 25ULL
 670 #else /* !__ARM64_PMAP_SUBPAGE_L1__ */
 671 #define T0SZ_BOOT 17ULL
 672 #endif /* !__ARM64_PMAP_SUBPAGE_L1__ */
 673 #else /* __ARM_16K_PG__ */
 674 #if __ARM64_PMAP_SUBPAGE_L1__
 675 #define T0SZ_BOOT 26ULL
 676 #else /* __ARM64_PMAP_SUBPAGE_L1__ */
 677 #define T0SZ_BOOT 25ULL
 678 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */
 679 #endif /* __ARM_16K_PG__ */
 680
 681 #if defined(APPLE_ARM64_ARCH_FAMILY)
 682 /* T0SZ must be the same as T1SZ */
 683 #define T1SZ_BOOT T0SZ_BOOT
 684 #else /* defined(APPLE_ARM64_ARCH_FAMILY) */
 685 #ifdef __ARM_16K_PG__
 686 #if __ARM64_PMAP_SUBPAGE_L1__
 687 #define T1SZ_BOOT 25ULL
 688 #else /* !__ARM64_PMAP_SUBPAGE_L1__ */
 689 #define T1SZ_BOOT 17ULL
 690 #endif /* !__ARM64_PMAP_SUBPAGE_L1__ */
 691 #else /* __ARM_16K_PG__ */
 692 #if __ARM64_PMAP_SUBPAGE_L1__
 693 #define T1SZ_BOOT 26ULL
 694 #else /* __ARM64_PMAP_SUBPAGE_L1__ */
 695 #define T1SZ_BOOT 25ULL
 696 #endif /*__ARM64_PMAP_SUBPAGE_L1__*/
 697 #endif /* __ARM_16K_PG__ */
 698 #endif /* defined(APPLE_ARM64_ARCH_FAMILY) */
 699
 700 #if __ARM_42BIT_PA_SPACE__
 701 #define TCR_IPS_VALUE TCR_IPS_42BITS
 702 #else /* !__ARM_42BIT_PA_SPACE__ */
 703 #define TCR_IPS_VALUE TCR_IPS_40BITS
 704 #endif /* !__ARM_42BIT_PA_SPACE__ */
 705
 706 #define TCR_EL1_BASE \
 707         (TCR_IPS_VALUE | TCR_SH0_OUTER | TCR_ORGN0_WRITEBACK |         \
 708          TCR_IRGN0_WRITEBACK | (T0SZ_BOOT << TCR_T0SZ_SHIFT) |          \
 709          TCR_SH1_OUTER | TCR_ORGN1_WRITEBACK | \
 710          TCR_IRGN1_WRITEBACK | (TCR_TG1_GRANULE_SIZE) |                 \
 711          TCR_TBI0_TOPBYTE_IGNORED | (TCR_TBID0_ENABLE) | TCR_E0PD_VALUE)
 712
 713 #if __ARM_KERNEL_PROTECT__
 714 #define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE))
 715 #define T1SZ_USER (T1SZ_BOOT + 1)
 716 #define TCR_EL1_USER (TCR_EL1_BASE | (T1SZ_USER << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE))
 717 #else
 718 #define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE))
 719 #endif /* __ARM_KERNEL_PROTECT__ */
 720
 721 #define TCR_EL1_4KB  (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_4KB))
 722 #define TCR_EL1_16KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_16KB))
 723
 724
 725
 726
 727 /*
 728  * Monitor Debug System Control Register (MDSCR)
 729  */
 730
 731 #define MDSCR_TFO_SHIFT                 31
 732 #define MDSCR_TFO                       (1ULL << MDSCR_TFO_SHIFT)
 733 #define MDSCR_RXFULL_SHIFT              30
 734 #define MDSCR_RXFULL                    (1ULL << MDSCR_RXFULL_SHIFT)
 735 #define MDSCR_TXFULL_SHIFT              29
 736 #define MDSCR_TXFULL                    (1ULL << MDSCR_TXFULL_SHIFT)
 737 #define MDSCR_RXO_SHIFT                 27
 738 #define MDSCR_RXO                       (1ULL << MDSCR_RXO_SHIFT)
 739 #define MDSCR_TXU_SHIFT                 26
 740 #define MDSCR_TXU                       (1ULL << MDSCR_TXU_SHIFT)
 741 #define MDSCR_INTDIS_SHIFT              22
 742 #define MDSCR_INTDIS_MASK               (0x2U << MDSCR_INTDIS_SHIFT)
 743 #define MDSCR_TDA_SHIFT                 21
 744 #define MDSCR_TDA                       (1ULL << MDSCR_TDA_SHIFT)
 745 #define MDSCR_SC2_SHIFT                 19
 746 #define MDSCR_SC2                       (1ULL << MDSCR_SC2_SHIFT)
 747 #define MDSCR_MDE_SHIFT                 15
 748 #define MDSCR_MDE                       (1ULL << MDSCR_MDE_SHIFT)
 749 #define MDSCR_HDE_SHIFT                 14
 750 #define MDSCR_HDE                       (1ULL << MDSCR_HDE_SHIFT)
 751 #define MDSCR_KDE_SHIFT                 13
 752 #define MDSCR_KDE                       (1ULL << MDSCR_KDE_SHIFT)
 753 #define MDSCR_TDCC_SHIFT                12
 754 #define MDSCR_TDCC                      (1ULL << MDSCR_TDCC_SHIFT)
 755 #define MDSCR_ERR_SHIFT                 6
 756 #define MDSCR_ERR                       (1ULL << MDSCR_ERR_SHIFT)
 757 #define MDSCR_SS_SHIFT                  0
 758 #define MDSCR_SS                        (1ULL << MDSCR_SS_SHIFT)
 759
 760 /*
 761  * Translation Table Base Register (TTBR)
 762  *
 763  *  63    48 47               x x-1  0
 764  * +--------+------------------+------+
 765  * |  ASID  |   Base Address   | zero |
 766  * +--------+------------------+------+
 767  *
 768  */
 769 #define TTBR_ASID_SHIFT 48
 770 #define TTBR_ASID_MASK  0xffff000000000000
 771
 772 #define TTBR_BADDR_MASK 0x0000ffffffffffff
 773
 774 /*
 775  * Memory Attribute Indirection Register
 776  *
 777  *  63   56 55   48 47   40 39   32 31   24 23   16 15    8 7     0
 778  * +-------+-------+-------+-------+-------+-------+-------+-------+
 779  * | Attr7 | Attr6 | Attr5 | Attr4 | Attr3 | Attr2 | Attr1 | Attr0 |
 780  * +-------+-------+-------+-------+-------+-------+-------+-------+
 781  *
 782  */
 783
 784 #define MAIR_ATTR_SHIFT(x)          (8*(x))
 785
 786 /* Strongly ordered or device memory attributes */
 787 #define MAIR_OUTER_STRONGLY_ORDERED 0x0
 788 #define MAIR_OUTER_DEVICE           0x0
 789
 790 #define MAIR_INNER_STRONGLY_ORDERED 0x0
 791 #define MAIR_INNER_DEVICE           0x4
 792
 793 /* Normal memory attributes */
 794 #define MAIR_OUTER_NON_CACHEABLE    0x40
 795 #define MAIR_OUTER_WRITE_THROUGH    0x80
 796 #define MAIR_OUTER_WRITE_BACK       0xc0
 797
 798 #define MAIR_INNER_NON_CACHEABLE    0x4
 799 #define MAIR_INNER_WRITE_THROUGH    0x8
 800 #define MAIR_INNER_WRITE_BACK       0xc
 801
 802 /* Allocate policy for cacheable memory */
 803 #define MAIR_OUTER_WRITE_ALLOCATE   0x10
 804 #define MAIR_OUTER_READ_ALLOCATE    0x20
 805
 806 #define MAIR_INNER_WRITE_ALLOCATE   0x1
 807 #define MAIR_INNER_READ_ALLOCATE    0x2
 808
 809 /* Memory Atribute Encoding */
 810
 811 /*
 812  * Device memory types:
 813  * G (gathering): multiple reads/writes can be combined
 814  * R (reordering): reads or writes may reach device out of program order
 815  * E (early-acknowledge): writes may return immediately (e.g. PCIe posted writes)
 816  */
 817 #define MAIR_DISABLE                   0x00 /* Device Memory, nGnRnE (strongly ordered) */
 818 #define MAIR_POSTED                    0x04 /* Device Memory, nGnRE (strongly ordered, posted writes) */
 819 #define MAIR_POSTED_REORDERED          0x08 /* Device Memory, nGRE (reorderable, posted writes) */
 820 #define MAIR_POSTED_COMBINED_REORDERED 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes) */
 821 #define MAIR_WRITECOMB                 0x44 /* Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable */
 822 #define MAIR_WRITETHRU                 0xBB /* Normal Memory, Outer Write-through, Inner Write-through */
 823 #define MAIR_WRITEBACK                 0xFF /* Normal Memory, Outer Write-back, Inner Write-back */
 824 #define MAIR_INNERWRITEBACK            0x4F /* Normal Memory, Outer Non-Cacheable, Inner Write-back */
 825
 826
 827 /*
 828  * ARM 4-level Page Table support - 2*1024TB (2^48) of address space
 829  */
 830
 831
 832 /*
 833  *  Memory Attribute Index
 834  */
 835 #define CACHE_ATTRINDX_WRITEBACK                 0x0 /* cache enabled, buffer enabled  (normal memory) */
 836 #define CACHE_ATTRINDX_WRITECOMB                 0x1 /* no cache, buffered writes (normal memory) */
 837 #define CACHE_ATTRINDX_WRITETHRU                 0x2 /* cache enabled, buffer disabled (normal memory) */
 838 #define CACHE_ATTRINDX_DISABLE                   0x3 /* no cache, no buffer (device memory) */
 839 #define CACHE_ATTRINDX_INNERWRITEBACK            0x4 /* inner cache enabled, buffer enabled, write allocate (normal memory) */
 840 #define CACHE_ATTRINDX_POSTED                    0x5 /* no cache, no buffer, posted writes (device memory) */
 841 #define CACHE_ATTRINDX_POSTED_REORDERED          0x6 /* no cache, reorderable access, posted writes (device memory) */
 842 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory) */
 843 #define CACHE_ATTRINDX_DEFAULT                   CACHE_ATTRINDX_WRITEBACK
 844
 845
 846 /*
 847  * Access protection bit values (TTEs and PTEs), stage 1
 848  *
 849  * Bit 1 controls access type (1=RO, 0=RW), bit 0 controls user (1=access, 0=no access)
 850  */
 851 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */
 852 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */
 853 #define AP_RONA 0x2 /* priv=read-only, user=no-access */
 854 #define AP_RORO 0x3 /* priv=read-only, user=read-only */
 855 #define AP_MASK 0x3 /* mask to find ap bits */
 856
 857 /*
 858  * Shareability attributes
 859  */
 860 #define SH_NONE         0x0 /* Non shareable  */
 861 #define SH_NONE         0x0 /* Device shareable */
 862 #define SH_DEVICE       0x2 /* Normal memory Inner non shareable - Outer non shareable */
 863 #define SH_OUTER_MEMORY 0x2 /* Normal memory Inner shareable - Outer shareable */
 864 #define SH_INNER_MEMORY 0x3 /* Normal memory Inner shareable - Outer non shareable */
 865
 866
 867 /*
 868  * ARM Page Granule
 869  */
 870 #ifdef __ARM_16K_PG__
 871 #define ARM_PGSHIFT 14
 872 #else
 873 #define ARM_PGSHIFT 12
 874 #endif
 875 #define ARM_PGBYTES (1 << ARM_PGSHIFT)
 876 #define ARM_PGMASK  (ARM_PGBYTES-1)
 877
 878 /*
 879  *  L0 Translation table
 880  *
 881  *  4KB granule size:
 882  *    Each translation table is 4KB
 883  *    512 64-bit entries of 512GB (2^39) of address space.
 884  *    Covers 256TB (2^48) of address space.
 885  *
 886  *  16KB granule size:
 887  *    Each translation table is 16KB
 888  *    2 64-bit entries of 128TB (2^47) of address space.
 889  *    Covers 256TB (2^48) of address space.
 890  */
 891
 892 /* 16K L0 */
 893 #define ARM_16K_TT_L0_SIZE       0x0000800000000000ULL /* size of area covered by a tte */
 894 #define ARM_16K_TT_L0_OFFMASK    0x00007fffffffffffULL /* offset within an L0 entry */
 895 #define ARM_16K_TT_L0_SHIFT      47                    /* page descriptor shift */
 896 #define ARM_16K_TT_L0_INDEX_MASK 0x0000800000000000ULL /* mask for getting index in L0 table from virtual address */
 897
 898 /* 4K L0 */
 899 #define ARM_4K_TT_L0_SIZE       0x0000008000000000ULL /* size of area covered by a tte */
 900 #define ARM_4K_TT_L0_OFFMASK    0x0000007fffffffffULL /* offset within an L0 entry */
 901 #define ARM_4K_TT_L0_SHIFT      39                    /* page descriptor shift */
 902 #define ARM_4K_TT_L0_INDEX_MASK 0x0000ff8000000000ULL /* mask for getting index in L0 table from virtual address */
 903
 904 /*
 905  *  L1 Translation table
 906  *
 907  *  4KB granule size:
 908  *    Each translation table is 4KB
 909  *    512 64-bit entries of 1GB (2^30) of address space.
 910  *    Covers 512GB (2^39) of address space.
 911  *
 912  *  16KB granule size:
 913  *    Each translation table is 16KB
 914  *    2048 64-bit entries of 64GB (2^36) of address space.
 915  *    Covers 128TB (2^47) of address space.
 916  */
 917
 918 /* 16K L1 */
 919 #define ARM_16K_TT_L1_SIZE       0x0000001000000000ULL /* size of area covered by a tte */
 920 #define ARM_16K_TT_L1_OFFMASK    0x0000000fffffffffULL /* offset within an L1 entry */
 921 #define ARM_16K_TT_L1_SHIFT      36                    /* page descriptor shift */
 922 #if __ARM64_PMAP_SUBPAGE_L1__ && __ARM_16K_PG__
 923 /* This config supports 512GB per TTBR. */
 924 #define ARM_16K_TT_L1_INDEX_MASK 0x0000007000000000ULL /* mask for getting index into L1 table from virtual address */
 925 #else /* __ARM64_PMAP_SUBPAGE_L1__ */
 926 #define ARM_16K_TT_L1_INDEX_MASK 0x00007ff000000000ULL /* mask for getting index into L1 table from virtual address */
 927 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */
 928
 929 /* 4K L1 */
 930 #define ARM_4K_TT_L1_SIZE       0x0000000040000000ULL /* size of area covered by a tte */
 931 #define ARM_4K_TT_L1_OFFMASK    0x000000003fffffffULL /* offset within an L1 entry */
 932 #define ARM_4K_TT_L1_SHIFT      30                    /* page descriptor shift */
 933 #if __ARM64_PMAP_SUBPAGE_L1__ && !__ARM_16K_PG__
 934 /* This config supports 256GB per TTBR. */
 935 #define ARM_4K_TT_L1_INDEX_MASK 0x0000003fc0000000ULL /* mask for getting index into L1 table from virtual address */
 936 #else /* __ARM64_PMAP_SUBPAGE_L1__ */
 937 #define ARM_4K_TT_L1_INDEX_MASK 0x0000007fc0000000ULL /* mask for getting index into L1 table from virtual address */
 938 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */
 939
 940 /* some sugar for getting pointers to page tables and entries */
 941
 942 #define L1_TABLE_INDEX(va) (((va) & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT)
 943 #define L2_TABLE_INDEX(va) (((va) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT)
 944 #define L3_TABLE_INDEX(va) (((va) & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT)
 945
 946 #define L2_TABLE_VA(tte)  ((tt_entry_t*) phystokv((*(tte)) & ARM_TTE_TABLE_MASK))
 947 #define L3_TABLE_VA(tte2) ((pt_entry_t*) phystokv((*(tte2)) & ARM_TTE_TABLE_MASK))
 948
 949 /*
 950  *  L2 Translation table
 951  *
 952  *  4KB granule size:
 953  *    Each translation table is 4KB
 954  *    512 64-bit entries of 2MB (2^21) of address space.
 955  *    Covers 1GB (2^30) of address space.
 956  *
 957  *  16KB granule size:
 958  *    Each translation table is 16KB
 959  *    2048 64-bit entries of 32MB (2^25) of address space.
 960  *    Covers 64GB (2^36) of address space.
 961  */
 962
 963 /* 16K L2 */
 964 #define ARM_16K_TT_L2_SIZE       0x0000000002000000ULL /* size of area covered by a tte */
 965 #define ARM_16K_TT_L2_OFFMASK    0x0000000001ffffffULL /* offset within an L2 entry */
 966 #define ARM_16K_TT_L2_SHIFT      25                    /* page descriptor shift */
 967 #define ARM_16K_TT_L2_INDEX_MASK 0x0000000ffe000000ULL /* mask for getting index in L2 table from virtual address */
 968
 969 /* 4K L2 */
 970 #define ARM_4K_TT_L2_SIZE       0x0000000000200000ULL /* size of area covered by a tte */
 971 #define ARM_4K_TT_L2_OFFMASK    0x00000000001fffffULL /* offset within an L2 entry */
 972 #define ARM_4K_TT_L2_SHIFT      21                    /* page descriptor shift */
 973 #define ARM_4K_TT_L2_INDEX_MASK 0x000000003fe00000ULL /* mask for getting index in L2 table from virtual address */
 974
 975 /*
 976  *  L3 Translation table
 977  *
 978  *  4KB granule size:
 979  *    Each translation table is 4KB
 980  *    512 64-bit entries of 4KB (2^12) of address space.
 981  *    Covers 2MB (2^21) of address space.
 982  *
 983  *  16KB granule size:
 984  *    Each translation table is 16KB
 985  *    2048 64-bit entries of 16KB (2^14) of address space.
 986  *    Covers 32MB (2^25) of address space.
 987  */
 988
 989 /* 16K L3 */
 990 #define ARM_16K_TT_L3_SIZE       0x0000000000004000ULL /* size of area covered by a tte */
 991 #define ARM_16K_TT_L3_OFFMASK    0x0000000000003fffULL /* offset within L3 PTE */
 992 #define ARM_16K_TT_L3_SHIFT      14                    /* page descriptor shift */
 993 #define ARM_16K_TT_L3_INDEX_MASK 0x0000000001ffc000ULL /* mask for page descriptor index */
 994
 995 /* 4K L3 */
 996 #define ARM_4K_TT_L3_SIZE       0x0000000000001000ULL /* size of area covered by a tte */
 997 #define ARM_4K_TT_L3_OFFMASK    0x0000000000000fffULL /* offset within L3 PTE */
 998 #define ARM_4K_TT_L3_SHIFT      12                    /* page descriptor shift */
 999 #define ARM_4K_TT_L3_INDEX_MASK 0x00000000001ff000ULL /* mask for page descriptor index */
1000
1001 #ifdef __ARM_16K_PG__
1002
1003 /* Native L0 defines */
1004 #define ARM_TT_L0_SIZE       ARM_16K_TT_L0_SIZE
1005 #define ARM_TT_L0_OFFMASK    ARM_16K_TT_L0_OFFMASK
1006 #define ARM_TT_L0_SHIFT      ARM_16K_TT_L0_SHIFT
1007 #define ARM_TT_L0_INDEX_MASK ARM_16K_TT_L0_INDEX_MASK
1008
1009 /* Native L1 defines */
1010 #define ARM_TT_L1_SIZE       ARM_16K_TT_L1_SIZE
1011 #define ARM_TT_L1_OFFMASK    ARM_16K_TT_L1_OFFMASK
1012 #define ARM_TT_L1_SHIFT      ARM_16K_TT_L1_SHIFT
1013 #define ARM_TT_L1_INDEX_MASK ARM_16K_TT_L1_INDEX_MASK
1014
1015 /* Native L2 defines */
1016 #define ARM_TT_L2_SIZE       ARM_16K_TT_L2_SIZE
1017 #define ARM_TT_L2_OFFMASK    ARM_16K_TT_L2_OFFMASK
1018 #define ARM_TT_L2_SHIFT      ARM_16K_TT_L2_SHIFT
1019 #define ARM_TT_L2_INDEX_MASK ARM_16K_TT_L2_INDEX_MASK
1020
1021 /* Native L3 defines */
1022 #define ARM_TT_L3_SIZE       ARM_16K_TT_L3_SIZE
1023 #define ARM_TT_L3_OFFMASK    ARM_16K_TT_L3_OFFMASK
1024 #define ARM_TT_L3_SHIFT      ARM_16K_TT_L3_SHIFT
1025 #define ARM_TT_L3_INDEX_MASK ARM_16K_TT_L3_INDEX_MASK
1026
1027 #else /* !__ARM_16K_PG__ */
1028
1029 /* Native L0 defines */
1030 #define ARM_TT_L0_SIZE       ARM_4K_TT_L0_SIZE
1031 #define ARM_TT_L0_OFFMASK    ARM_4K_TT_L0_OFFMASK
1032 #define ARM_TT_L0_SHIFT      ARM_4K_TT_L0_SHIFT
1033 #define ARM_TT_L0_INDEX_MASK ARM_4K_TT_L0_INDEX_MASK
1034
1035 /* Native L1 defines */
1036 #define ARM_TT_L1_SIZE       ARM_4K_TT_L1_SIZE
1037 #define ARM_TT_L1_OFFMASK    ARM_4K_TT_L1_OFFMASK
1038 #define ARM_TT_L1_SHIFT      ARM_4K_TT_L1_SHIFT
1039 #define ARM_TT_L1_INDEX_MASK ARM_4K_TT_L1_INDEX_MASK
1040
1041 /* Native L2 defines */
1042 #define ARM_TT_L2_SIZE       ARM_4K_TT_L2_SIZE
1043 #define ARM_TT_L2_OFFMASK    ARM_4K_TT_L2_OFFMASK
1044 #define ARM_TT_L2_SHIFT      ARM_4K_TT_L2_SHIFT
1045 #define ARM_TT_L2_INDEX_MASK ARM_4K_TT_L2_INDEX_MASK
1046
1047 /* Native L3 defines */
1048 #define ARM_TT_L3_SIZE       ARM_4K_TT_L3_SIZE
1049 #define ARM_TT_L3_OFFMASK    ARM_4K_TT_L3_OFFMASK
1050 #define ARM_TT_L3_SHIFT      ARM_4K_TT_L3_SHIFT
1051 #define ARM_TT_L3_INDEX_MASK ARM_4K_TT_L3_INDEX_MASK
1052
1053 #endif /* !__ARM_16K_PG__ */
1054
1055 /*
1056  * Convenience definitions for:
1057  *   ARM_TT_LEAF: The last level of the configured page table format.
1058  *   ARM_TT_TWIG: The second to last level of the configured page table format.
1059  *   ARM_TT_ROOT: The first level of the configured page table format.
1060  *
1061  *   My apologies to any botanists who may be reading this.
1062  */
1063 #define ARM_TT_LEAF_SIZE       ARM_TT_L3_SIZE
1064 #define ARM_TT_LEAF_OFFMASK    ARM_TT_L3_OFFMASK
1065 #define ARM_TT_LEAF_SHIFT      ARM_TT_L3_SHIFT
1066 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L3_INDEX_MASK
1067
1068 #define ARM_TT_TWIG_SIZE       ARM_TT_L2_SIZE
1069 #define ARM_TT_TWIG_OFFMASK    ARM_TT_L2_OFFMASK
1070 #define ARM_TT_TWIG_SHIFT      ARM_TT_L2_SHIFT
1071 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L2_INDEX_MASK
1072
1073 #define ARM_TT_ROOT_SIZE       ARM_TT_L1_SIZE
1074 #define ARM_TT_ROOT_OFFMASK    ARM_TT_L1_OFFMASK
1075 #define ARM_TT_ROOT_SHIFT      ARM_TT_L1_SHIFT
1076 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK
1077
1078 /*
1079  * 4KB granule size:
1080  *
1081  * Level 0 Translation Table Entry
1082  *
1083  *  63 62 61 60  59 58   52 51  48 47                  12 11    2 1 0
1084  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1085  * |NS|  AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V|
1086  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1087  *
1088  * Level 1 Translation Table Entry
1089  *
1090  *  63 62 61 60  59 58   52 51  48 47                  12 11    2 1 0
1091  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1092  * |NS|  AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V|
1093  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1094  *
1095  * Level 1 Translation Block Entry
1096  *
1097  *  63 59 58  55 54  53   52 51  48 47                  30 29  12 11 10 9  8 7  6  5 4     2 1 0
1098  * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
1099  * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:30] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V|
1100  * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
1101  *
1102  * Level 2 Translation Table Entry
1103  *
1104  *  63 62 61 60  59 58   52 51  48 47                  12 11    2 1 0
1105  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1106  * |NS|  AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V|
1107  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1108  *
1109  * Level 2 Translation Block Entry
1110  *
1111  *  63 59 58  55 54  53   52 51  48 47                  21 20  12 11 10 9  8 7  6  5 4     2 1 0
1112  * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
1113  * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:21] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V|
1114  * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
1115  *
1116  * 16KB granule size:
1117  *
1118  * Level 0 Translation Table Entry
1119  *
1120  *  63 62 61 60  59 58   52 51  48 47                  14 13    2 1 0
1121  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1122  * |NS|  AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V|
1123  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1124  *
1125  * Level 1 Translation Table Entry
1126  *
1127  *  63 62 61 60  59 58   52 51  48 47                  14 13    2 1 0
1128  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1129  * |NS|  AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V|
1130  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1131  *
1132  * Level 2 Translation Table Entry
1133  *
1134  *  63 62 61 60  59 58   52 51  48 47                  14 13    2 1 0
1135  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1136  * |NS|  AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V|
1137  * +--+-----+--+---+-------+------+----------------------+-------+-+-+
1138  *
1139  * Level 2 Translation Block Entry
1140  *
1141  *  63 59 58  55 54  53   52 51  48 47                  25 24  12 11 10 9  8 7  6  5 4     2 1 0
1142  * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
1143  * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:25] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V|
1144  * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
1145  *
1146  * where:
1147  *   nG:      notGlobal bit
1148  *   SH:      Shareability field
1149  *   AP:      access protection
1150  *   XN:      eXecute Never bit
1151  *   PXN:     Privilege eXecute Never bit
1152  *   NS:      Non-Secure bit
1153  *   HINT:    16 entry continuguous output hint
1154  *   AttrIdx: Memory Attribute Index
1155  */
1156
1157 #define TTE_SHIFT                   3                              /* shift width of a tte (sizeof(tte) == (1 << TTE_SHIFT)) */
1158 #ifdef __ARM_16K_PG__
1159 #define TTE_PGENTRIES               (16384 >> TTE_SHIFT)           /* number of ttes per page */
1160 #else
1161 #define TTE_PGENTRIES               (4096 >> TTE_SHIFT)            /* number of ttes per page */
1162 #endif
1163
1164 #define ARM_TTE_MAX                 (TTE_PGENTRIES)
1165
1166 #define ARM_TTE_EMPTY               0x0000000000000000ULL          /* unasigned - invalid entry */
1167 #define ARM_TTE_TYPE_FAULT          0x0000000000000000ULL          /* unasigned - invalid entry */
1168
1169 #define ARM_TTE_VALID               0x0000000000000001ULL          /* valid entry */
1170
1171 #define ARM_TTE_TYPE_MASK           0x0000000000000002ULL          /* mask for extracting the type */
1172 #define ARM_TTE_TYPE_TABLE          0x0000000000000002ULL          /* page table type */
1173 #define ARM_TTE_TYPE_BLOCK          0x0000000000000000ULL          /* block entry type */
1174 #define ARM_TTE_TYPE_L3BLOCK        0x0000000000000002ULL
1175 #define ARM_TTE_TYPE_MASK           0x0000000000000002ULL          /* mask for extracting the type */
1176
1177 #ifdef __ARM_16K_PG__
1178 /*
1179  * Note that L0/L1 block entries are disallowed for the 16KB granule size; what
1180  * are we doing with these?
1181  */
1182 #define ARM_TTE_BLOCK_SHIFT         12                             /* entry shift for a 16KB L3 TTE entry */
1183 #define ARM_TTE_BLOCK_L0_SHIFT      ARM_TT_L0_SHIFT                /* block shift for 128TB section */
1184 #define ARM_TTE_BLOCK_L1_MASK       0x0000fff000000000ULL          /* mask to extract phys address from L1 block entry */
1185 #define ARM_TTE_BLOCK_L1_SHIFT      ARM_TT_L1_SHIFT                /* block shift for 64GB section */
1186 #define ARM_TTE_BLOCK_L2_MASK       0x0000fffffe000000ULL          /* mask to extract phys address from Level 2 Translation Block entry */
1187 #define ARM_TTE_BLOCK_L2_SHIFT      ARM_TT_L2_SHIFT                /* block shift for 32MB section */
1188 #else
1189 #define ARM_TTE_BLOCK_SHIFT         12                             /* entry shift for a 4KB L3 TTE entry */
1190 #define ARM_TTE_BLOCK_L0_SHIFT      ARM_TT_L0_SHIFT                /* block shift for 2048GB section */
1191 #define ARM_TTE_BLOCK_L1_MASK       0x0000ffffc0000000ULL          /* mask to extract phys address from L1 block entry */
1192 #define ARM_TTE_BLOCK_L1_SHIFT      ARM_TT_L1_SHIFT                /* block shift for 1GB section */
1193 #define ARM_TTE_BLOCK_L2_MASK       0x0000ffffffe00000ULL          /* mask to extract phys address from Level 2 Translation Block entry */
1194 #define ARM_TTE_BLOCK_L2_SHIFT      ARM_TT_L2_SHIFT                /* block shift for 2MB section */
1195 #endif
1196
1197 #define ARM_TTE_BLOCK_APSHIFT       6
1198 #define ARM_TTE_BLOCK_AP(x)         ((x)<<ARM_TTE_BLOCK_APSHIFT)   /* access protection */
1199 #define ARM_TTE_BLOCK_APMASK        (0x3 << ARM_TTE_BLOCK_APSHIFT)
1200
1201 #define ARM_TTE_BLOCK_ATTRINDX(x)   ((x) << 2)                     /* memory attributes index */
1202 #define ARM_TTE_BLOCK_ATTRINDXMASK  (0x7ULL << 2)                  /* mask memory attributes index */
1203
1204 #define ARM_TTE_BLOCK_SH(x)         ((x) << 8)                     /* access shared */
1205 #define ARM_TTE_BLOCK_SHMASK        (0x3ULL << 8)                  /* mask access shared */
1206
1207 #define ARM_TTE_BLOCK_AF            0x0000000000000400ULL          /* value for access */
1208 #define ARM_TTE_BLOCK_AFMASK        0x0000000000000400ULL          /* access mask */
1209
1210 #define ARM_TTE_BLOCK_NG            0x0000000000000800ULL          /* value for a global mapping */
1211 #define ARM_TTE_BLOCK_NG_MASK       0x0000000000000800ULL          /* notGlobal mapping mask */
1212
1213 #define ARM_TTE_BLOCK_NS            0x0000000000000020ULL          /* value for a secure mapping */
1214 #define ARM_TTE_BLOCK_NS_MASK       0x0000000000000020ULL          /* notSecure mapping mask */
1215
1216 #define ARM_TTE_BLOCK_PNX           0x0020000000000000ULL          /* value for privilege no execute bit */
1217 #define ARM_TTE_BLOCK_PNXMASK       0x0020000000000000ULL          /* privilege no execute mask */
1218
1219 #define ARM_TTE_BLOCK_NX            0x0040000000000000ULL          /* value for no execute */
1220 #define ARM_TTE_BLOCK_NXMASK        0x0040000000000000ULL          /* no execute mask */
1221
1222 #define ARM_TTE_BLOCK_WIRED         0x0400000000000000ULL          /* value for software wired bit */
1223 #define ARM_TTE_BLOCK_WIREDMASK     0x0400000000000000ULL          /* software wired mask */
1224
1225 #define ARM_TTE_BLOCK_WRITEABLE     0x0800000000000000ULL          /* value for software writeable bit */
1226 #define ARM_TTE_BLOCK_WRITEABLEMASK 0x0800000000000000ULL          /* software writeable mask */
1227
1228 #define ARM_TTE_TABLE_MASK          0x0000fffffffff000ULL          /* mask for extracting pointer to next table (works at any level) */
1229
1230 #define ARM_TTE_TABLE_APSHIFT       61
1231 #define ARM_TTE_TABLE_AP(x)         ((x)<<TTE_BLOCK_APSHIFT)       /* access protection */
1232
1233 #define ARM_TTE_TABLE_NS            0x8000000000000020ULL          /* value for a secure mapping */
1234 #define ARM_TTE_TABLE_NS_MASK       0x8000000000000020ULL          /* notSecure mapping mask */
1235
1236 #define ARM_TTE_TABLE_XN            0x1000000000000000ULL          /* value for no execute */
1237 #define ARM_TTE_TABLE_XNMASK        0x1000000000000000ULL          /* no execute mask */
1238
1239 #define ARM_TTE_TABLE_PXN           0x0800000000000000ULL          /* value for privilege no execute bit */
1240 #define ARM_TTE_TABLE_PXNMASK       0x0800000000000000ULL          /* privilege execute mask */
1241
1242 #if __ARM_KERNEL_PROTECT__
1243 #define ARM_TTE_BOOT_BLOCK \
1244         (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \
1245          ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF | ARM_TTE_BLOCK_NG)
1246 #else /* __ARM_KERNEL_PROTECT__ */
1247 #define ARM_TTE_BOOT_BLOCK \
1248         (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \
1249          ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF)
1250 #endif /* __ARM_KERNEL_PROTECT__ */
1251
1252 #define ARM_TTE_BOOT_TABLE (ARM_TTE_TYPE_TABLE | ARM_TTE_VALID )
1253 /*
1254  *  L3 Translation table
1255  *
1256  *  4KB granule size:
1257  *    Each translation table is 4KB
1258  *    512 64-bit entries of 4KB (2^12) of address space.
1259  *    Covers 2MB (2^21) of address space.
1260  *
1261  *  16KB granule size:
1262  *    Each translation table is 16KB
1263  *    2048 64-bit entries of 16KB (2^14) of address space.
1264  *    Covers 32MB (2^25) of address space.
1265  */
1266
1267 #ifdef __ARM_16K_PG__
1268 #define ARM_PTE_SIZE    0x0000000000004000ULL /* size of area covered by a tte */
1269 #define ARM_PTE_OFFMASK 0x0000000000003fffULL /* offset within pte area */
1270 #define ARM_PTE_SHIFT   14                    /* page descriptor shift */
1271 #define ARM_PTE_MASK    0x0000ffffffffc000ULL /* mask for output address in PTE */
1272 #else
1273 #define ARM_PTE_SIZE    0x0000000000001000ULL /* size of area covered by a tte */
1274 #define ARM_PTE_OFFMASK 0x0000000000000fffULL /* offset within pte area */
1275 #define ARM_PTE_SHIFT   12                    /* page descriptor shift */
1276 #define ARM_PTE_MASK    0x0000fffffffff000ULL /* mask for output address in PTE */
1277 #endif
1278
1279 #define ARM_TTE_PA_MASK 0x0000fffffffff000ULL
1280
1281 /*
1282  * L3 Page table entries
1283  *
1284  * The following page table entry types are possible:
1285  *
1286  * fault page entry
1287  *  63                            2  0
1288  * +------------------------------+--+
1289  * |    ignored                   |00|
1290  * +------------------------------+--+
1291  *
1292  *
1293  *  63 59 58  55 54  53   52 51  48 47                  12 11 10 9  8 7  6  5 4     2 1 0
1294  * +-----+------+--+---+----+------+----------------------+--+--+----+----+--+-------+-+-+
1295  * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:12] |nG|AF| SH | AP |NS|AttrIdx|1|V|
1296  * +-----+------+--+---+----+------+----------------------+--+--+----+----+--+-------+-+-+
1297  *
1298  * where:
1299  *   nG:      notGlobal bit
1300  *   SH:      Shareability field
1301  *   AP:      access protection
1302  *   XN:      eXecute Never bit
1303  *   PXN:     Privilege eXecute Never bit
1304  *   NS:      Non-Secure bit
1305  *   HINT:    16 entry continuguous output hint
1306  *   AttrIdx: Memory Attribute Index
1307  */
1308
1309 #define PTE_SHIFT               3                     /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */
1310 #ifdef __ARM_16K_PG__
1311 #define PTE_PGENTRIES           (16384 >> PTE_SHIFT)  /* number of ptes per page */
1312 #else
1313 #define PTE_PGENTRIES           (4096 >> PTE_SHIFT)   /* number of ptes per page */
1314 #endif
1315
1316 #define ARM_PTE_EMPTY           0x0000000000000000ULL /* unassigned - invalid entry */
1317
1318 /* markers for (invalid) PTE for a page sent to compressor */
1319 #define ARM_PTE_COMPRESSED      0x8000000000000000ULL /* compressed... */
1320 #define ARM_PTE_COMPRESSED_ALT  0x4000000000000000ULL /* ... and was "alt_acct" */
1321 #define ARM_PTE_COMPRESSED_MASK 0xC000000000000000ULL
1322
1323 #define ARM_PTE_IS_COMPRESSED(x, p) \
1324         ((((x) & 0x3) == 0) && /* PTE is not valid... */                      \
1325          ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */      \
1326          ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */       \
1327          (panic("compressed PTE %p 0x%llx has extra bits 0x%llx: corrupted?", \
1328                 (p), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
1329
1330 #define ARM_PTE_TYPE               0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */
1331 #define ARM_PTE_TYPE_VALID         0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */
1332 #define ARM_PTE_TYPE_FAULT         0x0000000000000000ULL /* invalid L3 entry */
1333 #define ARM_PTE_TYPE_MASK          0x0000000000000002ULL /* mask to get pte type */
1334
1335 /* This mask works for both 16K and 4K pages because bits 12-13 will be zero in 16K pages */
1336 #define ARM_PTE_PAGE_MASK          0x0000FFFFFFFFF000ULL /* output address mask for page */
1337 #define ARM_PTE_PAGE_SHIFT         12                    /* page shift for the output address in the entry */
1338
1339 #define ARM_PTE_AP(x)              ((x) << 6)            /* access protections */
1340 #define ARM_PTE_APMASK             (0x3ULL << 6)         /* mask access protections */
1341 #define ARM_PTE_EXTRACT_AP(x)      (((x) >> 6) & 0x3ULL) /* extract access protections from PTE */
1342
1343 #define ARM_PTE_ATTRINDX(x)        ((x) << 2)            /* memory attributes index */
1344 #define ARM_PTE_ATTRINDXMASK       (0x7ULL << 2)         /* mask memory attributes index */
1345
1346 #define ARM_PTE_SH(x)              ((x) << 8)            /* access shared */
1347 #define ARM_PTE_SHMASK             (0x3ULL << 8)         /* mask access shared */
1348
1349 #define ARM_PTE_AF                 0x0000000000000400ULL /* value for access */
1350 #define ARM_PTE_AFMASK             0x0000000000000400ULL /* access mask */
1351
1352 #define ARM_PTE_NG                 0x0000000000000800ULL /* value for a global mapping */
1353 #define ARM_PTE_NG_MASK            0x0000000000000800ULL /* notGlobal mapping mask */
1354
1355 #define ARM_PTE_NS                 0x0000000000000020ULL /* value for a secure mapping */
1356 #define ARM_PTE_NS_MASK            0x0000000000000020ULL /* notSecure mapping mask */
1357
1358 #define ARM_PTE_HINT               0x0010000000000000ULL /* value for contiguous entries hint */
1359 #define ARM_PTE_HINT_MASK          0x0010000000000000ULL /* mask for contiguous entries hint */
1360
1361 #if __ARM_16K_PG__
1362 #define ARM_PTE_HINT_ENTRIES       128ULL                /* number of entries the hint covers */
1363 #define ARM_PTE_HINT_ENTRIES_SHIFT 7ULL                  /* shift to construct the number of entries */
1364 #define ARM_PTE_HINT_ADDR_MASK     0x0000FFFFFFE00000ULL /* mask to extract the starting hint address */
1365 #define ARM_PTE_HINT_ADDR_SHIFT    21                    /* shift for the hint address */
1366 #define ARM_KVA_HINT_ADDR_MASK     0xFFFFFFFFFFE00000ULL /* mask to extract the starting hint address */
1367 #else
1368 #define ARM_PTE_HINT_ENTRIES       16ULL                 /* number of entries the hint covers */
1369 #define ARM_PTE_HINT_ENTRIES_SHIFT 4ULL                  /* shift to construct the number of entries */
1370 #define ARM_PTE_HINT_ADDR_MASK     0x0000FFFFFFFF0000ULL /* mask to extract the starting hint address */
1371 #define ARM_PTE_HINT_ADDR_SHIFT    16                    /* shift for the hint address */
1372 #define ARM_KVA_HINT_ADDR_MASK     0xFFFFFFFFFFFF0000ULL /* mask to extract the starting hint address */
1373 #endif
1374
1375 #define ARM_PTE_PNX                0x0020000000000000ULL /* value for privilege no execute bit */
1376 #define ARM_PTE_PNXMASK            0x0020000000000000ULL /* privilege no execute mask */
1377
1378 #define ARM_PTE_NX                 0x0040000000000000ULL /* value for no execute bit */
1379 #define ARM_PTE_NXMASK             0x0040000000000000ULL /* no execute mask */
1380
1381 #define ARM_PTE_WIRED              0x0400000000000000ULL /* value for software wired bit */
1382 #define ARM_PTE_WIRED_MASK         0x0400000000000000ULL /* software wired mask */
1383
1384 #define ARM_PTE_WRITEABLE          0x0800000000000000ULL /* value for software writeable bit */
1385 #define ARM_PTE_WRITEABLE_MASK     0x0800000000000000ULL /* software writeable mask */
1386
1387 #if CONFIG_PGTRACE
1388 #define ARM_PTE_PGTRACE            0x0200000000000000ULL /* value for software trace bit */
1389 #define ARM_PTE_PGTRACE_MASK       0x0200000000000000ULL /* software trace mask */
1390 #endif
1391
1392 #define ARM_PTE_BOOT_PAGE_BASE \
1393         (ARM_PTE_TYPE_VALID | ARM_PTE_SH(SH_OUTER_MEMORY) |       \
1394          ARM_PTE_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_PTE_AF)
1395
1396 #if __ARM_KERNEL_PROTECT__
1397 #define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE | ARM_PTE_NG)
1398 #else /* __ARM_KERNEL_PROTECT__ */
1399 #define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE)
1400 #endif /* __ARM_KERNEL_PROTECT__ */
1401
1402 /*
1403  * TLBI appers to only deal in 4KB page addresses, so give
1404  * it an explicit shift of 12.
1405  */
1406 #define TLBI_ADDR_SHIFT (0)
1407 #define TLBI_ADDR_SIZE  (44)
1408 #define TLBI_ADDR_MASK  ((1ULL << TLBI_ADDR_SIZE) - 1)
1409 #define TLBI_ASID_SHIFT (48)
1410 #define TLBI_ASID_SIZE  (16)
1411 #define TLBI_ASID_MASK  (((1ULL << TLBI_ASID_SIZE) - 1))
1412
1413 #define RTLBI_ADDR_SIZE (37)
1414 #define RTLBI_ADDR_MASK ((1ULL << RTLBI_ADDR_SIZE) - 1)
1415 #define RTLBI_ADDR_SHIFT ARM_TT_L3_SHIFT
1416 #define RTLBI_TG(_page_shift_) ((uint64_t)((((_page_shift_) - 12) >> 1) + 1) << 46)
1417 #define RTLBI_SCALE_SHIFT (44)
1418 #define RTLBI_NUM_SHIFT (39)
1419
1420 /*
1421  * Exception Syndrome Register
1422  *
1423  *  31  26 25 24               0
1424  * +------+--+------------------+
1425  * |  EC  |IL|       ISS        |
1426  * +------+--+------------------+
1427  *
1428  * EC  - Exception Class
1429  * IL  - Instruction Length
1430  * ISS - Instruction Specific Syndrome
1431  *
1432  * Note: The ISS can have many forms. These are defined separately below.
1433  */
1434
1435 #define ESR_EC_SHIFT           26
1436 #define ESR_EC_MASK            (0x3FULL << ESR_EC_SHIFT)
1437 #define ESR_EC(x)              ((x & ESR_EC_MASK) >> ESR_EC_SHIFT)
1438
1439 #define ESR_IL_SHIFT           25
1440 #define ESR_IL                 (1 << ESR_IL_SHIFT)
1441
1442 #define ESR_INSTR_IS_2BYTES(x) (!(x & ESR_IL))
1443
1444 #define ESR_ISS_MASK           0x01FFFFFF
1445 #define ESR_ISS(x)             (x & ESR_ISS_MASK)
1446
1447 #ifdef __ASSEMBLER__
1448 /* Define only the classes we need to test in the exception vectors. */
1449 #define ESR_EC_IABORT_EL1      0x21
1450 #define ESR_EC_DABORT_EL1      0x25
1451 #define ESR_EC_SP_ALIGN        0x26
1452 #else
1453 typedef enum {
1454         ESR_EC_UNCATEGORIZED       = 0x00,
1455         ESR_EC_WFI_WFE             = 0x01,
1456         ESR_EC_MCR_MRC_CP15_TRAP   = 0x03,
1457         ESR_EC_MCRR_MRRC_CP15_TRAP = 0x04,
1458         ESR_EC_MCR_MRC_CP14_TRAP   = 0x05,
1459         ESR_EC_LDC_STC_CP14_TRAP   = 0x06,
1460         ESR_EC_TRAP_SIMD_FP        = 0x07,
1461         ESR_EC_PTRAUTH_INSTR_TRAP  = 0x09,
1462         ESR_EC_MCRR_MRRC_CP14_TRAP = 0x0c,
1463         ESR_EC_ILLEGAL_INSTR_SET   = 0x0e,
1464         ESR_EC_SVC_32              = 0x11,
1465         ESR_EC_SVC_64              = 0x15,
1466         ESR_EC_MSR_TRAP            = 0x18,
1467         ESR_EC_IABORT_EL0          = 0x20,
1468         ESR_EC_IABORT_EL1          = 0x21,
1469         ESR_EC_PC_ALIGN            = 0x22,
1470         ESR_EC_DABORT_EL0          = 0x24,
1471         ESR_EC_DABORT_EL1          = 0x25,
1472         ESR_EC_SP_ALIGN            = 0x26,
1473         ESR_EC_FLOATING_POINT_32   = 0x28,
1474         ESR_EC_FLOATING_POINT_64   = 0x2C,
1475         ESR_EC_BKPT_REG_MATCH_EL0  = 0x30, // Breakpoint Debug event taken to the EL from a lower EL.
1476         ESR_EC_BKPT_REG_MATCH_EL1  = 0x31, // Breakpoint Debug event taken to the EL from the EL.
1477         ESR_EC_SW_STEP_DEBUG_EL0   = 0x32, // Software Step Debug event taken to the EL from a lower EL.
1478         ESR_EC_SW_STEP_DEBUG_EL1   = 0x33, // Software Step Debug event taken to the EL from the EL.
1479         ESR_EC_WATCHPT_MATCH_EL0   = 0x34, // Watchpoint Debug event taken to the EL from a lower EL.
1480         ESR_EC_WATCHPT_MATCH_EL1   = 0x35, // Watchpoint Debug event taken to the EL from the EL.
1481         ESR_EC_BKPT_AARCH32        = 0x38,
1482         ESR_EC_BRK_AARCH64         = 0x3C,
1483 } esr_exception_class_t;
1484
1485 typedef enum {
1486         FSC_TRANSLATION_FAULT_L0   = 0x04,
1487         FSC_TRANSLATION_FAULT_L1   = 0x05,
1488         FSC_TRANSLATION_FAULT_L2   = 0x06,
1489         FSC_TRANSLATION_FAULT_L3   = 0x07,
1490         FSC_ACCESS_FLAG_FAULT_L1   = 0x09,
1491         FSC_ACCESS_FLAG_FAULT_L2   = 0x0A,
1492         FSC_ACCESS_FLAG_FAULT_L3   = 0x0B,
1493         FSC_PERMISSION_FAULT_L1    = 0x0D,
1494         FSC_PERMISSION_FAULT_L2    = 0x0E,
1495         FSC_PERMISSION_FAULT_L3    = 0x0F,
1496         FSC_SYNC_EXT_ABORT         = 0x10,
1497         FSC_ASYNC_EXT_ABORT        = 0x11,
1498         FSC_SYNC_EXT_ABORT_TT_L1   = 0x15,
1499         FSC_SYNC_EXT_ABORT_TT_L2   = 0x16,
1500         FSC_SYNC_EXT_ABORT_TT_L3   = 0x17,
1501         FSC_SYNC_PARITY            = 0x18,
1502         FSC_ASYNC_PARITY           = 0x19,
1503         FSC_SYNC_PARITY_TT_L1      = 0x1D,
1504         FSC_SYNC_PARITY_TT_L2      = 0x1E,
1505         FSC_SYNC_PARITY_TT_L3      = 0x1F,
1506         FSC_ALIGNMENT_FAULT        = 0x21,
1507         FSC_DEBUG_FAULT            = 0x22,
1508 } fault_status_t;
1509 #endif /* ASSEMBLER */
1510
1511 /*
1512  * Software step debug event ISS (EL1)
1513  *  24  23                6  5    0
1514  * +---+-----------------+--+------+
1515  * |ISV|00000000000000000|EX| IFSC |
1516  * +---+-----------------+--+------+
1517  *
1518  * where:
1519  *   ISV:  Instruction syndrome valid
1520  *   EX:   Exclusive access
1521  *   IFSC: Instruction Fault Status Code
1522  */
1523
1524 #define ISS_SSDE_ISV_SHIFT 24
1525 #define ISS_SSDE_ISV       (0x1 << ISS_SSDE_ISV_SHIFT)
1526
1527 #define ISS_SSDE_EX_SHIFT  6
1528 #define ISS_SSDE_EX        (0x1 << ISS_SSDE_EX_SHIFT)
1529
1530 #define ISS_SSDE_FSC_MASK  0x3F
1531 #define ISS_SSDE_FSC(x)    (x & ISS_SSDE_FSC_MASK)
1532
1533 /*
1534  * Instruction Abort ISS (EL1)
1535  *  24           10 9      5    0
1536  * +---------------+--+---+------+
1537  * |000000000000000|EA|000| IFSC |
1538  * +---------------+--+---+------+
1539  *
1540  * where:
1541  *   EA:   External Abort type
1542  *   IFSC: Instruction Fault Status Code
1543  */
1544
1545 #define ISS_IA_EA_SHIFT 9
1546 #define ISS_IA_EA       (0x1 << ISS_IA_EA_SHIFT)
1547
1548 #define ISS_IA_FSC_MASK 0x3F
1549 #define ISS_IA_FSC(x)   (x & ISS_IA_FSC_MASK)
1550
1551
1552 /*
1553  * Data Abort ISS (EL1)
1554  *
1555  *  24              9  8  7  6  5  0
1556  * +---------------+--+--+-+---+----+
1557  * |000000000000000|EA|CM|S1PTW|WnR|DFSC|
1558  * +---------------+--+--+-+---+----+
1559  *
1560  * where:
1561  *   EA:    External Abort type
1562  *   CM:    Cache Maintenance operation
1563  *   WnR:   Write not Read
1564  *   S1PTW: Stage 2 exception on Stage 1 page table walk
1565  *   DFSC:  Data Fault Status Code
1566  */
1567 #define ISS_DA_EA_SHIFT  9
1568 #define ISS_DA_EA        (0x1 << ISS_DA_EA_SHIFT)
1569
1570 #define ISS_DA_CM_SHIFT  8
1571 #define ISS_DA_CM        (0x1 << ISS_DA_CM_SHIFT)
1572
1573 #define ISS_DA_WNR_SHIFT 6
1574 #define ISS_DA_WNR       (0x1 << ISS_DA_WNR_SHIFT)
1575
1576 #define ISS_DA_S1PTW_SHIFT 7
1577 #define ISS_DA_S1PTW     (0x1 << ISS_DA_S1PTW_SHIFT)
1578
1579 #define ISS_DA_FSC_MASK  0x3F
1580 #define ISS_DA_FSC(x)    (x & ISS_DA_FSC_MASK)
1581
1582 /*
1583  * Floating Point Exception ISS (EL1)
1584  *
1585  * 24  23 22            8  7      4   3   2   1   0
1586  * +-+---+---------------+---+--+---+---+---+---+---+
1587  * |0|TFV|000000000000000|IDF|00|IXF|UFF|OFF|DZF|IOF|
1588  * +-+---+---------------+---+--+---+---+---+---+---+
1589  *
1590  * where:
1591  *   TFV: Trapped Fault Valid
1592  *   IDF: Input Denormal Exception
1593  *   IXF: Input Inexact Exception
1594  *   UFF: Underflow Exception
1595  *   OFF: Overflow Exception
1596  *   DZF: Divide by Zero Exception
1597  *   IOF: Invalid Operation Exception
1598  */
1599 #define ISS_FP_TFV_SHIFT 23
1600 #define ISS_FP_TFV       (0x1 << ISS_FP_TFV_SHIFT)
1601
1602 #define ISS_FP_IDF_SHIFT 7
1603 #define ISS_FP_IDF       (0x1 << ISS_FP_IDF_SHIFT)
1604
1605 #define ISS_FP_IXF_SHIFT 4
1606 #define ISS_FP_IXF       (0x1 << ISS_FP_IXF_SHIFT)
1607
1608 #define ISS_FP_UFF_SHIFT 3
1609 #define ISS_FP_UFF       (0x1 << ISS_FP_UFF_SHIFT)
1610
1611 #define ISS_FP_OFF_SHIFT 2
1612 #define ISS_FP_OFF       (0x1 << ISS_FP_OFF_SHIFT)
1613
1614 #define ISS_FP_DZF_SHIFT 1
1615 #define ISS_FP_DZF       (0x1 << ISS_FP_DZF_SHIFT)
1616
1617 #define ISS_FP_IOF_SHIFT 0
1618 #define ISS_FP_IOF       (0x1 << ISS_FP_IOF_SHIFT)
1619
1620 /*
1621  * Breakpoint Exception ISS (EL1)
1622  *  24     16          0
1623  * +---------+---------+
1624  * |000000000| Comment |
1625  * +---------+---------+
1626  *
1627  * where:
1628  *   Comment: Instruction Comment Field Value
1629  */
1630 #define ISS_BRK_COMMENT_MASK    0xFFFF
1631 #define ISS_BRK_COMMENT(x)      (x & ISS_BRK_COMMENT_MASK)
1632
1633
1634
1635
1636
1637 /*
1638  * Physical Address Register (EL1)
1639  */
1640 #define PAR_F_SHIFT 0
1641 #define PAR_F       (0x1 << PAR_F_SHIFT)
1642
1643 #define PLATFORM_SYSCALL_TRAP_NO 0x80000000
1644
1645 #define ARM64_SYSCALL_CODE_REG_NUM (16)
1646
1647 #define ARM64_CLINE_SHIFT 6
1648
1649 #if defined(APPLE_ARM64_ARCH_FAMILY)
1650 #define L2CERRSTS_DATSBEESV (1ULL << 2) /* L2C data single bit ECC error */
1651 #define L2CERRSTS_DATDBEESV (1ULL << 4) /* L2C data double bit ECC error */
1652 #endif
1653
1654 /*
1655  * Timer definitions.
1656  */
1657 #define CNTKCTL_EL1_PL0PTEN      (0x1 << 9)           /* 1: EL0 access to physical timer regs permitted */
1658 #define CNTKCTL_EL1_PL0VTEN      (0x1 << 8)           /* 1: EL0 access to virtual timer regs permitted */
1659 #define CNTKCTL_EL1_EVENTI_MASK  (0x000000f0)         /* Mask for bits describing which bit to use for triggering event stream */
1660 #define CNTKCTL_EL1_EVENTI_SHIFT (0x4)                /* Shift for same */
1661 #define CNTKCTL_EL1_EVENTDIR     (0x1 << 3)           /* 1: one-to-zero transition of specified bit causes event */
1662 #define CNTKCTL_EL1_EVNTEN       (0x1 << 2)           /* 1: enable event stream */
1663 #define CNTKCTL_EL1_PL0VCTEN     (0x1 << 1)           /* 1: EL0 access to virtual timebase + frequency reg enabled */
1664 #define CNTKCTL_EL1_PL0PCTEN     (0x1 << 0)           /* 1: EL0 access to physical timebase + frequency reg enabled */
1665
1666 #define CNTV_CTL_EL0_ISTATUS     (0x1 << 2)           /* (read only): whether interrupt asserted */
1667 #define CNTV_CTL_EL0_IMASKED     (0x1 << 1)           /* 1: interrupt masked */
1668 #define CNTV_CTL_EL0_ENABLE      (0x1 << 0)           /* 1: virtual timer enabled */
1669
1670 #define CNTP_CTL_EL0_ISTATUS     CNTV_CTL_EL0_ISTATUS
1671 #define CNTP_CTL_EL0_IMASKED     CNTV_CTL_EL0_IMASKED
1672 #define CNTP_CTL_EL0_ENABLE      CNTV_CTL_EL0_ENABLE
1673
1674 /*
1675  * At present all other uses of ARM_DBG_* are shared bit compatibly with the 32bit definitons.
1676  * (cf. osfmk/arm/proc_reg.h)
1677  */
1678 #define ARM_DBG_VR_ADDRESS_MASK64 0xFFFFFFFFFFFFFFFCull /* BVR & WVR */
1679
1680 #define MIDR_EL1_REV_SHIFT  0
1681 #define MIDR_EL1_REV_MASK   (0xf << MIDR_EL1_REV_SHIFT)
1682 #define MIDR_EL1_PNUM_SHIFT 4
1683 #define MIDR_EL1_PNUM_MASK  (0xfff << MIDR_EL1_PNUM_SHIFT)
1684 #define MIDR_EL1_ARCH_SHIFT 16
1685 #define MIDR_EL1_ARCH_MASK  (0xf << MIDR_EL1_ARCH_SHIFT)
1686 #define MIDR_EL1_VAR_SHIFT  20
1687 #define MIDR_EL1_VAR_MASK   (0xf << MIDR_EL1_VAR_SHIFT)
1688 #define MIDR_EL1_IMP_SHIFT  24
1689 #define MIDR_EL1_IMP_MASK   (0xff << MIDR_EL1_IMP_SHIFT)
1690
1691 #define MIDR_FIJI             (0x002 << MIDR_EL1_PNUM_SHIFT)
1692 #define MIDR_CAPRI            (0x003 << MIDR_EL1_PNUM_SHIFT)
1693 #define MIDR_MAUI             (0x004 << MIDR_EL1_PNUM_SHIFT)
1694 #define MIDR_ELBA             (0x005 << MIDR_EL1_PNUM_SHIFT)
1695 #define MIDR_CAYMAN           (0x006 << MIDR_EL1_PNUM_SHIFT)
1696 #define MIDR_MYST             (0x007 << MIDR_EL1_PNUM_SHIFT)
1697 #define MIDR_SKYE_MONSOON     (0x008 << MIDR_EL1_PNUM_SHIFT)
1698 #define MIDR_SKYE_MISTRAL     (0x009 << MIDR_EL1_PNUM_SHIFT)
1699 #define MIDR_CYPRUS_VORTEX    (0x00B << MIDR_EL1_PNUM_SHIFT)
1700 #define MIDR_CYPRUS_TEMPEST   (0x00C << MIDR_EL1_PNUM_SHIFT)
1701 #define MIDR_M9               (0x00F << MIDR_EL1_PNUM_SHIFT)
1702 #define MIDR_ARUBA_VORTEX     (0x010 << MIDR_EL1_PNUM_SHIFT)
1703 #define MIDR_ARUBA_TEMPEST    (0x011 << MIDR_EL1_PNUM_SHIFT)
1704
1705 #ifdef APPLELIGHTNING
1706 #define MIDR_CEBU_LIGHTNING   (0x012 << MIDR_EL1_PNUM_SHIFT)
1707 #define MIDR_CEBU_THUNDER     (0x013 << MIDR_EL1_PNUM_SHIFT)
1708 #define MIDR_TURKS            (0x026 << MIDR_EL1_PNUM_SHIFT)
1709 #endif
1710
1711 #ifdef APPLEFIRESTORM
1712 #define MIDR_SICILY_ICESTORM            (0x020 << MIDR_EL1_PNUM_SHIFT)
1713 #define MIDR_SICILY_FIRESTORM           (0x021 << MIDR_EL1_PNUM_SHIFT)
1714 #define MIDR_TONGA_ICESTORM             (0x022 << MIDR_EL1_PNUM_SHIFT)
1715 #define MIDR_TONGA_FIRESTORM            (0x023 << MIDR_EL1_PNUM_SHIFT)
1716 #endif
1717
1718
1719 /*
1720  * Apple-ISA-Extensions ID Register.
1721  */
1722 #define AIDR_MUL53            (1 << 0)
1723 #define AIDR_WKDM             (1 << 1)
1724 #define AIDR_ARCHRETENTION    (1 << 2)
1725
1726
1727 /*
1728  * CoreSight debug registers
1729  */
1730 #define CORESIGHT_ED  0
1731 #define CORESIGHT_CTI 1
1732 #define CORESIGHT_PMU 2
1733 #define CORESIGHT_UTT 3 /* Not truly a coresight thing, but at a fixed convenient location right after the coresight region */
1734
1735 #define CORESIGHT_OFFSET(x) ((x) * 0x10000)
1736 #define CORESIGHT_REGIONS   4
1737 #define CORESIGHT_SIZE      0x1000
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748 /*
1749  * ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0
1750  *
1751  *  63      24 23    20 19  16 15  12 11   8 7   4 3    0
1752  * +----------+--------+------+------+------+-----+------+
1753  * | reserved | atomic |crc32 | sha2 | sha1 | aes | res0 |
1754  * +----------+--------+------+------+------+-----+------+
1755  */
1756
1757 #define ID_AA64ISAR0_EL1_FHM_OFFSET    48
1758 #define ID_AA64ISAR0_EL1_FHM_MASK      (0xfull << ID_AA64ISAR0_EL1_FHM_OFFSET)
1759 #define ID_AA64ISAR0_EL1_FHM_8_2       (1ull << ID_AA64ISAR0_EL1_FHM_OFFSET)
1760
1761 #define ID_AA64ISAR0_EL1_ATOMIC_OFFSET 20
1762 #define ID_AA64ISAR0_EL1_ATOMIC_MASK   (0xfull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET)
1763 #define ID_AA64ISAR0_EL1_ATOMIC_8_1    (2ull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET)
1764
1765 #define ID_AA64ISAR0_EL1_CRC32_OFFSET  16
1766 #define ID_AA64ISAR0_EL1_CRC32_MASK    (0xfull << ID_AA64ISAR0_EL1_CRC32_OFFSET)
1767 #define ID_AA64ISAR0_EL1_CRC32_EN      (1ull << ID_AA64ISAR0_EL1_CRC32_OFFSET)
1768
1769 #define ID_AA64ISAR0_EL1_SHA3_OFFSET   32
1770 #define ID_AA64ISAR0_EL1_SHA3_MASK     (0xfull << ID_AA64ISAR0_EL1_SHA3_OFFSET)
1771 #define ID_AA64ISAR0_EL1_SHA3_EN       (1ull << ID_AA64ISAR0_EL1_SHA3_OFFSET)
1772
1773 #define ID_AA64ISAR0_EL1_SHA2_OFFSET   12
1774 #define ID_AA64ISAR0_EL1_SHA2_MASK     (0xfull << ID_AA64ISAR0_EL1_SHA2_OFFSET)
1775 #define ID_AA64ISAR0_EL1_SHA2_EN       (1ull << ID_AA64ISAR0_EL1_SHA2_OFFSET)
1776
1777 #define ID_AA64ISAR0_EL1_SHA1_OFFSET   8
1778 #define ID_AA64ISAR0_EL1_SHA1_MASK     (0xfull << ID_AA64ISAR0_EL1_SHA1_OFFSET)
1779 #define ID_AA64ISAR0_EL1_SHA1_EN       (1ull << ID_AA64ISAR0_EL1_SHA1_OFFSET)
1780
1781 #define ID_AA64ISAR0_EL1_AES_OFFSET    4
1782 #define ID_AA64ISAR0_EL1_AES_MASK      (0xfull << ID_AA64ISAR0_EL1_AES_OFFSET)
1783 #define ID_AA64ISAR0_EL1_AES_EN        (1ull << ID_AA64ISAR0_EL1_AES_OFFSET)
1784 #define ID_AA64ISAR0_EL1_AES_PMULL_EN  (2ull << ID_AA64ISAR0_EL1_AES_OFFSET)
1785
1786
1787
1788 #define APSTATE_G_SHIFT  (0)
1789 #define APSTATE_P_SHIFT  (1)
1790 #define APSTATE_A_SHIFT  (2)
1791 #define APSTATE_AP_MASK  ((1ULL << APSTATE_A_SHIFT) | (1ULL << APSTATE_P_SHIFT))
1792
1793
1794 #define ACTLR_EL1_EnTSO   (1ULL << 1)
1795 #define ACTLR_EL1_EnAPFLG (1ULL << 4)
1796 #define ACTLR_EL1_EnAFP   (1ULL << 5)
1797 #define ACTLR_EL1_EnPRSV  (1ULL << 6)
1798
1799 #define ACTLR_EL1_DisHWP_OFFSET  3
1800 #define ACTLR_EL1_DisHWP_MASK    (1ULL << ACTLR_EL1_DisHWP_OFFSET)
1801 #define ACTLR_EL1_DisHWP         ACTLR_EL1_DisHWP_MASK
1802
1803
1804
1805 #define AFPCR_DAZ_SHIFT  (0)
1806 #define AFPCR_FTZ_SHIFT  (1)
1807
1808 #if defined(HAS_APPLE_PAC)
1809 // The value of ptrauth_string_discriminator("recover"), hardcoded so it can be used from assembly code
1810 #define PAC_DISCRIMINATOR_RECOVER    0x1e02
1811 #endif
1812
1813
1814 #define CTR_EL0_L1Ip_OFFSET 14
1815 #define CTR_EL0_L1Ip_VIPT (2ULL << CTR_EL0_L1Ip_OFFSET)
1816 #define CTR_EL0_L1Ip_PIPT (3ULL << CTR_EL0_L1Ip_OFFSET)
1817 #define CTR_EL0_L1Ip_MASK (3ULL << CTR_EL0_L1Ip_OFFSET)
1818
1819
1820 #ifdef __ASSEMBLER__
1821
1822 /*
1823  * Conditionally write to system/special-purpose register.
1824  * The register is written to only when the first two arguments
1825  * do not match. If they do match, the macro jumps to a
1826  * caller-provided label.
1827  * The _ISB variant also conditionally issues an ISB after the MSR.
1828  *
1829  * $0 - System/special-purpose register to modify
1830  * $1 - Register containing current FPCR value
1831  * $2 - Register containing expected value
1832  * $3 - Label to jump to when register is already set to expected value
1833  */
1834 .macro CMSR
1835 cmp $1, $2
1836
1837 /* Skip expensive MSR if not required */
1838 b.eq $3f
1839 msr $0, $2
1840 .endmacro
1841
1842 .macro CMSR_ISB
1843 CMSR $0, $1, $2, $3
1844 isb sy
1845 .endmacro
1846
1847 /*
1848  * Modify FPCR only if it does not contain the XNU default value.
1849  * $0 - Register containing current FPCR value
1850  * $1 - Scratch register
1851  * $2 - Label to jump to when FPCR is already set to default value
1852  */
1853 .macro SANITIZE_FPCR
1854 mov $1, #FPCR_DEFAULT
1855 CMSR FPCR, $0, $1, $2
1856 .endmacro
1857
1858 /*
1859  * Family of macros that can be used to protect code sections such that they
1860  * are only executed on a particular SoC/Revision/CPU, and skipped otherwise.
1861  * All macros will forward-jump to 1f when the condition is not matched.
1862  * This label may be defined manually, or implicitly through the use of
1863  * the EXEC_END macro.
1864  * For cores, XX can be: EQ (equal), ALL (don't care).
1865  * For revisions, XX can be: EQ (equal), LO (lower than), HS (higher or same), ALL (don't care).
1866  */
1867
1868 /*
1869  * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX
1870  * $1 - CPU_VERSION_XX, e.g. CPU_VERSION_B1
1871  * $2 - GPR containing MIDR_EL1 value
1872  * $3 - Scratch register
1873  */
1874 .macro EXEC_COREEQ_REVEQ
1875 and $3, $2, #MIDR_EL1_PNUM_MASK
1876 cmp $3, $0
1877 b.ne 1f
1878
1879 mov $3, $2
1880 bfi  $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4
1881 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8
1882 cmp $3, $1
1883 b.ne 1f
1884 .endmacro
1885
1886 .macro EXEC_COREEQ_REVLO
1887 and $3, $2, #MIDR_EL1_PNUM_MASK
1888 cmp $3, $0
1889 b.ne 1f
1890
1891 mov $3, $2
1892 bfi  $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4
1893 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8
1894 cmp $3, $1
1895 b.pl 1f
1896 .endmacro
1897
1898 .macro EXEC_COREEQ_REVHS
1899 and $3, $2, #MIDR_EL1_PNUM_MASK
1900 cmp $3, $0
1901 b.ne 1f
1902
1903 mov $3, $2
1904 bfi  $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4
1905 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8
1906 cmp $3, $1
1907 b.mi 1f
1908 .endmacro
1909
1910 /*
1911  * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1
1912  * $1 - GPR containing MIDR_EL1 value
1913  * $2 - Scratch register
1914  */
1915 .macro EXEC_COREALL_REVEQ
1916 mov $2, $1
1917 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
1918 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
1919 cmp $2, $0
1920 b.ne 1f
1921 .endmacro
1922
1923 .macro EXEC_COREALL_REVLO
1924 mov  $2, $1
1925 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
1926 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
1927 cmp $2, $0
1928 b.pl 1f
1929 .endmacro
1930
1931 .macro EXEC_COREALL_REVHS
1932 mov $2, $1
1933 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
1934 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
1935 cmp $2, $0
1936 b.mi 1f
1937 .endmacro
1938
1939 /*
1940  * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX
1941  * $1 - GPR containing MIDR_EL1 value
1942  * $2 - Scratch register
1943  */
1944 .macro EXEC_COREEQ_REVALL
1945 and $2, $1, #MIDR_EL1_PNUM_MASK
1946 cmp $2, $0
1947 b.ne 1f
1948 .endmacro
1949
1950 /*
1951  * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1
1952  * $1 - GPR containing MIDR_EL1 value
1953  * $2 - Scratch register
1954  */
1955 .macro EXEC_PCORE_REVEQ
1956 mrs $2, MPIDR_EL1
1957 and $2, $2, #(MPIDR_PNE)
1958 cmp $2, xzr
1959 b.eq 1f
1960
1961 mov $2, $1
1962 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
1963 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
1964 cmp $2, $0
1965 b.ne 1f
1966 .endmacro
1967
1968 .macro EXEC_PCORE_REVLO
1969 mrs $2, MPIDR_EL1
1970 and $2, $2, #(MPIDR_PNE)
1971 cmp $2, xzr
1972 b.eq 1f
1973
1974 mov $2, $1
1975 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
1976 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
1977 cmp $2, $0
1978 b.pl 1f
1979 .endmacro
1980
1981 .macro EXEC_PCORE_REVHS
1982 mrs $2, MPIDR_EL1
1983 and $2, $2, #(MPIDR_PNE)
1984 cmp $2, xzr
1985 b.eq 1f
1986
1987 mov $2, $1
1988 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
1989 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
1990 cmp $2, $0
1991 b.mi 1f
1992 .endmacro
1993
1994 .macro EXEC_ECORE_REVEQ
1995 mrs $2, MPIDR_EL1
1996 and $2, $2, #(MPIDR_PNE)
1997 cmp $2, xzr
1998 b.ne 1f
1999
2000 mov $2, $1
2001 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
2002 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
2003 cmp $2, $0
2004 b.ne 1f
2005 .endmacro
2006
2007 .macro EXEC_ECORE_REVLO
2008 mrs $2, MPIDR_EL1
2009 and $2, $2, #(MPIDR_PNE)
2010 cmp $2, xzr
2011 b.ne 1f
2012
2013 mov $2, $1
2014 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
2015 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
2016 cmp $2, $0
2017 b.pl 1f
2018 .endmacro
2019
2020 .macro EXEC_ECORE_REVHS
2021 mrs $2, MPIDR_EL1
2022 and $2, $2, #(MPIDR_PNE)
2023 cmp $2, xzr
2024 b.ne 1f
2025
2026 mov $2, $1
2027 bfi  $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4
2028 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8
2029 cmp $2, $0
2030 b.mi 1f
2031 .endmacro
2032
2033 /*
2034  * $0 - GPR containing MIDR_EL1 value
2035  * $1 - Scratch register
2036  */
2037 .macro EXEC_PCORE_REVALL
2038 mrs $1, MPIDR_EL1
2039 and $1, $1, #(MPIDR_PNE)
2040 cmp $1, xzr
2041 b.eq 1f
2042 .endmacro
2043
2044 .macro EXEC_ECORE_REVALL
2045 mrs $1, MPIDR_EL1
2046 and $1, $1, #(MPIDR_PNE)
2047 cmp $1, xzr
2048 b.ne 1f
2049 .endmacro
2050
2051
2052
2053 /*
2054  * Macro that defines the label that all EXEC_COREXX_REVXX macros jump to.
2055  */
2056 .macro EXEC_END
2057 1:
2058 .endmacro
2059
2060 /*
2061  * Sets bits in an SPR register.
2062  * arg0: Name of the register to be accessed.
2063  * arg1: Mask of bits to be set.
2064  * arg2: Scratch register
2065  */
2066 .macro HID_SET_BITS
2067 mrs $2, $0
2068 orr $2, $2, $1
2069 msr $0, $2
2070 .endmacro
2071
2072 /*
2073  * Clears bits in an SPR register.
2074  * arg0: Name of the register to be accessed.
2075  * arg1: Mask of bits to be cleared.
2076  * arg2: Scratch register
2077  */
2078 .macro HID_CLEAR_BITS
2079 mrs $2, $0
2080 bic $2, $2, $1
2081 msr $0, $2
2082 .endmacro
2083
2084 /*
2085  * Clears bits in an SPR register.
2086  * arg0: Name of the register to be accessed.
2087  * arg1: Mask of bits to be cleared.
2088  * arg2: Value to insert
2089  * arg3: Scratch register
2090  */
2091 .macro HID_INSERT_BITS
2092 mrs $3, $0
2093 bic $3, $3, $1
2094 orr $3, $3, $2
2095 msr $0, $3
2096 .endmacro
2097
2098 /*
2099  * Macro intended to be used as a replacement for ERET.
2100  * It prevents speculation past ERET instructions by padding
2101  * up to the decoder width.
2102  */
2103 .macro ERET_CONTEXT_SYNCHRONIZING
2104 eret
2105 #if __ARM_SB_AVAILABLE__
2106 sb                              // Technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures
2107 #else /* __ARM_SB_AVAILABLE__ */
2108 isb                             // ISB technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures
2109 nop                             // Sequence of six NOPs to pad out and terminate instruction decode group */
2110 nop
2111 nop
2112 nop
2113 nop
2114 nop
2115 #endif /* !__ARM_SB_AVAILABLE__ */
2116 .endmacro
2117
2118 #endif /* __ASSEMBLER__ */
2119
2120 #define MSR(reg, src)  __asm__ volatile ("msr " reg ", %0" :: "r" (src))
2121 #define MRS(dest, reg) __asm__ volatile ("mrs %0, " reg : "=r" (dest))
2122
2123 #if XNU_MONITOR
2124 #define __ARM_PTE_PHYSMAP__ 1
2125 #define PPL_STATE_KERNEL    0
2126 #define PPL_STATE_DISPATCH  1
2127 #define PPL_STATE_PANIC     2
2128 #define PPL_STATE_EXCEPTION 3
2129 #endif
2130
2131
2132 #endif /* _ARM64_PROC_REG_H_ */